We can think of transistors as switches that allow either our source (logic 1) or drain (logic 0) to pass through depending on the value of the input to the transistor.
CMOS & Transistor Level Diagrams We can think of transistors as switches that allow either our source (logic 1) or drain (logic 0) to pass through depending on the value of the input to the transistor. If a logic 0 arrives at the input of a p-type transistor, then the switch is closed, meaning that the source can go through the transistor – but if a logic 1 arrives at its input, the switch becomes open, meaning that no source can go through. The n-type transistor, complementary to the p-type, is closed by a logic 1 and opened by a logic 0. The following table summarizes the characteristics of pMOS and nMOS: Value that closes switch
Position in circuit
p
0
top
n
1
bottom
Type
Picture
Note: Somewhat counter-intuitively, a closed switch means that source can go through the transistor.
A simple object we can use to remember these characteristics of pMOS and nMOS transistors is a bubble. Of the two types n and p, only one of them has a closed circle – or bubble – in the letter representing it: p. Incidentally, this is the transistor with the “bubble” placed on the input of its diagram. The value that closes this gate (or “goes through” the gate) is 0. Unlike ‘1,’ ‘0’ is bubble shaped. As for the position of the transistors in the circuit, the p type is on top as bubbles float to the top. Though this analogy helps us remember, it doesn’t have much of anything to do with the physical workings of CMOS transistors. When drawing transistor level diagrams, we place the source (commonly labeled Vdd) on top and the drain (commonly called “ground” and labeled GND) on the bottom. p-type transistors connect to the source whereas n-type transistors connect with the drain. That is, p-type transistors appear on the top of the circuit and n-type transistors appear on the bottom. We can use one of each of the complementary transistors to create a NOT gate, which simply outputs the inverted input. To do this, we attach a p-type transistor below the source and connect the bottom to an n-type transistor attached to ground. The input of the NOT gate is fed into the inputs of both transistors and the output of the NOT gate extends from the connection between the two transistors. See below.
If the output (labeled “inverted input” above) is connected to Vdd, then the output is a logic 1. If, on the other hand, the output is connected to GND, it is a logic 0. To verify that this is a functional design for a NOT gate, we consider the two possible inputs, 0 and 1, and see that their outputs are 1 and 0, respectively.
Now supposed we are tasked to analyze a transistor level circuit a bit more complicated than the one above and determine what kind of logical function it implements. By enumerating all combinations of inputs and finding their outputs, we can derive a formula (or another logic gate, perhaps). We can accomplish this using a truth table.
Here is our circuit…
…and here is our truth table: A 0 0 1 1
B 0 1 0 1
C (output) 1 1 1 0
Note: There are 22 = 4 possible combinations of input since there are two inputs and each input can be either a 0 or a 1.
We have four combinations of inputs to test. Here is one example, the case when A = 0 and B = 1. If we repeat this process for each of the four combination of input, we can fill the entire truth table above.
Though expressing the results of our completed truth table as a logic equation can be achieved using the sum of products method (to be introduced later in the course), we can see directly from the table that this circuit implements a NAND gate: an inversion of the AND gate.
