Jun 1, 2000 - U.S. Patent. Sep. 3, 2002. Sheet 6 0f 20. US 6,445,231 B1 u530 Evjo. _J. 3830 v 02.85. \ _'Evjo. 3830 c530. QL ...
US006445231B1
(12)
(54)
United States Patent
(10) Patent N0.:
Baker et al.
(45) Date of Patent:
US 6,445,231 B1 Sep. 3, 2002
DIGITAL DUAL-LOOP DLL DESIGN USING
5,355,037 A
* 10/1994 Andressen et al. ....... .. 307/158
COARSE AND FINE LOOPS
5,604,775 A
*
2/1997 Saitoh et a1. ............... .. 331/25
5,744,991 A
4/1998 Jefferson et a1. .......... .. 327/158
4/2000 Eto et al. .................. .. 327/158 8/2000 Keeth 61 al. .......... .. 370/517
(75)
Inventors; R, Jacob Baker, Meridian; Feng Lin, Boise, both of 1]) (Us)
6,049,239 A * 6,101,197 A
(73)
Assigneei Micron Technology, 1116030156,“)
6,297,680 B1 * 10/2001 KOIldO ..................... .. 327/276
6,130,552 A
* 10/2000 Jefferson et al.
..... .. 326/39
(Us) * cited by examiner
(*)
Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
USC. 154(b) by 0 days.
Primary Examiner—Dinh T. Le
(74) Attorney, Agent, or Firm—SchWegman, Lundberg, (21) APPL NO; 09/585,035
Woessner & Kluth PA.
(22) Filed:
(57)
Jun. 1, 2000
ABSTRACT
(51)
Int. Cl.7 ................................................ .. H03D 3/24
A dual-loop digital delay locked loop (DLL) is provided.
(52) (58)
us. Cl. ...................... .. 327/158; 327/278; 375/376 Field of Search ............................... .. 327/156, 158,
The DLL includes a Coarse 100p to produce a ?rst delayed Signal and Provides a Wide frequency lock range The DLL
327/149, 3, 12, 276, 278, 291; 375/376, 374
further includes a ?ne loop connected to the coarse loop to produce a second delayed signal and provides a tight lock ing. This dual-loop architecture can provide robust operation and tight synchronization over a Wide range of delay varia
(56)
References Cited
tions. U.S. PATENT DOCUMENTS 5,109,394 A
4/1992 Hjerpe et a1. ............. .. 375/119
34 Claims, 20 Drawing Sheets
1 O2 5
1 12
E
F ______ _ _ i _ _ _ “ _ 1
|
I
203
'
5
|
I
2P2
I
.
D
204
: 1I1
____S _
_
_
_
_
r
00
_
|
LATCH
:
I _
_
_
_
_
_
_
_
_
_
_
_
_
205
OUTPUT |
1
I
I 206
Q
|
@
I
L _ _ _ _
CIRCUIT
7 '
_ _
_
7
I
7 7 _ _ _ J
| |
_
I
I
CLKm
_
_
_
_
_5
_
_
_
_
_
_
_
_
_
2055b
1 COARSE
CLKin2-—‘—18
FINE
I
I
I
CLKout 7- ''00 P
1 I
: I
I
L
21 o I ‘
_
20550
I
5
—H+I—
CLKW"
_
211
208 ' '
_
LOOP
_
_I
| I
I ' DLL t
. '
I I
_
_
_
_
_
_
_
_
_
_
_
212
I I
I | I I _
_
_
_
I 214
_
_
_
_|
I
r207 I
I
OUTPUT
:
|
MODEL
:
|
I
|
|
21 6
|
I I_
°“
'
220 _
|
[I DS I
|
|
|
I
I
l
|
l
I
l
l
l
I
|
|
|
l
l
I
|
l
l
U.S. Patent
Sep. 3, 2002
Sheet 3 0f 20
00
US 6,445,231 B1
O0
U.S. Patent
Sep. 3, 2002
Sheet 6 0f 20
US 6,445,231 B1
_J
QL
v02.85 _‘E\vjo
c530
38 0
38 0
Evjo
u53 0
U.S. Patent
Sep. 3, 2002
Sheet 8 0f 20
US 6,445,231 B1
9:830 Bow
1 7:
£888
wow 88
mm.0_|._
5
m om
38:0
U.S. Patent
Sep. 3, 2002
Sheet 9 0f 20
.z|m.r
US 6,445,231 B1
30.30 F o
zTwlownm
iH/!5.6 ;
