Digital parameterizable VHDL module for ... - Semantic Scholar

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 9, SEPTEMBER 2011

Digital Parameterizable VHDL Module for Multilevel Multiphase Space Vector PWM Jacobo Álvarez, Óscar López, Member, IEEE, Francisco D. Freijedo, Member, IEEE, and Jesús Doval-Gandoy, Member, IEEE

Abstract—The multilevel multiphase technology combines the benefits of multilevel converters and multiphase machines. Recently, a new multilevel multiphase space vector pulsewidth modulation algorithm that is valid for any number of levels and phases was developed. In this paper, a generic digital VHDL module for such an algorithm is presented. This module is parameterizable in relation to the number of levels, the number of phases, and the number of bits of fractional part of the reference vector. It is also technology independent, reusable, and modular. This circuit has been tested by implementation in a field-programmable gate array, with the goal of a balance of speed and area optimization. It was tested by using a five-level five-phase inverter feeding an induction motor. Index Terms—Field-programmable gate array (FPGA), multilevel converter, multiphase machine, space vector pulsewidth modulation (SVPWM), VHDL.

I. I NTRODUCTION

M

ULTIPHASE electrical machines have many advantages when compared with their three-phase counterparts, such us improved reliability, increased fault tolerance, higher efficiency, and lower torque pulsations [1]. They have been found to be ideally suited for direct drives in marine propulsion applications [2]–[4] and for drive systems in safety-critical applications, such as the more-electric aircraft [5]–[9]. Other recent applications include electric vehicle propulsion [10]– [13] and locomotive traction [14], [15]. Multilevel converters have been extensively studied because they can manage high output voltages with voltage-limited devices, and they combine high efficiency with low harmonic distortion [16]. Recent industrial applications of multilevel inverters include induction high-power motor drives [17]– [19], hybrid electric vehicles [20], regenerative rectifiers [21], power conversion for renewable energy sources [22], [23], static synchronous compensators [24], [25], and fault-tolerant systems [26]. Multilevel multiphase variable-speed motor drives inherit the benefits of both technologies, with the drawback of an increased complexity of the modulation process because of Manuscript received March 15, 2010; revised July 26, 2010 and October 21, 2010; accepted November 29, 2010. Date of publication December 17, 2010; date of current version August 12, 2011. This work was supported by the Ministerio de Ciencia e Innovación under Project DPI2009-07004. The authors are with the Department of Electronics Technology, University of Vigo, 36310 Vigo, Spain (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2010.2100334

the large number of devices that must be controlled [27]. Carrier-based pulsewidth modulation (PWM) is a simple modulation technique that individually handles each leg of the converter. Therefore, its application multiphase converter is rather straightforward [28], [29]. The space vector PWM (SVPWM) simultaneously deals with all phases of the converter, and consequently, the extension of the three-phase SVPWM techniques to multiphase converters is more involved. In the last years, many multiphase SVPWM algorithms have been developed [30]–[42]. Most of them are devoted to two-level converters, and they make use of the multiple dq space concept [30]– [38]. The SVPWM techniques in [30] and [31] for five-phase converters, in [32] for seven-phase converters, and in [33] and [34] for nine-phase converters can only deal with the sinusoidal output voltage. The SVPWM algorithms presented in [35] and [36] allow us to add small amplitude harmonics to the output voltage. The extension of the sinusoidal output SVPWM algorithms to the multifrequency output was addressed in [37]. In [38], a general modulation algorithm for converters with an odd number of phases is presented. The algorithms in [39]–[41] can also deal with the multifrequency output, but they make use of the multidimensional approach introduced in [43]. The algorithm in [39] can be applied to two-level converters with any number of phases. Nevertheless, it is very time consuming, and its implementation using lookup tables (LUTs) requires a big amount of memory [44]. The SVPWM problem for the multilevel converters is addressed in [40] and [41], where two algorithms for converters with any number of levels and phases are presented. Both algorithms can handle the thousands of space vectors available in multilevel multiphase [45] converters with low computation and low memory requirements, which makes them very suitable for online algorithm implementation in a field-programmable gate array (FPGA). FPGAs stand out among the integrated circuits that allow the implementation of specific applications because they combine high performance, relatively low cost, enough flexibility, and short development process due to field programmability. Moreover, most of the FPGAs in the market are reprogrammable, which allows updating the implemented circuit with bug fixes and new enhancements [46], [47]. In the field of variable-speed motor drives, many experiences with FPGAs have been reported. The control for different permanent-magnet synchronous motors is implemented in an FPGA in [48]–[50]. In [51], an FPGA is used to implement a field-oriented controller based on a neural network for an induction motor drive. In [52], a direct-torque control for a sensorless induction motor

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ÁLVAREZ et al.: DIGITAL PARAMETERIZABLE VHDL MODULE FOR MULTILEVEL MULTIPHASE SVPWM

is implemented in an FPGA. A review of the FPGA-based current controllers for ac machine drives is presented in [53]. In [54], a digital PWM controller scheme for a brushless dc motor drive implemented in an FPGA is presented. The FPGA implementation of the SVPWM algorithms started with the two-level three-phase implementation realized in [55]. In [56]–[59], different multilevel SVPWM algorithms for three-phase converters were implemented in an FPGA. The two-level multiphase SVPWM algorithm presented in [60] and the multilevel multiphase SVPWM algorithms presented in [40] and [41] are verified using an FPGA. In [40] and [41], the circuits that were used to verify the modulation algorithms were specifically designed for a five-level five-phase converter, proving that they can be implemented online in a low-cost device. This paper presents a generic VHDL module for the multilevel multiphase SVPWM algorithm in [40]. The main contribution of this paper with respect to [40] is to detail a completely new and optimized VHDL implementation of the SVPWM technique. This implementation is parameterizable in relation to the number of levels, the number of phases, and the number of bits of the fractional part of the reference vector. The influence of the value of those parameters in the used FPGA resources, in the converter switching frequency, and in the resolution of the algorithm is discussed in this paper. A modular design, in which each step of the algorithm is carried out by an independent submodule, was developed. The SVPWM algorithm steps were analyzed to determine which submodules can run in parallel and which submodules must run sequentially to obtain a good area–speed tradeoff. All submodules were described using only the standard VHDL to obtain a technology-independent circuit. Since the SVPWM algorithm with switching state redundancy in [41] is based on [40], some of the circuits described in this paper can also be reused to implement such algorithm. This paper is organized as follows. The basics and the steps of the multilevel multiphase SVPWM algorithm in [40] are summarized in Section II. Section III describes the implementation in VHDL of the modulation algorithm. In Section IV, the implementation is verified by the simulation, and the circuit is tested in the laboratory by means of a five-level five-phase inverter. Section V presents the conclusion of this paper. II. M ULTILEVEL M ULTIPHASE SVPWM A LGORITHM In multiphase converters, the SVPWM is a multidimensional problem where the vector selection can be directly carried out in a multidimensional space [43]. In [40], the modulation problem of a P -phase converter is formulated in a P -dimensional space, and it is solved for multilevel topologies in which the output level of every phase is an integer multiple of a fixed voltage step Vdc . Flying capacitor, diode-clamped, cascaded full-bridge, and hybrid converters are included in such topologies [61]. Since the switching states of any power converter topology stay at discrete states, the SVPWM technique in [40] is used to synthesize a reference voltage vector vr = [vr1 , vr2 , . . . , vrP ]T by means of a sequence of space vectors during each modulation cycle. 1 2 P T , vsj , . . . , vsj ] must be applied Each space vector vsj = [vsj

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Fig. 1. Block diagram of the multilevel multiphase SVPWM. (a) Multilevel multiphase SVPWM based on a two-level SVPWM. (b) Block diagram of the two-level multiphase SVPWM.

during an interval tj in accordance with the following modulation law: vr =

P +1 j=1

vsj tj

P +1

tj = 1.

(1)

j=1

The aforementioned modulation problem is solved in [40] by means of a mathematical algorithm, with the block diagram shown in Fig. 1. This algorithm, which is based on a displacement plus a two-level multiphase SVPWM algorithm, has the following steps.1 1) Decompose the normalized reference vr into the sum of its integer part vi = [vi1 , vi2 , . . . , viP ]T and its fractional part vf = [vf1 , vf2 , . . . , vfP ]T by means of vi = integ(vr )

(2)

vf = vr − vi .

(3)

2) Calculate the permutation matrix P that sorts the vector vf in descending order in accordance with 1 1 P = (4) ˆf vf v ˆ f = [ˆ vf1 , vˆf2 , . . . , vˆfP ]T is the sorted vector in where v which 1 > vˆf1 ≥ · · · ≥ vˆfk−1 ≥ vˆfk ≥ · · · ≥ vˆfP ≥ 0.

(5)

1 All of the details of the mathematical justification of the modulation algorithm can be found in [40].

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3) Rearrange the rows of the upper triangular matrix ⎡ ⎤ 1 1 ... 1 ˆ =⎣ 1 ... 1⎦ D . .. . .. 0

TABLE I U SER PARAMETERS OF THE SVPWM C IRCUIT

(6)

to obtain matrix D by means of ˆ D = PT D.

(7)

4) Extract the sequence of the displaced switching vectors 1 2 P T , vdj , . . . , vdj ] from matrix D by taking into vdj = [vdj account that ⎤ ⎡ 1 1 ··· 1 ⎢ vd11 vd12 · · · vd1P +1 ⎥ ⎥ ⎢ ⎢ v 2 vd22 · · · vd2P +1 ⎥ (8) D = ⎢ d1 ⎥. ⎢ . .. .. ⎥ .. ⎦ ⎣ .. . . . vdP1 vdP2 · · · vdPP +1 5) Calculate the dwell time tj corresponding to each switchˆ f by ing vector from the components of the vector v means of ⎧ if j = 1 ⎨ 1 − vˆf 1 , (9) tj = vˆf j−1 − vˆf j , if 2 ≤ j ≤ P ⎩ vˆ P , if j = P + 1. f 6) Obtain the final switching vectors vsj by adding the integer part of the reference vi to the displaced switching vectors vdj vsj = vi + vdj .

(10)

Steps 2–5 correspond to the two-level multiphase SVPWM in Fig. 1(b), where vector vf is the reference voltage and vdj and tj are the output two-level space vectors and their corresponding dwell times, respectively. The multiphase modulation technique in [40] can be used with converters with any number of phases and levels, it is able to handle all switching states of the converter without discarding any one, and it provides a sorted switching vector sequence that minimizes the number of switchings. In addition, the algorithm is suitable for real-time implementation due to its low computational complexity. III. PARAMETERIZABLE SVPWM M ODULATOR

implementation because the values of the additional modulator parameters are automatically calculated. 2) Modular Design: Every component of the SVPWM circuit is designed to be a generic and parameterizable module, which makes them reusable. For example, there is only one VHDL file which describes a counter. This module is parameterized in a different way to make each distinct counter needed as part of the modulation circuit. The internal block diagram (structure) of the modulation algorithm described in [40] has been followed. Each of the six steps, which have been described in Section II, is carried out by an independent circuit. 3) Speed Optimization: The calculation time, which must be less than the converter switching period, depends on the actual values of the modulator parameters. The whole modulator circuit is synchronous, i.e., every component uses the same global clock signal. Therefore, the calculation time can be calculated by taking into account the clock frequency and the number of clock cycles needed by the modulation algorithm. In order to get an implementation tradeoff between speed and area, some operations are simultaneously executed, and some of them are sequentially executed. 4) Area Optimization: The partial results of the modulation algorithm are stored in distributed random-access memory (RAM). Such memory is based on the FPGA LUTs, which are actually tiny static RAMs (SRAMs). By using RAMs instead of registers, the required logical resources are drastically reduced. Nevertheless, it increases the calculation time of the circuit because of the sequential access to the data in the RAM. 5) Technology-Independent Description: All circuits are described entirely in VHDL, with no instantiations to any specific manufacturer components. Such a description allows the implementation of the modulation circuit in any FPGA, application-specific integrated circuit (ASIC), or equivalent digital integrated circuit.

A. Design Considerations In order to make a generic parameterizable circuit with a modular design, balanced in terms of speed and area and described with independence of the implementation technology, the following decisions were adopted. 1) Parameterizable Circuit: All of the components designed for the modulation circuit are parameterizable through the use of a VHDL package and the use of VHDL generics, which provides great flexibility. The user only needs to edit such package to select a new set of values for the parameters and to resynthesize the modulation circuit to obtain a new

B. Development of the SVPWM Circuit The parameters of the modulation circuit are the number of phases of system P , the number of levels of converter N , and the number of bits of the fractional part of the reference vector Q. All of these parameters are defined by the user in the part of the svpwm_constants.vhd VHDL package shown in Table I. All of the inner parameters of the circuit, such us the number of bits that is used to represent the levels of converter I, the number of bits K that is used to represent the number of phases, and the number of bits that is used to


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Fig. 3. Time line of the circuits.

Fig. 2.

Flow chart of the multilevel multiphase SVPWM module.

represent the number of phases plus one J, are also calculated in this package. The flow chart in Fig. 2 shows the different operations of the modulation circuit, which correspond with the algorithm steps described in Section II. The first step is realized by the Vr_dec circuit, the second step is realized by the Vf_sort circuit, the third step is realized by the D_calc circuit, the fourth step is realized by the Vd_extr circuit, the fifth step is realized by the t_calc circuit, and the sixth step is realized by the Vs_calc circuit. Since steps 2–5 correspond to an inner twolevel multiphase SVPWM algorithm, the circuits corresponding to those steps have been gathered in the 2P_SVPWM block. This block is parameterizable in relation to the number of phases P and the number of bits of the fractional part of the reference vector Q, and it can be used as a stand-alone with the twolevel multiphase converters. The whole multilevel multiphase SVPWM circuit is the NP_SVPWM block that groups all circuits. The flow chart in Fig. 2 shows that step 6 requires the data previously calculated in step 4, step 4 requires the data from step 3, and so on until step 1. Thus, circuits Vr_dec, Vf_sort, D_calc, Vd_extr, and Vs_calc must sequentially run, as shown in Fig. 3. Step 5 only requires the data calculated in step 2. Consequently, circuit t_calc can start after Vf_sort and can run in parallel with circuits D_calc, Vd_extr, and Vs_calc. Fig. 4 shows the hierarchical view of the NP_SVPWM module, with the internal circuits properly connected. It is composed of the following three main circuits: Vr_dec, 2P_SVPWM, and

Vs_calc. The operation of these circuits is sequential. The 2P_SVPWM circuit uses the values calculated by the Vr_dec circuit. Thus, it starts its operation once the Vr_dec circuit ends its operations. Similarly, the Vs_calc circuit uses the values calculated by the 2P_SVPWM circuit, so it starts its operation once 2P_SVPWM has ended its operation. To concatenate the sequential operation of the circuits, each one has two synchronizing signals (Init and End). Usually, the End signal of one circuit is connected to the Init signal of the following circuit. It means that the internal circuits are inactive most of the time. This consideration, joined to the use of synchronous circuits that avoid the propagation of unwanted glitches, reduces the FPGA dynamic power consumption due to the SVPWM process. The 2P_SVPWM block includes the following circuits: Vf_sort, D_calc, Vd_extr, and t_calc. The t_calc circuit runs in parallel with the D_calc and Vd_extr circuits. Therefore, the End signal of the Vf_sort circuit is connected to the Init signals of the D_calc and t_calc circuits. The End signal of the 2P_SVPWM circuit is activated only when Vd_extr ends its operations, because this circuit always ends the calculations after t_calc, as shown in Table III. All of the internal circuits in Fig. 4 have the basic structure shown in Fig. 5. They are controlled by a synchronous finitestate machine (FSM) that receives the Init order, controls the processing unit, and generates the End signal. The processing unit takes the input data In(Ain ) by means of an addressing signal Ain , and it makes the calculations and stores the results in a dual-port RAM Out(Aout ). The first addressing port of the RAM is a write-only port that is internally used to store the calculation results, and the second addressing port Aout is a read-only port that can be accessed by external circuits. Dualport RAMs are usual components physically included in most of the modern FPGAs, and of course, they can be included in any digital ASIC. Nevertheless, the SVPWM circuit is always implementable due to the VHDL code, which has been designed to be independent from any manufacturer libraries. However, if dual-port RAMs are not physically available, the implementation would use more hardware resources. C. Description of the Internal Circuits 1) Vr_dec: This circuit decomposes the normalized reference into its integer part vi and its fractional part vf according to (2) and (3). Therefore, it splits the I + Q bits of each component of the reference vector in two parts: the first I bits

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Fig. 4. Hierarchical view of the multilevel multiphase SVPWM circuit. (a) NP_SVPWM circuit. (b) 2P_SVPWM circuit.

Fig. 5. Basic structure of the internal circuits.

corresponding to the integer part and the last Q bits corresponding to the fractional part. The circuit reads the components of the reference vector Vr(kr) by means of the addressing signal kr. The resulting vectors vi and vf are separately stored in the dual-port RAMs Vi(ki) and Vf(kf) that can be addressed by means of ki and kf, respectively. Each memory position stores one vector component. The Vr_dec circuit is composed of one counter, two dual-port RAMs, and one FSM. 2) Vf_sort: This circuit sorts the components of the fractional part of the reference vector vf in descending order, according to (5), using the bubble sort algorithm. This sorting algorithm starts at the beginning of the vector. It compares the first two components (phases), and if the first one is lower than the second one, it swaps them. It continues to do this for each pair of adjacent components to the end of the vector. It then starts again with the first two components, repeating until no


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TABLE II S IZE OF THE M AIN BASIC C OMPONENTS U SED BY THE I NTERNAL C IRCUITS

swaps have occurred on the last pass. The sorted vector is stored in the RAM Vo(ko), and the final position of each component at the end of the sort process, with respect to its initial position, is stored in the RAM Id(kid). Both RAMs have two read ports and one write port. The read ports are used by the processing unit to access the dual-port RAM and to easily swap the vector components with the help of an auxiliary register. The Vf_sort circuit is composed of two counters, five multiplexers, two registers, one magnitude comparator, two dual-port RAMs, and one FSM. 3) D_calc: This circuit calculates matrix D in accordance with (7). Matrix PT reversely rearranges the rows of matrix ˆ with respect to the sort process of the fractional part. For D example, if the third component of vector vf finally takes the fifth position, then the fifth row of matrix D will finally have ˆ the value of the third row of the upper triangular matrix D. ˆ with Consequently, this circuit rearranges the rows of matrix D the information stored in Id(kid). Each row of the resulting matrix D is stored in a memory position of the dual-port RAM ˆ and D, ˆ which is useful D(row). The first row of matrices D in algorithm demonstration, was not taken into account in the implementation because this row is always constant, and it is not needed in extracting the displaced switching vectors vd . The D_calc circuit is composed of one counter, one register, one dual-port RAM, and one FSM. 4) Vd_extr: This circuit extracts the displaced switching vector sequence {vdj } from the coefficient matrix D according k to (8). The values of the components vdj of each vector are stored bit by bit in the 2-D RAM Vd(kd, jd). This simplifies the later calculations of the switching vector sequence {vsj }. A parameterizable 2-D dual-port RAM, with row and column addresses, was defined in VHDL. The parameters are the row size, the column size, and the number of bits of each memory position. Physically, the memory is implemented as a conventional RAM in which the actual address is obtained by combining both the row and column addresses by the equation address = row_address × 2column_size + column_address. The column address jd is used to access the jth vector of the displaced vector sequence {vsj }, and the row address kd is k used to access the k component vdj of that vector. The Vd_extr circuit is composed of two counters, one register, one dual-port RAM, and one FSM.

5) t_calc: This circuit calculates the dwell times tj from ˆ f in accordance with (9). The result is stored the sorted vector v in the dual-port RAM t(j). The t_calc circuit is composed of one counter, two registers that are used to store the minuend and the subtrahend, one subtracter, one dual-port RAM, and one FSM. The minuend register is initialized to a value of one to ease the calculation of the first switching time t1 = 1 − vˆf1 . 6) Vs_calc: This circuit calculates the final switching vector sequence {vsj } in accordance with (10). The results are stored component by component in the 2-D dual-port RAM k of the final Vs(ks, js). Therefore, to access the component vsj switching sequence, it is necessary to provide the row address ks and column address js, as with the {vdj } sequence in the Vd_extr circuit. The Vs_calc circuit is composed of two counters, one adder, one dual-port RAM, and one FSM. All signals, except Vr(kr), t(j), and Vf(kf), are integer numbers represented with the number of bits shown in Fig. 4. These three signals are real numbers that are represented in the fixed-point format. Signal Vr(kr) is represented in two’s complement using I bits for the integer part and Q bits for the fractional part. Signal Vf(kf) is a positive real number in the range [0, 1), with all Q bits representing the fractional part. Signal t(j) is a real number in the range [0, 1], using one bit to represent the integer part and Q bits to represent the fractional part. The size of the main basic components used by the internal circuits is detailed in Table II. It depends basically on the number of phases, directly through parameter P , and indirectly through variables J and K. The number of bits of the reference vector Q and the number of levels through variable I have a lower influence in the circuit size. Table III shows the number of clock cycles nclk used by the internal circuits. Related to this table, it is necessary to highlight the following issues. 1) The number of clock cycles n2 used by the Vf_sort circuit is not constant. It depends on the initial sorting of the numbers. 2) The value 2i in every circuit is due to two initial clock cycles, which simultaneously elapse for all circuits. Therefore, both cycles do not accumulate to the total delay of the whole circuit.

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TABLE III N UMBER OF C LOCK C YCLES

TABLE V M AXIMUM C ONVERTER S WITCHING F REQUENCY W ITH THE NP_SVPWM C IRCUIT

TABLE IV FPGA R ESOURCES U SED BY THE NP_SVPWM C IRCUIT

3) The number of clock cycles n5 elapsed by the t_calc circuit has not been added to the total number of clock cycles elapsed by the 2P_SVPWM and NP_SVPWM circuits, i.e., nclk = n2 + n3 + n4 and nclk = n1 + n2 + n3 + n4 + n6 . It is because t_calc simultaneously runs with D_calc and Vd_extr, and the sum of the number of clock cycles used by these two circuits is always greater than the number of clock cycles used by the t_calc circuit (n3 + n4 > n5 ). Fig. 3 shows the number of cycles elapsed by the circuits in the particular case P = 3. Since the circuit is synchronous, the calculation time can be calculated by taking into account the clock frequency and the number of clock cycles needed by the modulation algorithm. It is also important to remark that only the number of phases P has influence on the circuit speed. D. Implementation Results The parameterizable NP_SVPWM circuit has been implemented in FPGA XC3S200-FT256-4. This FPGA, which belongs to the Spartan 3 family from Xilinx, has basic configurable logic block cells called as slices, composed mainly of two LUTs that are 16 b (16 × 1) and two flip-flops. This is the second smallest FPGA of the family, which has 1920 slices (thus, 3840 LUTs and 3840 slice flip-flops). Table IV shows the resources used by the NP_SVPWM circuit, with different parameter values, obtained through the Foundation ISE 10.1 tool. The parameters that have a major influence are the number of phases P and the number of bits Q. The number of levels N affects in a lesser extent, and if its increment does not require more bits for its representation, it does not affect the amount of resources used at all. For instance, in the five-phase case, the resources used by the circuit for five and seven levels are the same. In the same case, with nine levels, the resources used increase a little because of the extra bit required

to represent the number nine. Any other FPGA with the same SRAM technology from other manufacturer will give similar implementation results. As an example, the implementation of the NP_SVPWM circuit with N = 5, P = 5, and Q = 9 in FPGA EP2C5F256C6, which is the smallest FPGA of the Cyclone II family from Altera, uses 242 logic elements (out of 4608), 136 flip-flops (out of 4608), and 768 memory bits (out of 119 808). Table V shows the maximum converter switching frequency fs that can be achieved with the NP_SVPWM circuit. The value of fs is fs ≤

1 nclk τclk

(11)

where the number of clock cycles nclk is obtained from Table III and the minimum applicable clock period τclk is extracted from the implementation tool report. The maximum switching frequency of the modulator circuit in Table V is, in all cases, higher than the typical switching frequencies used with the multilevel power converters. The implementation results, i.e., the resources used and the clock delay, can slightly vary from one implementation to another, with no circuit modifications due to the nondeterministic nature of the place and route algorithms. The time resolution of the modulation circuit is given by δ = max(τclk , τm ), where τclk is the clock period applied to the circuit and τm is the mathematical resolution of the algorithm. The value of τm can be calculated from the converter switching frequency and the parameter Q as τm =

1 . 2Q fs

(12)

IV. V ERIFICATION The NP_SVPWM circuit was tested by simulation and in the laboratory with a five-level five-phase converter. Nine bits were considered to represent the fractional part of the reference vector. Therefore, the svpwm_constants.vhd package is configured with N = 5, P = 5, and Q = 9, as shown in Table I. A. Simulation Results Figs. 6 and 7 show the simulation results of the multilevel multiphase SVPWM circuit. All of them have been obtained


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Fig. 6. Simulation results for the five-level five-phase NP_SVPWM circuit. (a) Input values for the reference vector vr . (b) Output values for the switching vector sequence {vsj } and the switching times tj .

lator calculations have ended. The activation of the End signal, which indicates the end of the calculations, is not shown in the figure. The results match the theoretical results obtained in the example in [40] vs1 = [1, 1, −1, −2, −1]T

t1 = 0.25

T

vs2 = [1, 1, −1, −2, 0]

t2 = 0.32

vs3 = [2, 1, −1, −2, 0]T

t3 = 0.01

vs4 = [2, 1, −1, −1, 0]

t4 = 0.15

vs5 = [2, 1, 0, −1, 0]T

t5 = 0.14

vs6 = [2, 2, 0, −1, 0]

t6 = 0.13.

T

T

Fig. 7.

Simulated filtered output leg voltages with a sinusoidal reference.

through the Modelsim simulation tool from Mentor Graphics in its XE (Xilinx Edition) version. Fig. 6 shows the post place and route simulation corresponding to one switching cycle. The values of the reference vector vr , the switching vectors vsj , and the dwell times tj are included in binary and real formats to facilitate the circuit analysis. The values in real format have been obtained through the VHDL test bench because the real format is not synthesizable in VHDL. In Fig. 6(a), the activation of the Init signal indicates the beginning of the calculations. After that, the reference vector component values are read by the Vr_dec circuit. The reference values vra = 1.43, vrb = 1.13, vrc = −0.73, vrd = −1.58, and vre = −0.25 match those of the example in [40]. Fig. 6(b) shows the final values of the final switching vector component values (Vs and Vs_int) and their corresponding switching times (t and t_real) once the modu-

(13)

Fig. 7 shows the functional simulation of the SVPWM circuit when the reference is a balanced five-phase sinusoidal wave. In this figure, Vr(a) stands for the reference voltage of phase a vra . The reference for the other four phases Vr(b), Vr(c), Vr(d), and Vr(e), not shown in the figure, is equal to Vr(a) with the appropriate phase offset. Traces Vo(a) and Vo(b) are the simulated filtered output voltages of phases a and b, respectively. Those signalshave been calculated through the k tj . The trace Vo(a) is equal VHDL test bench as vok = 6j=1 vsj to the reference Vr(a) delayed with one sampling cycle. Vo(b) is equal to Vo(a) shifted 2π/5 rad. The rest of the output signals, not shown in Fig. 7, is also correct. Therefore, the SVPWM modulator has been properly described in VHDL. All simulations in this section have also been carried out with the Altera edition of the Modelsim simulation tool for FPGA EP2C5F256C6, providing the same results. B. Experimental Results The NP_SVPWM circuit was tested by using the experimental setup shown in Fig. 8, which includes a dSPACE platform, an FPGA board, an inverter, and a load. The dSPACE

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Fig. 8. Experimental test setup. (a) Diagram. (b) Photograph.

Fig. 9. Five-level five-phase cascaded full-bridge inverter.

DS1103 PPC Controller Board provides the reference vectors to the modulation circuit. The SVPWM circuit has been implemented in an S3 board from Digilent Inc., which includes the XC3S200FT256-4 FPGA considered in Section III-D. Two auxiliary boards have been built to adapt the FPGA signals (3.3 V) to the dSPACE control board and the optical link that sends the trigger signals to the inverter (both 5 V). The 74LVC4245A integrated circuit was used to shift the voltage levels. The trigger signals generated by the FPGA control the 40 transistors of the five-level five-phase cascaded full-bridge inverter shown in Fig. 9, which has 3125 different switching states [45]. The dc source voltage of each full-bridge cell is 60 V. Therefore, the inverter voltage step Vdc is also 60 V. The load is a five-phase distributed–concentrated winding induction

motor of four poles in parallel with a five-phase RL circuit. This motor was specifically built for the tests by rewinding the stator phases on the 30 stator slots of one 1-kW three-phase motor. Each phase of the RL circuit is an L = 15 mH series connected with R = 300 Ω. In order to test the new VHDL module, two specific auxiliary VHDL modules (dSPACE_com and Trigger) were developed to interface the NP_SVPWM circuit with the dSPACE control board and the power converter, respectively. Their connection inside the FPGA is shown in Fig. 10. 1) dSPACE_com: This circuit receives the normalized reference vector vr given by the dSPACE control system and stores its components in a dual-port RAM that is read by the NP_SVPWM circuit. The dSPACE_com circuit uses a two-phase communication protocol (validation–acknowledge) specifically designed for this application. It is composed of various synchronizing flip-flops, one edge detector, one timer, one counter, one dual-port RAM, and one FSM. 2) Trigger: This circuit reads the dual-port RAMs Vs(ks, js) and t(j) that belong to the NP_SVPWM circuit to calculate the trigger signals T for the power transistors. Since the relationship between the transistor trigger signals and the converter output levels is different for each multilevel converter topology [61], this circuit is specifically designed for a five-level cascaded full-bridge inverter. It is composed of the following four subcircuits: Switch_timer, Change_instant, Switch_state_sequencer, and Trigger_signals. Switch_timer calculates the current time within the switching period by counting the pulses of the clk signal. The Change_instant circuit calculates the absolute time instants in which the converter must change the switching state. The Switch_state_sequencer circuit compares the absolute time instants with the current time provided by Switch_timer to determine the current switching vector, i.e., the current output level of every phase. The Trigger_signals circuit translates the current output level into trigger signals. Additionally, it inserts the dead times by delaying the rising edges of the complementary trigger signals. The Trigger circuit is composed of 5 + 8P counters, 3 + 17P registers, 2P + 2 dual-port RAMs, 1 + 9P multiplexers, two comparators, 4P combinatorial functions, and one FSM. As shown in Table V, the modulation circuit can deal with a switching frequency of up to 362 kHz. Nevertheless, a switching frequency of 10 kHz was used in the experimental test because the dSPACE platform is slower (it limits the switching frequency to 10.4 kHz). In this case, from (12), the mathematical resolution of the algorithm is τm = 195 ns, which is longer than the FPGA clock period τclk = 20 ns. Thus, the time resolution of the circuit is also δ = 195 ns. Figs. 11 and 12 show the experimental measurements obtained when a purely sinusoidal voltage reference is considered. In Fig. 11, channel 1 shows the leg voltage of phase a, channel 2 is the same signal after being filtered, channel 3 shows the current drawn by phase a of the motor, and channel 4 is the voltage across the resistor of the RL load in parallel with the motor. The harmonic content of the output voltage is depicted in Table VI. The amplitude of the low-order harmonics is below 1% of the fundamental, and the total harmonic distortion of the


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Fig. 10. Control.

Fig. 11. Voltages and current of phase a.

Fig. 12. Trajectories of the output voltage vector in the dq planes. TABLE VI H ARMONIC C ONTENT OF THE O UTPUT L EG VOLTAGE WAVEFORM

voltage waveform is 2.44%. The current drawn by the motor (CH3) presents a nonsinusoidal shape that is caused by the load characteristic of the motor operated in open loop (probably by mechanical ringing). The current drawn by the RL load, which has the same shape as that of the resistor voltage (CH4), does not show a low harmonic distortion as expected. Fig. 12 shows the trajectories of the output voltage vector in the dq planes. The gray trace corresponds to the output voltage, and the black trace corresponds to the filtered output voltage. The later trajectory is

a circle in the d1 –q1 plane and a point in the d2 –q2 plane that corresponds to a pure sinusoidal output, which proves that the system properly operates. The NP_SVPWM module was tested with a converter with externally supported dc sources, which alleviates the voltage capacitor balancing issue present in a number of applications. The SVPWM algorithm in [40] is a simple modulation technique that generates an output phase-to-neutral voltage that is equal to the reference phase-to-neutral voltage. Consequently, this multilevel multiphase algorithm does not handle jointphase redundancy, and it cannot integrate a general balancing capacitor technique. Nevertheless, in multilevel topologies with per-phase redundancy [61], such as flying capacitor and cascaded full-bridge converters, the Trigger_signals subcircuit in the Trigger auxiliary circuit can be designed to select the appropriate trigger signals from the switching vectors to the balance voltage capacitors. If the neutral voltage is not a constraint, then the SVPVM algorithm in [41], which handles jointphase redundancy, is a more appropriate modulation technique because it has a degree of freedom that can be used for voltage capacitor balancing. Additionally, the NP_SVPWM module requires balanced dc voltages. In the case of unbalanced dc voltages, the output voltage distortion can be reduced with the specific multilevel multiphase feedforward SVPWM technique in [62]. V. C ONCLUSION A generic digital parameterizable VHDL module for the recent multilevel multiphase SVPWM algorithm has been presented. The parameters of the module are the number of phases, the number of levels of the converter, and the number of bits of the fractional part of the reference vector. The new module has a modular design. It is technology independent as it was described using the standard VHDL sentences. Thus, although it was optimized for the common SRAM FPGAs, it can be synthesized with programmable devices of any manufacturer or even ASICs. The hierarchical structure, the logical resources, and the calculation time of the circuit are detailed throughout this paper. The resources used basically depend on the number of phases of the inverter and the number of bits used to represent the fractional part of the reference

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vector. The number of clock cycles only depends on the number of phases. Thus, the maximum modulation frequency that is achievable with the circuit mainly depends on the number of phases. The digital parameterizable VHDL module has been implemented in a low-cost SRAM FPGA, and it has been tested with a five-level five-phase voltage source inverter. R EFERENCES [1] E. Levi, “Multiphase electric machines for variable-speed applications,” IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 1893–1909, May 2008. [2] F. Terrien, S. Siala, and P. Noy, “Multiphase induction motor sensorless control for electric ship propulsion,” in Proc. IEE Int. Conf. PEMD, Edinburgh, U.K., Mar. 31–Apr. 2, 2004, vol. 2, pp. 556–561. [3] D. Gritter, S. Kalsi, and N. Henderson, “Variable speed electric drive options for electric ships,” in Proc. IEEE ESTS, Philadelphia, PA, 2005, pp. 347–354. [4] L. Parsa and H. A. Toliyat, “Five-phase permanent magnet motor drives for ship propulsion applications,” in Proc. IEEE ESTS, Philadelphia, PA, Jul. 25–27, 2005, pp. 371–378. [5] G. Atkinson, B. Mecrow, A. Jack, D. Atkinson, P. Sangha, and M. Benarous, “The design of fault tolerant machines for aerospace applications,” in Proc. IEEE IEMDC, San Antonio, TX, May 15–18, 2005, pp. 1863–1869. [6] J. Bennett, B. Mecrow, A. Jack, D. Atkinson, C. Sewell, G. Mason, S. Sheldon, and B. Cooper, “Choice of drive topologies for electrical actuation of aircraft flaps and slats,” in Proc. IEE Int. Conf. PEMD, Edinburgh, U.K., Mar. 31–Apr. 2, 2004, vol. 1, pp. 332–337. [7] G. Atkinson, B. Mecrow, A. Jack, D. Atkinson, P. Sangha, and M. Benarous, “The analysis of losses in high-power fault-tolerant machines for aerospace applications,” IEEE Trans. Ind. Appl., vol. 42, no. 5, pp. 1162–1170, Sep./Oct. 2006. [8] X. Huang, K. Bradley, A. Goodman, C. Gerada, P. Wheeler, J. Clare, and C. Whitley, “Fault-tolerant brushless dc motor drive for electrohydrostatic actuation system in aerospace application,” in Conf. Rec. IEEE IAS Annu. Meeting, Tampa, FL, Oct. 8–12, 2006, vol. 1, pp. 473–480. [9] C. Gerada and K. J. Bradley, “Integrated PM machine design for an aircraft EMA,” IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3300–3306, Sep. 2008. [10] M. G. Simoes and P. Vieira, “A high-torque low-speed multiphase brushless machine—A perspective application for electric vehicles,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1154–1164, Oct. 2002. [11] S. Jiang, K. Chau, and C. Chan, “Spectral analysis of a new six-phase pole-changing induction motor drive for electric vehicles,” IEEE Trans. Ind. Electron., vol. 50, no. 1, pp. 123–131, Feb. 2003. [12] R. Bojoi, A. Tenconi, F. Profumo, and F. Farina, “Dual-source fed multiphase induction motor drive for fuel cell vehicles: Topology and control,” in Proc. IEEE PESC, Recife, Brazil, Jun. 11–16, 2005, pp. 2676–2683. [13] S. Niu, K. Chau, D. Zhang, J. Jiang, and Z. Wang, “Design and control of a double-stator permanent-magnet motor drive for electric vehicles,” in Conf. Rec. IEEE IAS Annu. Meeting, New Orleans, LA, Sep. 23–27, 2007, pp. 1293–1300. [14] M. Steiner, R. Deplazes, and H. Stemmler, “New transformerless topology for ac-fed traction vehicles using multi-star induction motors,” EPE J. (Eur. Power Electron. Drives J.), vol. 10, no. 3/4, pp. 45–53, Sep. 2000. [15] M. Abolhassani, “A novel multiphase fault tolerant high torque density permanent magnet motor drive for traction application,” in Proc. IEEE IEMDC, San Antonio, TX, May 15–18, 2005, pp. 728–734. [16] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002. [17] J. Rodriguez, S. Bernet, B. Wu, J. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007. [18] M. Rotella, G. Penailillo, J. Pereda, and J. Dixon, “PWM method to eliminate power sources in a non-redundant 27-level inverter for machine drive applications,” IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 194– 201, Jan. 2009. [19] G. Baoming, F. Z. Peng, A. T. de Almeida, and H. Abu-Rub, “An effective control technique for medium-voltage high power induction motor fed by cascaded neutral point clamped inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2659–2668, Aug. 2010.

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Jacobo Álvarez received the M.Sc. and Ph.D. degrees from the University of Vigo, Vigo, Spain, in 1991 and 1995, respectively. He has been a Full Professor with the Department of Electronic Technology, University of Vigo, since 1997. His main topics of interest are programmable logic devices and field-programmable gate array architectures and design methods applied to industrial control problems.

Óscar López (M’05) received the M.Sc. and Ph.D. degrees from the University of Vigo, Vigo, Spain, in 2001 and 2009, respectively. Since 2004, he has been an Assistant Professor with the Department of Electronics Technology, University of Vigo. His research interests include the ac power switching converter technology.

Francisco D. Freijedo (M’07) received the M.Sc. degree in physics from the University of Santiago de Compostela, Santiago de Compostela, Spain, in 2002 and the Ph.D. degree from the University of Vigo, Vigo, Spain, in 2009. Since 2005, he has been an Assistant Professor with the Department of Electronics Technology, University of Vigo. His research interests include quality problems, grid-connected switching converters, ac power conversion, and flexible ac transmission systems.

Jesús Doval-Gandoy (M’99) received the M.Sc. degree from the Polytechnic University of Madrid, Madrid, Spain, in 1991 and the Ph.D. degree from the University of Vigo, Vigo, Spain, in 1999. From 1991 to 1994, he worked at the industry. He is currently an Associate Professor with the Department of Electronics Technology, University of Vigo. His research interests include ac power conversion.