EMI Modeling of Integrated Circuits using pattern simulation COURAU Lionel, GERBERT-GAILLARD Brice STMicroelectronics 850, Rue Jean Monnet F-38926 CROLLES CEDEX
[email protected] Abstract: Due to the increasing speed and the low voltage supply of CMOS processes, Integrated Circuits (ICs) are more and more confronted to ElectroMagnetic Compatibility (EMC) problems. Noise emission is propagated through ICs by coupling, routing capacitors and package parasitics. These effects often leads to signal integrity failures, and noise emission level overruns. To study this effect at chip level, from specifications to layout finishing, a new noise simulation has been developped in order to be fast and accurate. Then some comparisons have been made with standard spice simulations showing the efficiency of this flow.
1. Introduction The increasing speed of ICs combined with a high level of integration always lead to strongest noise, therefore problems appear concerning signal integrity and emission. Nevertheless, standard simulation methods cannot be applied on noise analysis, either due to the slowness (spice simulator) or the lack of accuracy (gate level simulator). This paper deals with a new simulation strategy aimed at performing analog simulations combined with behavioral considerations. As this method must be applied at any level of chip design, a modular approach has been chosen. After detailing the drawbacks of standard approaches applied to noise simulation, we will focus on the new methodology, and then some comparisons with standard spice simulations will be presented.
2. Standard simulation flows 2.a Spice simulations A standard spice simulation flow can be applied using next inputs: · · · ·
Partial chip netlist (input-outputs buffers and/or some core blocks) Netlist of the package parasitics (R, L, C modeling) Internal decoupling capacitance (extracted) Some other noise parameters may be considered
Next graph is an example of a very simple chip configuration:
Figure 1: spice simulation configuration for noise level simulation of a chip
Spice simulators can handle such netlist; the accuracy is correct for noise simulations. On the opposite, this flow has severe drawbacks when applied on a whole chip: · · ·
The time simulation is directly proportional to the number of transistors and passive elements included in the netlist. Small circuits take several days to be simulated; larger ones cannot be used because of hardware limitations. If one parameter changes in the specifications or during the chip design, the whole simulation must be performed again. It is impossible to take into account supplies routing, RC extractions and other parasitic noise parameters, due to the exponential netlist size.
2.b Gate level simulations For large-scale chips, gate level simulations can replace spice simulations for timing analysis. Instead of taking into account the voltage of each node in the chip, it only simulates digital levels. This method leads to fast simulations with a correct accuracy, even for a large number of gates. Unfortunately it cannot take into account all the noise parameters such as: supply current, package parasitics, RC routing extraction, supply routing grid, etc… These kinds of simulation are not well fitted for noise simulations; therefore a new noise simulation approach has been developed.
3. Modular simulation flow In order to be effective at any stage of chip design, the simulation should be modular, that is to say each step of simulation could be re-used. For this reason, the new simulation flow integrates two important parameters:
3.a Current waveform extracted from pattern simulation The current waveform generation is made using HSIM spice simulator from NASSDA Corporation. Most of spice softwares can handle vector file stimuli, corresponding to the input switching nodes of the core logic.
Netlist or schematic HSIM
Transient simulation
Input Stimuli
Current waveform
Figure 2: current waveform extraction based on pattern simulation
The simulation result is stored in a file and will be re-used in a global noise simulation as a waveform current generator.
3.b Power/ground equivalent impedance of the block The current waveform in stand-alone configuration is not realistic, because the current consumption greatly depends on the global impedance between power and ground nodes, often simplified as a decoupling capacitance. Unfortunately for HF purposes the stand-alone capacitance is not sufficient enough to reproduce all impedance effects. Therefore some AC simulations using standard spice simulator such as ELDO must be performed in order to extract the power/ground equivalent impedance of the simulated block, as shown in the next figure.
ELDO
VDD Port
Inputs
chip GND
Outputs
AC simulation
Z(f)
Figure 3: equivalent impedance extracting using S-parameters simulation
This equivalent impedance is stored in a file and is re-used in the last simulation.
3.c Global noise simulation After retrieving the waveform current and the equivalent power/ground impedance of the block, additional noise parameters can be added in last-stage simulation, leading to realistic supply bounces and current consumption of the block inside the package. Package parasitics
Current modeling Waveform current
Additional noise parameters
Impedance modeling S parameters extraction
Global noise simulation
Figure 4: Global noise simulation flow
This simulation technique offers several important advantages: ·
· ·
The modularity allows changing one of the simulation parameter without having to re-perform all the steps. For example the decoupling capacitance value can be changed within the impedance-modeling step only, or the power supply voltage can be changed within the current modeling step. The global noise simulation step is really fast, as it only includes waveform currents, S-parameters black boxes and package parasitics. Simulation time can therefore be optimized. Current modeling and impedance modeling steps can be calculated even in sub-blocks and implemented in the last global noise simulation step.
To illustrate this technique, next example deals with a real testchip.
4. Testchip example To study the problem of power and ground bounce, a testchip has been designed using core buffer chains and inputs/outputs buffers, in order to have a synchronous switching noise. Next figure contains a floorplan view of the cells and the block modeling synoptic used in the modular simulation flow.
IO Ring (Input, outputs and probe measurements
Assembled in a TQFP80 package
Oscillator cells (not used)
Buffers chains (most of noise)
External VDD Package parasitics on supply
Waveform current from serial buffers
Z model of oscillator
Z model of serial buffers
IOs ring netlist
Z model of routing
Z model other noise parameters
Package parasitics on ground
External GND Figure 5: Testchip description and modeling
This simulation flows contains: · ·
The package parasitics in RLC model or S-parameter black-box The equivalent power/ground impedance of the oscillator block and the serial buffers. Although the oscillator block is not active, the impedance modeling is mandatory in order to introduce its decoupling effect
· · ·
Additional equivalent power/ground impedance coming from routing extraction or substrate connections, etc… The waveform current generator extracted from previous HSIM pattern simulation, modelizing the transient current consumption of the serial buffers The IO ring, simulated in the last step, either in spice netlist or in IBIS format.
In our testcase, the 120k-transistor testchip has been simulated in less than two hours, including RC network extraction of the routing. On the opposite, the same testchip has been simulated in a classical spice simulation without RC network during two days. And the RC network extraction has been impossible due to hardware limitations. Next figure shows the efficiency of the method compared to the standard spice simulation. For better comparison, the RC network extraction has been removed.
Orange : VDD modelling Yellow : VDD spice simulation
Green : GND modelling Blue : GND spice simulation
Figure 6: Power and ground bounce on internal supplies during gate switching
5. Conclusion Giving good noise results according to spice reference, the new simulation method becomes an efficient tool to predict power and ground bounce and emission at chip level. The speed of this flow leads to consider noise effects at chip level, including most of the noise parameters such as routing RC effect, package parasitics, decoupling effect or substrate coupling. As this method is validated on dedicated testchip, latest works focus now on automatization and improved noise accuracy compared to conducted noise measurements.
