Evaluating Pathways for Optimised Subthreshold ...

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Journal of Computational and Theoretical Nanoscience Vol. 9, 1–8, 2012

Evaluating Pathways for Optimised Subthreshold Design: Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region Subhra Dhar1 ∗ , Manisha Pattanaik1 , and P. Rajaram2 1

Department of Information Technology, VLSI Group, ABV-Indian Institute of Information Technology and Management Gwalior, Gwalior-474010, M.P., India 2 Department of Physics, Jiwaji University, Gwalior-474009, M.P., India

For low power electronics, power dissipation is the primary concern. As operation in sub threshold region is synonymous to minimum energy operation, this endeavor revisits the scaling strategies to achieve improvement in energy and delay by using bulk nMOSFET devices in deep and ultradeep submicron region with optimized channel lengths, dopings, gate oxide thicknesses and temperatures. The authors attempt to present a novel design methodology for low and ultra low power design in bulk nMOSFETs using leakage minimizing techniques for device subthreshold operation. This paper studies the power delay product as part of sensitivity analysis of devices explored in the deep and ultra deep submicron region. The suggested optimized sub threshold design at the deep and ultra deep submicron region are encouraging enough and the application roadmap provided thus can be functional to device engineers.

Keywords: MOSFET, Scaling, Leakage, Low Power, Deep Submicron, Reduction Techniques,

1. INTRODUCTION CMOS technology evolution in the past thirty years has followed the path of device scaling for achieving density, speed and power improvements. Scaling down MOSFETs has a multitude of benefits. The principle of constant field scaling suggested scaling the device voltages and the device dimensions by the same factor so that the electric field remains unchanged. Once the device dimensions and the power supply voltages are scaled down, the circuit speeds up by the same factor. The power dissipation per circuit is reduced and the power delay product of the scaled CMOS circuit shows dramatic improvement due to constant field scaling. Even though this type of scaling provides a basic guideline to the design of scaled MOSFETs, the requirement of reducing the voltage by the same factor as the device physical dimension is too restrictive. For device design purposes, it is necessary to develop a more general set of guidelines that allows the electric field to increase. In generalized scaling, it is desired that both the lateral and vertical electric fields change by the same multiplication factor so that the shape of the electric field pattern is ∗

Author to whom correspondence should be addressed.

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preserved. Due to generalized scaling, the circuit delay scales down depending upon the degree of velocity saturation. This kind of scaling increases the power density very much and thus puts a great burden on VLSI packaging technology.1 Constant voltage scaling helps to preserve the shape of the field pattern, since the electric field scales up by the scaling factor k.2 Both the power supply voltage and the threshold voltage remain unchanged. Although constant voltage scaling leaves the solution of Poisson’s equation for the electrostatic potential unchanged, voltage scaling is also limited on several fronts. The built in junction voltages are set by the 1.1 eV band gap of Si which does not scale. Consequently as the applied voltages are scaled towards 1 V, the internal fields do not automatically scale as desired.3 A similar difficulty occurs in trying to scale the threshold voltage Vt , which is tied to the nonscaling behavior of the subthreshold slope and its influence on the OFF current. These and other issues associated with scaling motivated the authors to revisit the scaling rules to be applied on bulk nMOSFET and seek possibly better design profiles in the deep submicron and ultra deep submicron region for ultra low power applications. The need for alternative scaling trends for subthreshold design is emphasized in Ref. [4]. The scaling of transistors dimensions and

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doi:10.1166/jctn.2012.2038

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Power, Delay, Channel Length, Fixed Oxide Charge, Subthreshold, Simulation.

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Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region

electrical characteristics represent both an opportunity and a threat for subthreshold circuits. Exponential dependence of drain current on Vgs and Vth makes subthreshold circuit design quite different from the conventional superthreshold design. Scaled subthreshold circuits have the following advantages for conventional planar MOSFETs: smaller devices have lower capacitance and thus lower switching power, gate oxide thickness is smaller which increases the gate control. The short channel effects for subthreshold operation are lower because of smaller Vdd and hence the degradation in the ratio of ON current to OFF current due to channel length scaling becomes less significant. The advantage of using scaled devices for subthreshold operation is very well brought out in Ref. [5]. Among the different leakage currents in the deep submicron and ultra deep sub micron region, the subthreshold and gate leakage are the most dominant. Reduction of leakage currents involves application of different device and circuit level techniques. At the device level, it involves controlling the doping profiles and physical dimensions of transistors, while at the circuit level it involves the manipulation of Vth and source biasing of the transistor.6 The gate leakage and the sub threshold leakage are strongly correlated through the oxide thickness. The individual leakage component and the total leakage component depends strongly on the temperature.7 It has been shown that the halo and retrograde doping are not essential for subthreshold device design as the process technology becomes simplified in terms of steps and cost, and the junction capacitance will also be reduced.4 OFF state leakage reduction techniques include cooling solutions, as the subthreshold current is mainly because of diffusion, lower temperature reduces the rate of diffusion. The dependence of various leakage components on temperature is reported in Ref. [8]. This work excludes the cooling options and tries to focus on other methods of leakage reduction, reduced Vth -roll off and reduced DIBL in the investigated region. In this paper, scaled bulk nMOSFETs of 90 nm, 65 nm, 45 nm and 32 nm gate lengths are explored for enhanced subthreshold design. With the scaling strategy proposed for subthreshold circuits, this paper brings out the improvement achieved in power and delay by using devices with optimized channel length and gate oxide thickness and doping. This paper is divided into six sections. Section 2 discusses the device structure and the simulation tool used to obtain the results. The scaled device parameters employed for the standard device design are presented in the form of a table. Section 3 suggests techniques which are applied to enhance the subthreshold characteristics of this region and analyses the graphical results thus obtained. Low power consumption being the major concern, Section 4 brings out the power delay product and the total leakage power analysis of the regions investigated. Section 5 attempts to provide the application wise optimized design for the explored regions. Section 6 brings out the achievements of the paper and thus concludes the paper. 2

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Fig. 1.

2. DEVICE STRUCTURE AND SIMULATION This paper investigates uniformly doped nMOS devices of gate lengths 90 nm and 65 nm in the deep submicron region and 45 nm and 32 nm in the ultra deep submicron region. SILVACO ATLAS is used for all simulation purpose. ATLAS is designed to be used with VWF interactive tools. The VWF interactive tools are DECKBUILD, TONYPLOT and DEVEDIT. The important device parameters namely the gate length (Lg , gate oxide thickness (Tox ), junction depth (Xj , silicon substrate doping concentration (Na ), and polysilicon gate with arsenic doping concentration (Nd ) and the supply voltage Vdd are scaled according to constant field scaling as well as constant voltage scaling rules. DECKBUILD is the interface between DEVEDIT and the device simulator ATLAS. In this environ, the nMOS structure is called through the command which is made at DEVEDIT environment, and the ATLAS device simulator simulates it. In all simulated devices, the fixed interface oxide charge is 3e10 cm−2 . For all simulation purpose, operating temperature of 300 K is used. In our simulation, the LOMBARDI CVT mobility model is used as it is a complete model including N , T , E parallel and E Perpendicular effects. Newton-Gummel method is adopted to solve the equations in this model. The schematic of a MOSFET shown in Figure 1. The device design parameters used in this manuscript for the 65 nm and 45 nm nMOSFETs are as shown in Table I.

3. TECHNIQUES TO ENHANCE SUBTHRESHOLD CHARACTERISTICS IN DEEP AND ULTRA DEEP SUBMICRON REGION With the continuous scaling of CMOS devices, leakage current is becoming a major contributor to the total power consumption. In current deep sub micrometer devices with Table I.

Lg 65 45

Standard device parameters according to scaling rules. Tox , Xj (nm), Na , Nd (cm−3 , Vdd (V) constant voltage scaling

Tox , Xj (nm), Na , Nd (cm−3 , Vdd (V) constant field scaling

2.17, 43.47, 1.9e17, 1.9e20, 1.2 1.59, 31.5, 3.61e17, 3.61e20, 1.2

2.17, 43.47, 1.38e17, 1.38e20, 0.86 1.59, 31.5, 2.62e17, 2.62e20, 0.62

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low threshold voltages, subthreshold and gate leakage have been dominant sources of leakage and are expected to increase with the technology scaling. Exponential dependence of drain current on Vgs and Vth makes subthreshold circuit design quite different from the conventional super threshold design. Device level techniques to reduce leakage currents are made by either modifying the standard bulk CMOS process technology or by introducing new process technologies. Existing methods like halo doping and retrograde doping, minimizing oxide thickness and reducing operating temperature have been extensively advocated by various researchers over the past decade to reduce leakage current and thus contain dissipated power. In this work, the authors have assessed supplementary techniques to enhance the subthreshold operation which can be applied to devices below 90 nm region. The standard bulk nMOS process technology can be adjusted to meet low leakage currents requirements by various techniques identified as follows: increasing channel length, varying Tox , low doping in substrate, reducing fixed oxide charge and increasing Vth close to Vdd . The impact of these techniques on the scaled standard devices is discussed below and a possible pathway to an optimized subthreshold design is shaped up in the next section.

3.1. Increase in Channel Length To reduce subthreshold leakage, channel length can be slightly increased.9 There is a penalty in performance when channel length is increased but can still be applied to non-critical paths. The ratio Leff /Tox reduces with each technology generation due to the slow scaling of Tox and worsens the Vth roll off problem. This suggests that longer channel lengths should be used to accommodate the gate oxide. MOSFETS with longer channel lengths will result in lower power or better performance because of improved subthreshold swing. An increase in channel length causes considerable changes in the leakage current as shown in this table, but the subthreshold slope shows less improvement as this work concludes. J. Comput. Theor. Nanosci. 9, 1–8, 2012

Table II. Effect of increasing channel length on deep and ultra deep submicron devices. Scaled standard device at 300 K Lg (nm) 90 65 45

Increase in channel length at 300 K

CVS/CFS

CVS/CFS

CVS/CFS

CVS/CFS

S

Ioff

S

Ioff

70.7/69.4 6.94e−7/2.34e − 6 85.6/73.2 2.40e − 8/1.91e − 7 99.5/69.2 5.32e − 9/4.63e − 7 98.9/73.3 5.29e − 9/8.39e − 8 135.7/78.1 2.34e − 11/1.94e − 12 190.0/94.1 3.52e − 13/1.52e − 13

As the technology move to ultra deep submicron region, not much improvement could be possible in S due to the close proximity of source and drain as is seen in the Table II. 32 nm data is excluded. 3.2. Varying Tox Scaling MOSFETS for higher and higher performance has been associated with higher and higher leakage. Traditionally MOSFETS have been associated with subthreshold leakage, though aggressive scaling beyond 100 nm has resulted in dominant gate and junction BTBT leakages as well. The oxide thickness has been scaled to gain better gate control but the gate leakage increases exponentially due to the exponential increase in the tunneling probability of the electrons. In energy constrained design, the primary objective of the subthreshold operation is to optimize Tox to minimize parasitic capacitances. Change in Tox affects both effective capacitance and the subthreshold swing. Minimizing oxide thickness to improve subthreshold slope does not necessarily provide minimum energy consumption in digital subthreshold operation. Oxide thickness should be optimized considering the changes in both transistor effective capacitance and the subthreshold slope to achieve minimum power consumption.4 Variations in Tox impact the oxide capacitance Cox . Earlier work suggests thinner oxide requirement to overcome Vth roll off as Tox reduction increases gate leakage current exponentially. Thus careful engineering of the Tox dimension is crucial to meet the constraints. Generally Tox is required to minimize, but this study considers varying Tox above and below the scaled values of the investigated devices and study their effect on S and Ioff . Simulation results in this work suggest that if scaling rules are not followed, keeping the value of Tox at 2 nm thickness from 90 nm − 45 nm device gives good results. Figures 2–5 are the subthreshold results obtained due to variation of Tox in these regions. 3.3. Reducing Fixed Oxide Charge It is often said that the real magic in silicon technology lies not in the silicon material but in silicon dioxide. Silicon dioxide forms critical components of silicon devices, serves as insulation and passivation layers and it 3

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Standard devices investigated in this paper: (I) Parameters obtained due to constant voltage scaling at 300 K. 90 nm [Vt : 0.491, S: 70.7, Ioff : 6.94e − 7] 65 nm [Vt : 0.477, S: 99.5, Ioff : 5.32e − 9] 45 nm [Vt : 0.419, S: 135.7, Ioff : 2.34e − 11] 32 nm [Vt : 0.415, S = 1159, Ioff : 9.44e − 14] (II) Parameters obtained due to constant field scaling at 300 K. 90 nm [Vt : 0.463, S: 69.4, Ioff : 2.34e − 6] 65 nm [Vt : 0.477, S: 69.2, Ioff : 4.63e − 7] 45 nm [Vt : 0.40, S: 78.1, Ioff : 1.94e − 12] 32 nm [Vt : 0.32, S = 1099, Ioff : 1.204e − 10] Ion is the drain current at Vgs = Vds = Vdd , AC frequency = 1 MHz.

Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region

Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region

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Fig. 4. Ioff versus Lg due to const, voltage scaling.

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Fig. 2.

Subthreshold slope versus Lg due to const voltage scaling.

is often used as an effective masking/diffusion barrier layer in device fabrication. Since every device has some regions that are covered by silicon dioxide, the electrical characteristics of a device are very sensitive to the density and properties of the charges inside its oxide regions and at its silicon-oxide interface. Fixed oxide charges are positive charges located in the oxide layer very close to the Si– SiO2 interface. The presence of oxide charges and interface

Fig. 3.

4

Subthreshold slope versus Lg due to const field scaling.

traps has major effects on the characteristics of devices.1 The interface traps act as generation-recombination centers and assist in the band to band tunneling process thus contributing to the leakage current. Also the leakage current increases when the gate voltage begins to cause field crowding in and around the junction region leading to gate induced leakage current. This work considered reducing the fixed oxide charge from 3e10 to 1e10 and study the subthreshold characteristics obtained in the deep and ultra deep submicron nMOSFET devices. The impact of reducing the oxide charge on 90–65–45 is as shown in Table III. This may be a possible technique to reduce leakage currents in the investigated regions.

Fig. 5. Ioff versus Lg due to const field scaling.

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Table III. The impact of reducing the oxide charge on deep and ultra deep submicron devices. Scaled standard device

Impact of reducing FOC

(FOC = 3e10) Lg (nm) 90 65 45

Fig. 6.

FOC = 1e10

CVS/CFS

CVS/CFS

CVS/CFS

S

Ioff

S

Ioff

S

Ioff

70.7/69.4 99.5/69.2 135.7/78.1

6.94e − 7/2.34e − 6 5.32e − 9/4.63e − 7 2.34e − 11/1.94e − 12

70.9/68.1 98.1/69.2 144.0/78.9

7.04e − 7/6.35e − 6 1.42e − 8/4.27e − 7 9.12e − 12/1.62e − 12

71.0/69.4 97.1/69.3 145/79.4

6.30e − 7/2.04e − 6 4.27e − 7 /3.93e − 7 7.86e − 12/1.36e − 12

S versus Lg (CFS).

3.4. Lower Doping Concentration of Substrate (Extended to 32 nm)

S versus Lg (CVS).

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Fig. 8. Ioff versus Lg (CFS).

3.5. Effect of Increasing Vth ∼Vdd Circuits operating in the subthreshold region suffer from slow speed, but systems whose primary requirement is ultralow power and not high performance maybe the target of this technique. The major requirement upon Vt is

Fig. 9. Ioff versus Lg (CVS).

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Low doping level in bulk of the device is required to reduce the capacitance of the bottom junction and reduce substrate noise effects and parasitic latch up problems.4 This work considers this technique as a potential method to reduce leakage current and improve S. The doping 1 and doping 2 are below the scaled values of Na . Figures 5–8 present the subthreshold result details due to the scaling rules. Lower concentration of bulk doping impacts the off current status of 65 nm, 45 nm and the 32 nm devices the most, whereas for the 90 nm its influence is not appreciable.

Fig. 7.

FOC = 2e10

CVS/CFS

Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region

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Table IV. Effect of increasing Vth ∼Vdd on deep and ultradeep submicron devices. 90 [CVS] 65 [CVS] 45 [CVS] 32 [CVS]

S = 482 Ioff = 127e–7 S = 480 Ioff = 291e–8 S = 727 Ioff = 494e–9 S = 2430 Ioff = 169e–14

90 [CFS] 65 [CFS] 45 [CFS] 32 [CFS]

S = 490 Ioff = 144e–5 S = 724 Ioff = 191e–7 S = 412 Ioff = 248e–10 S = 1112 Ioff = 221e–11

taken to be the drive limitation upon the closeness of Vt to Vdd .10 To reduce leakage, noise and power dissipation as much as possible, Vt is set as near to Vdd as the drive requirement allows. The condition Vdd ∼ 4Vt is adopted for this purpose thereby coupling the maximum doping to the applied voltage, to make a device small by decrease of the depletion layer widths the dopings must increase in turn making Vt higher. The 90–65–45 nm devices improve their subthreshold behavior on application of this technique as shown below in Table IV except the 32 nm node.

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4. POWER DELAY PRODUCT AND THE TOTAL LEAKAGE POWER ANALYSIS OF THE REGIONS INVESTIGATED For low power electronics, power dissipation being the primary concern, the most effective way of reducing active power at the device level is to lower the supply voltage. Lower threshold voltages leads to exponentially increasing standby power dissipation. Low power CMOS operates at lower supply voltages and possibly at a higher threshold voltage if the standby power is of primary concern. Depending on specific requirements of the application, CMOS technologies can be tailored by choosing an appropriate set of power supply and threshold voltages. A practical limit for the nominal threshold voltage for room temperature CMOS is about 0.3 V, below which the chip standby power becomes unmanageable. For high performance logic chips threshold voltage needs to be reduced as the delay rises sharply.1 Since the frequency targets for ultralow power systems allow the use of slow devices, speed can be traded off for power by scaling the supply voltage beyond the threshold voltage and using the subthreshold voltage for computation.5 Optimization techniques specifically suited for subthreshold operation need to be applied to achieve improvement in power consumption. Device optimization for the subthreshold operation can improve the power delay product. A device should be specifically optimized for subthreshold operation to improve the device’s power delay product. In this part of the work, nMOSFET devices of gate lengths of 90, 65, 45 and 32 nm which were simulated to obtain optimized designs with better subthreshold slope, and maximum possible reduced leakage current (Section 3) then explored for 6

Fig. 10. Total power due to scaling rules versus gate lengths.

the total power and power delay product analysis. To calculate the delay of the devices, frequency of operation is kept at 1 MHz. The threshold voltages of the devices are as shown in Section 3. The Vth values being above 0.3 V are responsible for the enhanced performance of the devices explored. Benefits of technology scaling can be seen the most in the 45 nm region, with field scaling giving the most improved result. The total power Ptot at 65 nm due to const. voltage and const. field scaling remains quite close to each other. Significant improvement in the PDP is observed in the Figure 11 built with the optimized devices at room temperature. The authors have also calculated the PDP at the optimized temperature for variability reasons.

Fig. 11. Power delay product of the devices at the optimized temperature and room temperature due to scaling rules.

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Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region

5. PERFORMANCE OF OPTIMIZED DEVICES AS COMPARED TO STANDARD DEVICES To optimize the sub threshold design of investigates devices, this work considered all the leakage techniques applied in Section 3. To fully optimize S with device scaling it is not sufficient to simply lengthen L without considering the doping. Thus L and doping must be optimized simultaneously. Increasing L and reducing doping improves S at the cost of increased gate capacitance. The cost of this optimization can be quantified in terms of energy and delay. In subthreshold operation, if constant Table V. Proposed optimized design for subthreshold operation.

Lg (nm) 90

65

32

Constant field scaling

At 135 K, Tox = 2 nm, FOC = 1e10, and an increase in length, S = 562, Ioff = 6.14e − 11, may be applicable in LOP with delay = 7.89 ps At 300 K, delay = 3.65 ps At 260 K, Tox = 2 nm, FOC = 2e10 and a moderate increase in bulk doping compared to the scaled value, S = 509, Ioff = 1.44e − 10, may be applicable to HP devices with delay = 1.454e − 10 At 300 K, delay = 0.442e − 10 At 255 K, with the above specifications, S = 549, Ioff = 1.03e − 10 may be applicable to LOP, LSTP devices At 200 K, Tox = 2 nm, FOC = 2e10, with a moderate increase in bulk doping, S = 671 Ioff = 3.51e − 18, maybe applicable to LOP devices with delay = 3.98 s. Delay at 300 K = 0.394e − 4 s

At 280 K, with Tox = 3 nm S = 645, Ioff = 1.93e − 6, may be applicable to HP devices with delay = 1.01e − 11

At 180 K, Tox = 2 nm, FOC = 1e10, with an increased bulk doping, S = 640, Ioff = 5.27e − 18, may be applicable to LOP devices with delay = 0.13 s At 300 K, delay = 1.04e − 6

At 300 K, 0.538e − 12 s At 280 K, Tox = 2 nm with a moderate increase in bulk doping, S = 629, Ioff = 4.9e − 8 may be applicable to HP devices with delay = 1.47e − 10

At 300 K, delay = 0.89e − 10

At 200 K, Tox = 2 nm, S = 575, Ioff = 6.21e − 18, may be applicable to LOP, HP devices with delay = 13.97 s

At 300 K, delay = 0.495e − 4 At T = 200 K, Tox = 2 nm with increased bulk doping, S = 556, Ioff = 3.31e − 16 may be applicable to LOP, HP devices with delay = 81.08 s At 300 K, delay = 0.255e − 4

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6. CONCLUSION While significant transistor challenges like short channel effects, capacitance, and mobility exist for deep submicron devices, numerous solutions towards low and ultralow power are explored in this paper. This work reconsiders the scaling strategies to achieve improvement in energy and delay by using scaled bulk nMOSFET devices in deep and ultradeep submicron region with optimized channel lengths, dopings, gate oxide thicknesses and temperatures. Scaling rules are revisited and voltage scaling assumes significance for highly scaled devices in order to keep the electric field well below its critical value. The authors attempt to present a novel design methodology for low and ultra low power design in bulk nMOSFETs using leakage minimizing techniques for device subthreshold operation. Ultra low power dissipation can be achieved with scaled devices albeit with degradation in speed and increased susceptibility to parameter variations. This paper studies the power delay product as part of sensitivity analysis of devices explored in the deep and ultra deep submicron region. The suggested optimized sub threshold design at the deep and ultra deep submicron region are encouraging enough and the application roadmap provided thus may be useful to device engineers.

References 1. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, South Asian Edition, Cambridge University Press, Cambridge, UK (2003). 2. B. G. Streetman and S. Banerjee, Solid State Electronic Devices, Prentice-Hall, New Delhi, India (2002). 3. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Taur, Proc. IEEE 89, 273 (2001). 4. R. Vaddi, S. Dasgupta, and R. P. Agarwal, J. VLSI Design 2009 (2009).

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Constant voltage scaling

voltage scaling is considered since the overall supply bias is small the effects of DIBL and body punchthrough are extremely low. Ideally DIBL doesn’t change the S, but lowers the Vth . Higher surface and channel doping and shallow S/D junction depths reduce the DIBL effect on the subthreshold leakage current. As reducing temperature is a successful method of leakage reduction, this work considers the cooling options too for the optimized design. This work finds out that all the devices from 90 nm to 65 nm and 45 nm respond positively to most of the techniques applied. The 32 nm device doesn’t show much improvement in its subthreshold characteristics, though the reduction in leakage current is appreciable. At 32 nm, Vt is low and limitations come from high subthreshold swing, DIBL and variability. So field scaling is a better option instead of voltage scaling. The optimized design for the devices based on the scaling strategy followed throughout this paper is presented below in Table V along with the possible area of application.

Scaled Bulk nMOSFETs in Deep and Ultradeep Submicron Region 5. S. K. Gupta, A. Raychowdhury, and K. Roy, Proc. IEEE 98, 160 (2010). 6. N. Ekekwe and R. E. Cummings, Microelectronics Journal 37, 851 (2006). 7. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, IEEE Trans. Computer Aided Design of Integrated Circuits and Systems 24, 363 (2005).

Dhar et al. 8. O. Semenov, A. Vassighi, and Manoj Sachdev, Microelectronics Journal 33, 985 (2002). 9. M. Anis and M. H. Aburahma, Proc. 9th Inter. Database Engg. Application Symposium (IDEAS’05), IEEE Computer Society (2005). 10. S. M. Sze, High Speed Semiconductor Devices, John Wiley & Sons, Inc. (1990).

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Received: 21 March 2011. Accepted: 5 May 2011.

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