International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016), pp. 81-92 http://dx.doi.org/10.14257/ijseia.2016.10.6.07
FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology Vandana Thind1, Bishwajeet Pandey2, Kartik Kalia3, D M Akbar Hussain4, Teerath Das5 and Tanesh Kumar6 1-3
Gyancity Research Lab, Gurgaon, India Aalborg University, Esbjerg, Denmark 5 Gran Sasso Science Institute, L’Aquila, Italy 6 Center for Internet Excellence, University of Oulu, Finland
[email protected],
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Abstract In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V. Keywords: DES Algorithm, IO standards, MOBILE_DDR, HSUL_12, LVTTL, LVCMOS, power dissipation
1. Introduction When designs are implemented on the hardware, designer‟s main focus is on correct placement and routing of components on chip. After this power consumption is the main concern. In this particular work, we have done the power analysis of DES security encryption algorithm. Whole analysis is done using software development kit Xilinx ISE. DES is symmetric key algorithm for encryption of electronic data. It is designed for the data of size 56-bits.The plain-text is provided to input, then it is encrypted by DES algorithm [8, 10] and we get cipher-text as an output. This algorithm is implemented on Artix-7 FPGA. We have done the analysis on power dissipation of DES algorithm, with constant frequency of 2.4GHz. As IO standard is main area of concern, we have done analysis using 4 different IO standards like MOBILE_DDR [1], HSUL_12, LVTTL and LVCMOS as shown in Figure 1.
ISSN: 1738-9984 IJSEIA Copyright ⓒ 2016 SERSC
International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
MOBIL E_DDR
IO STANDA RDS
HSUL_ 12
LVTTL
LVCMOS
Figure 1. Types of IO Standard used for Power Analysis MOBILE_DDR is Mobile Double Data Rate (DDR) SDRAM. It is designed for full programmability, high clock rates and high memory throughputs. It eliminates the need for Vref and Vtt voltage supplies. LVTTL (Low Voltage TTL) is a general-purpose EIA/JESD standard for 3.3V applications that use single-ended CMOS input buffer and a push-pull output buffer. This standard requires output source voltage (VCCO) of 3.3V and doesn‟t require reference voltage. LVCMOS (Low Voltage CMOS) is widely used switching standard implemented in CMOS transistors. The LVCMOS standards supported in 7 series FPGAs are: LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33.
LVCMOS_18
LVCMOS_25
LVCMOS_15
LVCMOS_33
LVCMOS
Figure 2. Type of LVCMOS IO Standards Xilinx XPower analyzer help us to perform power estimation and analysis for the design. Total power in an FPGA is the sum of two components: static power and dynamic power. Static power results from the transistor leakage current in the device. Dynamic power is associated with the switching event and design activity which include clock, signal, logic and IO of the device as shown in Figure 3.
STATIC
TOTAL POWER DYNAMIC
Figure 3. Total power
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Copyright ⓒ 2016 SERSC
International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
For each IO standard, we notified the power dissipation of clock power, signal power, logic power, IO power, leakage power and supply power by varying voltages as shown in Figure 2. We considered five different voltages 0.2V, 0.5V, 1.0V, 1.2V and 1.5V.
CLOCK
SIGNAL
LOGIC
IO
LEAKAGE
Figure 4: On-Chip Power Analysis done on these Power Elements We have calculated the percentage change in power from minimum voltage i.e., 0.5V to maximum voltage i.e., 1.5V.
2. Related Work In the related research work, we have notified that one of the researcher have done study about MOBILE_DDR I/O standard for designing ALU [1], where we are using different I/O standard in order to search the most efficient I/O standard among them, for implementation of DES algorithm on 28nm FPGA. Other researcher has researched about the power consumption of hardware implementation of security system, mainly focusing on the power consumed by microchips [2]. We have done the analysis of power dissipation of clock power, signal power, leakage power, IO power and supply power. Another researcher has done the analysis on process of enciphering and deciphering of words having word width 64bits [3]. Our main focus area is power dissipation at constant frequency i.e., 2.4GHz. One scientist has described a single-chip implementation of the data encryption standard using XC4000 FPGA [4]. Whereas, we are using Artix-7 FPGA for power dissipation analysis. Other researchers researched on the hardware implementation of DES algorithm on the parallel architecture for secure encryption and they have also worked on the reusability of hardware functions [5]. In context to this we have used the DES Architecture for power analysis so that we can design more efficient and improved design of DES algorithm on hardware for strong security purposes. One scholar has done research on the configuration of parts of bit-stream [6]. Another researcher‟s work shows that there are extreme regular properties might point to weakness of the cipher [7]. Here, we have done the analysis of power dissipation, using four different IO standards at five different voltages, provided to the FPGA. We have done analysis by keeping constant frequency i.e., 2.4 GHz. SSTL is also best IO standard for implementation of security algorithm on FPGA [8].
3. Power Analysis Power is dependent on the design and is affected by output loading, system performance (switching frequency), logic block and interconnect structure, percent of interconnect switching and supply power [11-14]. Accurate power calculation at the early stage in the design cycle will result in fewer problems later. The power dissipation is very significant aspect of any design implementation. It is a measure of the rate at which energy is lost, from an electrical system. We have done analysis on power dissipation by various on-chip components, to design more efficient DES algorithm for implementation on 28nm FPGA. IO Standards are the resources that describe the electrical behavior of the input drivers and output receivers. Devices like FPGA offer both high-performance (HP) and high-range (HR) I/O banks, accordingly I/O Standards are divided. There are many kind of I/O Standard at different voltages. We have considered four IO standards (i.e., MOBILE_DDR, HSUL_12, LVTTL and LVCMOS) for which power analysis of clock power, logic power, signals power, IO power and leakage power is contrasted at five different voltage levels.
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International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
Voltages On-chip power elements IO Standards Figure 5. Process of Power Analysis We have notified the reading of power dissipation of on-chip components using Xilinx ISE software. Figure 4 shows the process of our analysis. We calculated percentage change in power dissipations between 0.5V and 1.5V. We also analyzed the effect of voltages on the supply power and total power dissipated.
4. Power analysis using MOBILE_DDR as IO standard MOBILE_DDR is a 1.8V single-ended I/O standard that eliminates the need for reference voltages supplies. 28nm FPGAs support this standard for single-ended signaling and differential outputs. It is available for high-range I/O Banks. It is bidirectional standard and provide both fast and slow slew rate. Table 1, shows the power dissipation of clock power, logic power, signal power, IO power, and leakage power, when MOBIL_DDR is I/O standard. This table also shows the supply power of the DES algorithm. Table 1. Power Dissipations at Five Different Voltages using MOBILE_DDR Voltag e
Clock
Logic
Signal
IO
Leaka ge
Total
supply power
0.5 0.8 1.0 1.2 1.5
0.082 0.163 0.230 0.308 0.445
0.063 0.161 0.251 0.362 0.565
0.140 0.358 0.559 0.806 1.259
2.052 2.066 2.076 2.086 2.100
0.030 0.038 0.052 0.079 0.177
2.366 2.786 3.169 3.640 4.546
2.678 2.969 3.169 3.376 3.716
Figure 5 is the graphical representation of above data. It clearly shows variation in power dissipation of different on-chip components power. Especially for IO power and leakage power, there is 2.28% and 83.1% change in power, when voltage is increased from 0.5V to 1.5V.
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International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
Figure 6. Graphical Representation of Power Dissipation using MOBILE_DDR
5. Power Analysis using HSUL_12 as IO Standard HSUL_12 is high speed unterminated logic for single-ended signaling and differential signaling. HSUL_12 is available for both HR and HP I/O bank type. Its output operating voltage is 1.8V but input operating voltage can be any. This I/O standard considers reference voltage of 0.6V. It specifies the slew rate strength of the output buffer. In Table 2, analysis of power dissipation at five different voltages is shown. Table 2. Power Dissipations at Five Different Voltages using HSUL_12 Voltage
Clock
Logic
Signal
IO
Leakage
Total
supply power
0.5 0.8 1.0 1.2 1.5
0.076 0.153 0.218 0.294 0.428
0.063 0.161 0.251 0.361 0.565
0.140 0.359 0.561 0.808 1.263
1.307 1.333 1.351 1.368 1.394
0.029 0.036 0.049 0.073 0.162
1.614 2.043 2.430 2.905 3.812
1.940 2.231 2.430 2.636 2.971
Table 2 & Figure 6 graphically display power dissipation of DES. We have notified that when voltage increases from 0.5V to 1.5V, percentage change in power dissipation of IO is 6.28% and for leakage power is 82.1%.
Figure 7. Graphical Representation of Power dissipation using HSUL_12
6. Power Analysis using LVTTL as IO Standard LVTTL is low voltage TTL. This standard requires 3.3V output source voltages but does not require reference voltages. It is both bidirectional and unidirectional standard. LVTTL is applicable for only HR bank and the value for current drive strength is 4mA, 8mA, 12mA, 16mA and 24mA.It is single-ended I/O Standard. LVTTL is IO Standard which supports the SLEW attribute that can be selected between both FAST and SLOW edge rates. In Table 3, comparison of power dissipation can be done, for different voltage levels.
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International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
Table 3. Power Dissipations at Five Different Voltages using LVTTL Voltage
Clock
Logic
Signal
IO
Leakage
Total
supply power
0.5 0.8 1.0 1.2 1.5
0.094 0.184 0.258 0.342 0.490
0.063 0.161 0.251 0.362 0.565
0.147 0.375 0.587 0.845 1.320
6.543 6.557 6.567 6.576 6.591
0.037 0.053 0.077 0.127 0.311
6.883 7.330 7.739 8.252 9.276
7.217 7.525 7.739 7.968 8.368
From Figure 7, which is graphical representation of Table 3, we inferred that percentage change in IO power and leakage power is 0.73% and 88.1% respectively, when voltage changes from 0.5V to 1.5 V.
Figure 8. Graphical Representation of Power Dissipation using LVTTL
7. Power Analysis using LVCMOS as IO Standard LVCMOS (Low-Voltage CMOS) is widely used switching standard implemented in CMOS transistors. There are five types of LVCMOS IO Standards like LVCMOS_12, LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33. We have done analysis on four I/O Standard as shown below. a) LVCMOS_15 LVCMOS_15 is I/O Standard which is available in both the HR and HP I/O banks. it support drive current strength of 2mV, 4mV, 6mV, 8mV, 12mV and 16 mV for HP I/O Banks, on the other hand for HR I/O Bank drive current strength applicable is 4mV, 8mV, 12mV and 16mV. It allows both fast and slow edge slew rate for both HP and HR I/O Banks. We have done the analysis of power dissipation of the IO power and leakage power, during implementation of DES algorithm on 28nm FPGA. In Table 4, we noticed that when voltage is raised from 0.5V to 1.5V, percentage change in IO power is 3.05% and leakage power is 82.7%. Table 4. Power Dissipations at Five Different Voltages using LVCMOS_15 Voltage
Clock
Logic
Signal
IO
Leakage
Total
supply power
0.5 0.8 1.0 1.2 1.5
0.094 0.184 0.258 0.342 0.490
0.063 0.161 0.251 0.362 0.565
0.147 0.375 0.587 0.845 1.320
1.524 1.538 1.548 1.557 1.572
0.029 0.037 0.050 0.075 0.168
1.857 2.295 2.693 3.181 4.115
2.187 2.488 2.693 2.905 3.252
Figure 8, presents the graphical representation of power dissipation of table 4. We analyzed from this graph that total power dissipation at 1.5V increases as compared to the supply power.
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International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
Figure 9. Graphical Representation of Power Dissipation using LVCMOS_15. b) LVCMOS_18 LVCMOS_18 have operating voltage of 1.8V. It is available for both the HR and HP I/O banks. It is bidirectional buffer. It allows both slow and fast edge slew rate. The drive current strength availability for both HP and HR Bank is same as in LVCMOS_15 but additional 24mA of current is available in HR, which is not present in LVCMOS_15. Power dissipation is part of our research so, in Table 5, the analyzed data shows that the percentage change in IO power is 2.24% and leakage power changes by 83.3%. Table 5. Power Dissipations at Five Different Voltages using LVCMOS_18 Voltage
Clock
Logic
Signal
IO
Leakage
Total
Supply Power
0.5 0.8 1.0 1.2 1.5
0.094 0.184 0.258 0.342 0.490
0.063 0.161 0.251 0.362 0.565
0.147 0.375 0.587 0.845 1.320
2.090 2.104 2.114 2.123 2.138
0.030 0.039 0.052 0.079 0.180
2.423 2.863 3.261 3.751 4.692
2.754 3.055 3.261 3.475 3.826
Figure 9 shows clearly variation in power dissipation of different on-chip component, of DES Algorithm. In graph we notified that maximum leakage power dissipation is at 1.5V and IO power has very small variation.
Figure 10. Graphical Representation of Power Dissipation using LVCMOS_18 c) LVCMOS_25 LVCMOS_25 are only available in the HR I/O Bank. It is bidirectional standard. The drive current supported by LVCMOS_25 is 4mA, 8mA, 12mA and 16mA. In Table 6, we notified that in IO power there is 2.24% variation and 83.3% variation in leakage power.
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International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
Table 6. Power Dissipations at Five Different Voltages using LVCMOS_25 Voltage
Clock
Logic
Signal
IO
Leakage
Total
supply power
0.5 0.8 1.0 1.2 1.5
0.094 0.184 0.258 0.342 0.490
0.063 0.161 0.251 0.362 0.565
0.147 0.375 0.587 0.845 1.320
3.789 3.804 3.813 3.823 3.837
0.032 0.043 0.060 0.094 0.490
4.125 4.567 4.969 5.466 0.565
4.457 4.760 4.969 5.187 1.320
Figure 10, clearly show above mentioned observation. Using this IO standard we observed least variation in total power and supplied power.
Figure 11. Graphical Representation of Power Dissipation using LVCMOS_25 d) LVCMOS_33 LVCMOS_33 standard shows similar availabilities as in LVCMOS_25. In Table 7 and Figure 11, we notify that IO power changes by 0.72% and leakage power varies by 88.1% when we change voltage from 0.5V to 1.5V. Table 7. Power Dissipations at Five Different Voltages using LVCMOS_33 Voltage
Clock
Logic
Signal
IO
Leakage
Total
supply power
0.5 0.8 1.0 1.2 1.5
0.094 0.184 0.258 0.342 0.490
0.063 0.161 0.251 0.362 0.565
0.147 0.375 0.587 0.845 1.320
6.543 6.557 6.567 6.576 6.591
0.037 0.053 0.077 0.127 0.311
6.883 7.330 7.739 8.252 9.276
7.217 7.525 7.739 7.968 8.368
Figure 12. Graphical Representation of Power Dissipation using LVCMOS_33.
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Copyright ⓒ 2016 SERSC
International Journal of Software Engineering and Its Applications Vol. 10, No. 6 (2016)
8. Total Power and Supply Power Variation at Various Voltages Level Total power is the combination of static power and dynamic power. As we know that when actual design is implemented on FPGA, there are certain variations in supplied power and total power consumed. Here, we have done analysis of total power variation with respect to the supply power, at five different voltage levels.
Voltage > 1.0V • There is an increase in total power consumption in comparision to supply power
Voltage
