FPGA Implementation of 2x2 Crossbar Switch.pdf

DOI 10.4010/2016.1761 ISSN 2321 3361 © 2016 IJESC `

Research Article

Volume 6 Issue No. 6

FPGA Implementation of 2x2 Crossbar Switch Aniket Kumar1, Gaurav Gautam2, Vijay Kumar Ram3 Assistant Professor 1, 3, M.Tech Scholar2 Shobhit University, Meerut, India1, 2, CSS University, Meerut, India3 [email protected], [email protected], Vijayk10ster @gmail.com3

Abstract: Crossbar Switch is switching equipment mainly used to manage signal traffic at telephone exchange. It is an assembly of individual switches between set of inputs and set of outputs. This equipment can be implemented using metal wires and switches using fusible wires. This paper presents the FPGA implementation of 2*2 Crossbar switch using VHDL coding, as FPGA implementation is advantageous for having programmable interconnects that are volatile in nature, number of IO ports and is less expensive. The system is implemented on SPARTAN 3E. Keywords: Field Programmable Gate Array (FPGA), Vary high speed integrated circuits((VHSIC) hardware descriptive language, Finite state machine (FSM). I. INTRODUCTION Crossbar switches are extensively used today in a variety of applications including Network switching, parallel computing and various communications applications. There are off-thebookshelf devices available that implement standard crossbar configurations[1].The basic idea of crossbar switching is to give a matrix of n*m sets of contact with only m+n activators or less to select one of then n*m sets of contacts. This form of switching is also Known as coordinating switching [2]. M1 ’

c) Connection release. T H 6

H 4

M2 ’

N 7 N 6

a

M 1

N 8 N 5

T N 9

T

T T

N 4

b M 2

N 1

H 1

Fig.1.1 2*2 Crossbar switching II. SWITCHING METHODS Circuit Switching -In this switching, an electrical path is maintained between the source and the destination earlier than any data transfer takes place. The Circuit may be realized by physical wires or coaxial cables. No other potential user can use the path even if it is idle. Three explicit phase involved in circuit switch data transfer: a) Connection establishment b) Data transmission

International Journal of Engineering Science and Computing, June 2016

T

N 2

N 3

T

H 3

H 2

Fig. 1.2 Circuit switched Network PACKET Switching- In the early years of 21st century, communication by packet flow in large-scale computer networks becomes much more important in our life than ever before. The problem of finding the shortest path between two nodes is a familiar problem in network analysis. Shortest path algorithms have been a subject of extensive research, resulting 7435

http://ijesc.org/

in a number of algorithms for various situations and constrain. Adaptive routing algorithms , which can select the route of packets dynamically, have been extensively studied to make the best use of bandwidth in interconnection networks of especially parallel computers and system area networks (SANs)[3]. Basically in packet switching messages are split into a numbers of packet , often fixed in size, and the packets are transmitted in store and forward fashion

4. Choose an appropriate link towards destination based on certain routing criterion 5. Forward the message to the next mode III. STATE DIAGRAM In order to implement 2*2 crossbar switch we have considered two inputs IA and IB, each of eight bits and two outputs each of eight bits i.e. O1 and O2. The crossbar is controlled by two inputs : requestA and requestB. These control inputs are used by two different clients using crossbar. When the crossbar gets request by client A/B using requestA/B, it attempt to satisfy with an acknowledgement signal grantA/B, informing client that request has been granted. For the output that is used by a clientA/B and at the same time it gets request for the same output by client B/A, then crossbar ignores request. However if crossbar is idle and gets request from clientA and clientB both at the similar time, it grants both the request so long as they are for different outputs, if both client request for the same output then , in such situation on the priority basis connection is made (A has been given higher priority in implementation) . In order to explain the mechanism of Crossbar we have use FSM using three state i.e. busyA ,idle, busyB.

Fig. 1.3 Packet Switching Network H stands for Host Processor T stands for Terminal N stands for Switching Node Message switching- In message switching, one time the transmission is started, a message is transmitted in its entirely without a break from one mode to other.the functions of node processor are 1. Receive the full user message and store the same. 2. Check the message for data transmission errors and performed error recovery if required. Fig.1.4 RTL Schematic of 2*2 crossbar 3. Determine the destination address from the user massage

International Journal of Engineering Science and Computing, June 2016

7436

http://ijesc.org/

Timing Summary: Minimum period: 5.367ns (Maximum Frequency: 186.333MHz) Minimum input arrival time before clock: 6.106ns Maximum output required time after clock: 4.063ns

Fig. 1.5 State diagram IV. SIMULATION AND RESULT The VHDL code of 2*2 crossbar switch has been successfully simulated in Xylinx-ISE 14.7 using Modelsim- SE mixed as simulator and then synthesized using XylinxSpartan3E:XC3S100E.

Fig 1.7 shows the simulation result , The timing diagram is explained in tabular form, for convenience some short form used are idle(i), Busy1(B1), Busy2(B2), RequestA(rA), request(rB), grantA(GA), grantB(GB), reset(rst) , releseA(rlA), releseB(rlB), statusA(As), StatusB , (Bs) and not a connection as (nac). RequestA/B is two bit wide. A(1) shows user needs to connect himself and A(0) bit indicates type of output needs to be connected. So, A=00 and 01 are unused combination and similarly for RequestB.

Fig.1.6 Snapshot of circuit

International Journal of Engineering Science and Computing, June 2016

7437

http://ijesc.org/

Fig. 1.7 Model Sim Simulations Result

Time (ns) Rst IA IB O1 O2 rA rB rlA rlB GA GB As Bs

Table-2 Truth Table for Crossbar .5 1 1.7 2 2.8 3.5 4

4.5

1 AE FC 00 00 10 11 1 1 0 0 i i

0 AE FC 00 00 00 01 1 1 0 0 nac nac

0 AE FC AE FC 10 11 0 0 1 1 B1 B2

1 AE FC 00 00 10 10 1 1 0 0 i i

0 AE FC AE 00 10 10 0 1 1 0 B1 i

0 AE FC FC 00 11 11 0 1 1 0 B2 i

0 AE FC FC AE 11 10 0 0 1 1 B2 B1

0 AE FC 00 AE 00 10 1 0 0 1 nac B1

V. CONCLUSION AND FUTURE WORK In this paper, Crossbar switch is implemented and successfully executed to obtain the design summary . This switch has two controlling parameters that can further be increased depending on the no. of clients . Similar work may be extended for 4*4, 8*8 crossbar switch. This work may be further extended for Simulation & Design of Telephone (landline) Switching System. Also priority nature for the collision situation has much scope of research. REFERENCES [1] Gajendra singh Chandel , Ravindra Gupta, Arvinda Kushwaha,.”Implementation of shortest path in packet switching Network using Genetic Algorithm”, “International Journal of Advance Research in Computer Science and Software Engineering”, vol.2,Issue 2,feb. 2012.

International Journal of Engineering Science and Computing, June 2016

[2] B. Deli, Y. Alekhya, P. Diva Bharathi, “FPGA Implementation of an Advanced Traffic ”, “.International Journal of Advanced Research in Computer Engineering ” ,Vol. 1, Issue 7, September 2012. [3] Thiagarajan Viswanathan, “Telecommunication Switching Systems and Networks”, Published by Asoke K. Ghosh, Prentice hall of india private limited, 24 th printing in July 2005, pp-74,403,411,412. [4] MANO.M.M.,Computer Engineering : Hardware Design Englewood cliffs, NJ: Prentice-Hall,1988M. Young, University Science, 1989. [5] Aniket kumar, Sumit kumar, Ajit Singh and Divya Garg , “FPGA Implemantation of traffic light controller using VHDL”, Student Symposium on Information & communication technologies”, on Feb 7 , 2014,. Amity institute of Telecom Engineering & Management(AITEM) and IETE Sub-Centre, Amity University , UP, India., pp4043. [6] Aniket Kumar and Ashwani Kumar Pandey, “Fpga Implementation Of Advance Traffic Light Controller”, Presented at National Conference on Broadband & Optical Fiber Technologies on March 13-14, 2015, Conducted by ABES Engineering College, Ghaziabad, UP, India and financially supported by IEEE UP Section. [7] J.Bhaskar, A VHDL Primer,Third Edition ,Allentown, PA Pearson publication. [8] Douglas L.perry, VHDL Programming Example,Fourth Edition ,McGraw-Hill.

by

[9] John F. Wakerly, Digital Design, Fourth Edition, Pearson

7438

http://ijesc.org/