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Abhishek Basu et al. / International Journal of Engineering Science and Technology (IJEST)

FPGA IMPLEMENTATION OF IP PROTECTION THROUGH VISUAL INFORMATION HIDING ABHISHEK BASU†, DEBAPRIYA BASU ROY‡, DEEP BANERJEE‡, ARCHAN SENGUPTA‡, ANIKET SAHA‡, TIRTHA SANKAR DAS† AND S.K. SARKAR† †

ETCE Dept., Jadavpur University, Raja S. C. Mallick Road, Kolkata, 700032, India

‡

ECE Dept., RCC Institute of Information Technology, Canal south Road, Beliaghata, Kolkata, 700015, India

Abstract: IP based design is one of the most potential techniques to promote the SoC design promptly into market. To assist the process it is advantageous to have IP exchanged in different forms. Though, sharing IP blocks in today’s aggressive market poses significant security risks. Proving that a given IP is derived from a patented method or technique is in general a conscientiously time-consuming task, often requiring reverse-engineering and forensic investigation of IP. These techniques are so multifaceted that their uses to a huge collection of marketable products are almost always unaffordable. So protection of IPs in VLSI design has received a deal of interest in recent era. In this paper, we present an approach based on the embedding of the ownership proof as part of the IP design’s finite state machine (FSM) by means of visual information hiding. Keywords: Visual Information Hiding, Intellectual Property protection, copy detection, FSM, sequential circuits, state transition graph, FPGA. 1. Introduction Rapid advancement in IC processing technologies have enabled new paradigm of the “System-on-a-Chip” (SOC) technology and have changed the traditional system design methodology. Reusable virtual components or Intellectual Property blocks (IPs) based designs have become more and more important. IP plays a vital role in the design-for-reuse methodology which reduces cost and development time of SOC designs. There exist three basic types of IP, based on its characterization through (a) behavioral description (soft IP), (b) structural description (firm IP), and (c) physical description (hard IP). IP design is a big venture for companies; on the other hand, sharing IP designs create considerable high security risks. Most of this IP required time and effort to be designed and verified, but they can be hackneyed, or modified to cover up the authorship confirmation. Designers and proprietors of IP designs want guarantee that their contents will not be unlawfully redistributed by clients, and customers want assurance that the contents they buy are genuine. Piracy problems can be categorized in the following three classes: 1) Illegal Access, where the pirate tries to obtain a product without authorization; 2) Intentional Tampering, where the pirate modifies a product in order to remove/include features for malicious motives and then proceeds to its retransmission. The genuineness of the original product is lost; and 3) Copyright Violation, where the pirate receives a product and resells it without getting the permission from the copyright owner. In order to resolve above problems, the VSI Alliance IP protection development working group [1] identifies three major approaches to secure IPs: deterrent, protection, and detection. The first uses legal means, such as patents, copyrights or trade secrets to stop attempts for illegal distribution. The second prevents the unauthorized practice of the IP physically by license agreements and encryption. The third detects and map out both lawful and unlawful usages. In this paper, we present a scheme for IP protection technique that can be used near the beginning in the design cycle, mainly on the behavioral levels by means of Visual Information Hiding. Visual Information Hiding can be categorized as steganography, cryptography and watermarking of them watermarking has some inherent advantages like robustness, inseparability from the cover etc. which make it admired and superior. So watermarking is chosen as safety mechanism in our arrangement.

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The rest of the paper is organized as follows: Section 2 describes related approaches from the open literature. Section 3 gives a brief description on our IP protection technique. Section 4 presents a prototype implementation of the proposed method. Section 5 includes experimental results. Finally, Section 6 concludes the paper. 2. Related Work Watermarking has been projected to protect digital audio and visual IPs. The literature is especially widespread on the issue. Here we bring up only two workings [2, 3] as they allow us to introduce some of the techniques used. IP watermarking fall into two classes [4] dynamic, where the watermark is detected by running the watermarked IP and static, where the watermark is considered as a property of the design. In this paper we are concerned primarily with FSM watermarking techniques. In following we will limit our discussions to these techniques. For more information about other watermarking techniques, the reader can refer to a survey given in [5] and about few other techniques given in [6]. Torunoglu and Charbon first introduced an IP protection technique through FSM watermarking [7]. The algorithm principally based on extracting the unused transitions in a state transition graph (STG) of the behavioral model. These unused transitions are inserted in the STG and linked with a fresh defined input/output sequence, which will work as the watermark. The main advantage of this approach is the ability to detect the presence of the watermark at lower design levels. The next approach was by Oliveira is FSM watermarking by property implanting [8]. The author manipulates implicitly the STG of the finite state machine to implant the watermark as a property in the new one by adding extra states and transitions in a systematic way to satisfy this property. The algorithm has a low overhead on the design flow, because it does not need to go through the FSM to find the unused transitions. One of the main challenges of watermarking schemes is the authenticity of the watermark. This problem is solved by using a secure third party [9, 10]. A body that will be responsible for generating and distributing time-stamped authenticated signatures, as well as keeping a proof for such signatures for the extraction phase. 3. IP Protection Technique In this paper a scheme has been adopted to implant a watermark at the highest level of abstraction, i.e. at the Hardware Description Language (HDL) level. Nearly all HDL representations have one or more sequential functions. In its most common form, a sequential function is a utility that transforms input sequences into output sequences. Regular sequential functions are functions such that at any step the output depends only on the order of inputs which have been already received. Any standard sequential function working on finite input/output set can be specified by means of a Finite State Machine. We propose an approach in which together existing and unused transitions in the FSM are used to insert the information. In case of completely specified FSM, extra input/output bits are added to embed the information. In big sequential designs, generally a number of such small FSMs exists which can be used to watermark the whole design by watermarking the entire or a selected subset of these FSMs. The sequences of input and output bits in a FSM are represented by State Transition Graphs (STGs) and State Transition Tables (STTs). To find out an unused input/output symbol sequence and to use it as the watermark, every state of a STG representation of the sequential function visited. After calculating the required input/output sequence length which satisfies the inimitability limitation of watermark [11] a sequence created by selecting sufficient input/output pairs. If the input/output pairs are not adequate, then the input and/or output augmented by additional ones. Finally, by connecting the states, a trace is generated in the FSM. The algorithm for insertion of watermark state and transition between the states are given as: Insertion of watermarked state: Step 1: Insertion of the STG. Step 2: Finding the minimal spanning tree from the STG. Step 3: Calculation of the number of states from the tree, starting from a terminal state and ending at another terminal state. Step 4: If number of state is n, calculate i such that i= log2n Step 5: Check whether 2i=n, if yes go to step 6, else go to step 7 Step 6: If 2i=n, all the states are occupied and to insert watermarked state we need to add one bit extra which is logic high only at the watermarked state. Set i=i+1 and n=n+1. Step 7: If 2i ≠n insert a watermark in an unused state and set n=n+1; Step 8: After each insertion check, check whether all the required watermarked states are embedded or not, if yes, stop. Otherwise go to step 5

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This algorithm will only create the watermarked states, but transition between the states will be created in transition algorithm. Transition between states: Step 1: Marked the states in the STG. Step 2: For a particular state, check whether there is any unused transition. Step 3: If yes, use this transition as a transition to first watermarked state. Step 4: If no, create a transition by adding an extra bit which will be logic high only for the transition for the first watermarked state. Step 5: Repeat this process for each discrete state. Step 6: From the W1 (first watermarked state) create a transition to W2 (second watermarked state) with no i/p dependence. Step 7: Repeat this for W2 to W3, W3 toW4……… until one reaches the last watermarked state. Step 8: From the last watermarked state, create a transition to any of the discrete state with no i/p dependence. The algorithms are illustrated using the example given below. A simple FSM of figure 1 is considered to be a given FSM and both the algorithms are applied on it to create the watermark states and transition between them. In this FSM there are 5 states and the requirement is to add 4 watermarked states based on the calculation from minimal spanning tree. From insertion of the watermark algorithm the value of i is 3 and 2i >n . So there are free states which can be utilized as watermarked state. Figure 2 shows the FSM after the addition of first watermarked state.

Fig. 1. Given simple FSM.

Fig 2. FSM after the addition of first watermarked state

Now n=n+1 and the above is process repeated until 2i=n. So after those processes FSM will look like Figure 3.

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Fig 2. FSM after the addition of first watermarked state

After addition of three watermarked states, n=8 and 2i=n. Still one watermarked state is required to be added. So another extra bit is added which is at logic high only for the last watermarked state and at logic low for other states. Figure 4 shows the FSM after adding all states.

Fig 4. FSM after the addition of all watermarked states

Now it is needed to add transition to the watermarked states. It can be observed that for state P, Q, S, T, three transitions are used. Hence there is an unused transition for these states which will be utilized for the transition to the first watermarked state. Figure 5 represent the FSM after having first watermark transition.

Fig. 5. FSM after first watermark transition.

For the state R, there is no unused transition, hence an extra bit which will be at logic high only for that transition and at logic low for the other transition need to add. Finally it is just needed to add transition to the other watermarked states with no input dependence and the transition from the last watermarked state to any discrete states. So finally the FSM will look like Figure 6.

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Fig. 6. Final FSM after adding all transition.

3.1 Prototype implementation of Proposed Method

For FPGA implementation of the proposed technique we started with a FSM which shown in Figure 7. For every input sequence in FSM results in a unique output sequence. Both algorithms are applied on FSM to generate the watermark states and transition connecting them. The watermarked FSM is shown in figure 8. The RTL model for the FSM before and after watermark been implemented by means of synthesis, translate, map, place and route on Xilinx (ISE version 11.1i). The behavioral simulations done with Xilinx ISim and test benches were written in VHDL to give the input vectors for the simulated programs. For function verification it is tested on Spartan series of FPGA (device: xc3s500e-4fg320).

Fig. 7. FSM

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Fig. 8.The watermarked FSM after adding states and transitions

To produce the circuits for FSM and watermarked FSM both the state diagram translated into state table and from there on state assignment table which help to generate sequential circuits by the help of state variables.

Watermark state machine having 9 water marked state and 7 discrete states (total 16). After minimization the equations for combinational circuits in present state and next state are given below. Equation (1)-(6) represents the state and output equations for FSM.

A = a ′de′ + a ′df ′ + c′de′f + b′de′f + c′def ′ + b′def ′ + ab′d′e′f ′ + ac′d′e′f ′; (1) ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ B = ab df + a def + c d ef + a d ef + b d ef + a b d e + abc e f + a bd e f ; (2) C = a ′de′f + ab′c′de′ + abc′df ′ + ac′d′ef ′ + a ′bc′d′e + a ′b′d′ef + a ′b′c′d′f + ab′ce′f ′ (3) + ab′cd′f ′ + a ′bcd′f ′ + a ′cd′e′f ′ ; Z2 = a; Z1 = b; Z0 = c;

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(4) (5) (6)

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Now depending upon these equations circuits are implemented on Multisim (National Instruments, version 10) and figure 9 representing the circuit for FSM.

Fig 9: Circuit of the simple FSM (Implemented in Multisim)

Fig 9: Circuit of the simple FSM (Implemented in Multisim)

Watermarked states have a special property. Once a FSM enters into a watermarked state, it will move into the next watermarked state irrespective of the input and this will go on until the FSM reaches to the last watermarked state. Then it will return to the initial state. Hence design of the watermarked states requires special attention. Figure 10 represents the transition between the discrete state and watermarked state.

W1 Discrete states

W9

Other watermarked state

Fig 10: Transition between watermarked states and discrete states

Equations (7)-(9) correspond to the discrete state equations for the FSM A= a ′d + ab′e′f ′d′ + ac′d′e′f ′ + b′de + b′df + c′de + c′df ;

B = a ′b′e + a ′ef + b′ef + c′ef + a ′bd′e′f ′ + a ′de + ab′df ′ + abc′e′f ′ ; C = a ′df + b′def + a ′b′ef + a ′b′c′f + ab′c′de′ + abc′df ′ + abc′de + ac′d′ef ′ + a ′bc′d′e + ab′ce′f ′ + ab′cd′f ′ + a ′bcd′f ′ + a ′cd′e′f ′ ;

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The watermarked state equations given in (10)-(13)

Y3 = ga ′ + gc′ + gb′ + g′abc; Y2 = gac′ + gab′ + ga ′bc; Y1 = gb′c + gbc′; Y0 = gc′;

(10) (11) (12) (13)

Equations (14)-(17) represent the output equations

Z3 = g; Z2 = a; Z1 = b; Z0 = c;

(14) (15) (16) (17)

Based on these equations, the circuit for the watermarked FSM is given in Figure 11

4. Results

Fig 11: Circuit of the watermarked FSM (Implemented in Multisim)

This segment reports the simulation and synthesis results for the FPGA implementation. The RTL schematic of the original FSM and watermarked FSM are given to establish the fact that the HDL codes are synthesizable. The behavioral simulation result (Xilinx ISim) given in figure 12 and 13 for FSM and watermarked FSM. Figure 14 to 15 represent the RTL schematic and table 1 and 2 for design summaries report based on Xilinx ISE.

Fig 12. Behavioral simulation results for FSM

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Fig 13. Behavioral simulation results for Watermarked FSM

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Fig 14. RTL schematic of the FSM Table 1. Design Summary for FSM

Fig 15. RTL schematic of the Watermarked FSM Table 2. Design Summary for Watermarked FSM

5. Conclusion In this paper we have proposed a FSM based algorithm at behavioral level to protect intellectual property from copyright violation. The system will move into watermarked states after receiving a special input, known to manufacturer irrespective of its present states. Once in the watermarked states, it will produce a unique output. Actually this unique output represents the identity of manufacturer and hence the objective of copyright protection is achieved. The watermark embedding and extraction are discussed. Meanwhile the circuit functions before and after watermarking is verified and the experimental results are satisfactory References [1]

Intellectual Property Protection Development Working Group, “Intellectual Property Protection: Schemes, Alternatives and Discussion”, VSI Alliance, White Paper, Version 1.1, August 2001. [2] M. D. Swanson, B. Zhu, and A. H. Tewfik. Transparent robust image watermarking. In Proc. IEEE International Conference on Image Processing, volume 3, pages 211-214, September 1996. [3] L. Boney, A. H. Tewfik, and K. N. Hamdy. Digital watermarks for audio signals. In Proc. IEEE International Conference on Multimedia Computing and Systems, pages 473-480, June 1996. [4] A. T. Abdel-Hamid, S. Tahar and E. M. Aboulhamid, “Hardware IP Watermarking for Copyright Protection”, Technical Report, Electrical and Computer Engineering Department, Concordia University, Montreal, Canada, June 2004. [5] A. T. Abdel-Hamid, S. Tahar, and E.M. Aboulhamid, ”A Survey on IP Watermarking Techniques”; International Journal on Design Automation for Embedded Systems, Springer-Verlag press, Vol. 9, No. 3, July 2005, pp. 211-227. [6] Chip-Hong Chang and Aijiao Cui “Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property”, IEEE Trans. on Circuits & Systems—I: Regular Papers, 2009. [7] I. Torunoglu, and E. Charbon, “Watermarking-Based Copyright Protection of Sequential Functions”, IEEE Journal of Solid-State Circuits, Vol.35, No. 3, February 2000, pp. 434-440. [8] A. L. Oliveira, “Techniques for the Creation of Digital Watermarks in Sequential Circuit Designs”, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001, pp. 1101-1117. [9] E. Charbon and I. Torunoglu. Copyright protection of designs based on multi source IPs. In Proc. IEEE International Conference on Computer Aided Design, pages 591{595, November 1999. [10] A.T. Abdel-Hamid, S. Tahar, and E.M. Aboulhamid ," A Public-Key Watermarking Technique for IP Designs", Proc. IEEE/ACM Design Automation and Test in Europe (DATE'05), Munich, Germany , March 2005. [11] I. Torunoglu and E. Charbon. Watermarking-based copyright protection of sequential functions. IEEE Journal of Solid State Circuits, SC-35(3):434-440, 2000.

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