High Linearity and Large Output Swing Sub-Hz Pre

High Linearity and Large Output Swing Sub-Hz Pre-amplifier for Portable Biomedical Applications Moacir F. C. Monteiro

Hamilton Klimach

Sergio Bampi

PGMicro - Instituto de Informatica

PGMicro - Dep. de Eng. Eletrica

PGMicro - Instituto de Informatica

Federal Univ. of Rio Grande do Sui

Federal Univ. of Rio Grande do Sui

Federal Univ. of Rio Grande do Sui

Porto Alegre-RS 91501-970

Porto Alegre-RS 90035-190

Porto Alegre-RS 91501-970

mfcmontei [email protected]

hamilton. [email protected]

bam [email protected]

ABSTRACT

This paper presents a high-linearity and large output swing instrumentation amplifier for portable multichannel biomed­ ical applications. It is composed of a fully differential two­ stage CMOS amplifier in which a feedback provides stable signal gain that can be adjusted from 25 to 100 V IV. Addi­ tionally, a pseudo-resistive feedback combined with an ap­ propriate input capacitive coupling provides a high-pass be­ havior, presenting a -3 dB cut-off frequency lower than 120 mHz. The amplifier is fully integrated in a 130 nm CMOS process, using only 0.1 mm2 of silicon area, including large matched capacitor banks. Its power consumption is 31.3 f.LW under a 1.5 V supply. The pre-amplifier gain reaches less than 0.02 % of THD (total harmonic distortion) for an output swing of 2 Vpp in post-layout simulations. The to­ tal input-referred noise estimated from simulations is 1.93 f.LVrms inside the 0.5 Hz to 500 Hz frequency range. Categories and Subject Descriptors

B.7 [Hardware]: Integrated Circuits Keywords

Analog integrated circuits, biosignal, biomedical, amplifier, fully integrated, high linearity, sub-hetz. 1. INTRODUCTION Signal acquisition systems require both good analog-to-digital converter (ADC) and a signal conditioning circuit which guarantees high fidelity of the signal at the ADC input. Lin­ earity, low-noise, and accuracy are key, with respect to the sensor signal. A good signal conditioning circuit must assure that its output signal has linearity and noise characteristics compatible with the ADC's SNDR (Signal-to-Noise and Dis­ tortion Ratio) so that the ENOB (Effective Number Of Bits) achieved in the end is compatible with the capability of the ADC. While these issues might seem trivial in a circuit de­ sign with discrete components, the limitations imposed by current CMOS technologies seriously restrict the fabrication Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial ad vantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise. or republish. to post on servers or to redistribute to lists. requires prior specific permission and/or a fee. Request permissions from [email protected]. SBCCT '14. September 01 - 05 2014. Aracaju, Brazil Copyright 2014 ACM 978-1-4503-3156-2/14/09$15.00. http://dx.doi.org/l0.1145/2660540.2660975

of conditioning circuits which are completely integrated on a single chip, especially in applications involving very low frequency signals. For that reason, completely integrated circuits designed for bio-potential signal conditioning have been the topic of active research in the last decades, as it will be shown in this section. The greatest design challenge for such circuits is related to the frequency range of interest: physiological signals have frequency components in the DC to units of kHz range [1] . However, the slow electro-chemical processes that develop between the electrode-skin interface constitute a source of interfering signals in the sub-Hz frequency range [2] , de­ veloping offset voltages in the electrodes which can have amplitudes of up to tenths of m V [3]. This electrostatic potential has the same order of magnitude of the desired biological signals to be acquired. Fortunately, the greatest energy content of these relevant biological signals is located above 1 Hz, which allows the attenuation of those undesired signals through a high-pass filter with a Hz or sub-Hz cut-off corner placed before the amplification stages. An RC filter, passive or active, with cut-off frequency tar­ geted in the order of Hz, requires resistances and capaci­ tances of high value for its implementation inside an IC. Due to either cost or physical limitations of current CMOS tech­ nologies, the availability of integrated capacitors is usually limited to maximum values of hundreds of pF. Integrated resistors are limited to tenths of !vIn. However, components in these ranges of value already represent a significant cost in silicon area. For that reason, external components are frequently used to implement these filters, making the final product larger in circuit-board area, costlier and less robust [4], [5]. Many strategies have been proposed in the recent years of­ fering alternative solutions for these issues. In [6]' a pre­ amplifier using a transconductance integrator (Gm-C) in a negative feedback loop is used to provide simultaneously gain and high-pass behavior, with a 200 mHz pole. To allow a complete integration of the circuit, the amplifier was designed to offer an extremely low transconductance, using source degeneration and current division techniques [7]. Other low-transconductance amplifier circuits for Gm­ C filters using the bulk-driven and series-parallel association techniques are described in [8] and [9], respectively. Even though these circuits achieve transconductances in the or­ der of hundreds of pS, these techniques are extremely costly

in terms of area, as they require capacitors greater than 100 pF to obtain a pole below 1 Hz. The integrator in the feed­ back loop can, still, be replaced by an operational amplifier (OpAmp) operating as a low-pass filter, as presented in [19] ' where a Miller compensation scheme and cascode circuits have been used to reach 0.24 mHz cut-off frequency. All of these circuits, however, present low linearity, resulting in a total harmonic distortion (THD) in the order of 1 % (40 dBc) [10] or more, for the maximum output signal excursion. A simpler solution, with a high-pass filter followed by an amplifier, was proposed in [11] . The high resistance device of the filter consists of a PMOS transistors operating at a very low inversion level, adjusted by its gate voltage, while the reactive portion of the filter corresponds to the capac­ itance of the gate terminal itself. However, the necessity of trimming due to high process variability which impairs the transistors behaviours, together with the electrical pa­ rameters variations also present in the electrodes fabrication [12] , limit the practical implementation of this approach, es­ pecially in biomedical applications for which multi-channel circuits are required. Pre-amplifier topologies with capacitive coupling and feed­ back are frequently used to achieve gain and offset or low fre­ quency noise rejection of the electrodes. In these circuits, a high-pass pole is obtained through a DC path in the OpAmp feedback path, using MOSFETs biased with constant volt­ age, as proposed in [13] and [14] . Pseudo-resistors, using pMOS transistors connected as MOS-diode-Bipolar [15] , are also widely used for this purpose. In [16] a neural signal pre­ amplifier was proposed, using a series connection of pseudo­ resistors to increase the resistance and the linear excursion of the signal. Similar topologies were employed in [17] and [18] , but all of them present low linearity or limited excur­ sion ranges. In this paper, a circuit topology for pre-amplification of bio­ electrical signals is proposed and designed aiming to achieve high linearity and high-pass filtering with a cut-off frequency well below 1 Hz. The pre-amplifier developed is targeted to portable acquisition systems, used for the monitoring of differential signals, such as electro-miography (EMG) and electro-cardiography (ECG), with a minimum SNDR of 74 dB (or 12 ENOB). This circuit operates from a 1.5 V power supply, and it has a programmable gain between 25 and 100 V IV. The output differential maximum excursion required in our design is 2 Vpp. The text of this paper is organized as follows: section II dis­ cusses both the behavior of the PMOS diode used as a high resistivity device, and the circuit topology employed to as­ sure linearity of the pre-amplifier. This section describes as well the compromises involved in the design of the OpAmp. In section III the sizings of the transistors and other circuit components are presented, and section IV demonstrates the simulation results achieved after layout for the entire CMOS­ based circuit. In Section V conclusions of the paper and future work are presented. 2. CIRCUIT DESCRIPTION Among the strategies used to implement pre-amplifiers with integrated filters for very low frequencies, the ones resulting

.!!!.. R(VaJ iC2

-

C2

Va

(a)

Va

(b)

Figure 1: Basic pre-amplifier topology with high-pass filter using pseudo-resistor (a); Equivalent circuit for analysis (b).

(a) MOS Diode

(b) BJT Figure 2: Pseudoresistor model. (a) MOS Diode when Va Vb; (b) Parasitic BJT when Va < Vb.

>

in smaller circuits are those using pseudo-resistors, in the configuration shown in Fig. l(a). The obtained resistances, however, are highly non-linear due to their exponential de­ pendence with the applied voltage amplitude [15] . A highly linear resistance, however, is not strictly necessary. In Fig. 1(b), as long as the current that passes through the resistive element in the feedback loop, JR, is sufficiently low in com­ parison with the displacement current which passes through capacitor C2, JC2, its contribution to the linearity of the pre-amplifier can be neglected. This condition is usually satisfied by reducing the signal excursion over the pseudo­ resistor, keeping the resistance extremely high for the whole excursion. 2. 1 Pseudoresistor As described in [15] , the electrical model of the pseudo­ resistor (Fig. 2) depends on the polarity of the applied drain-source bias: when VA > VB, the device behaves as a diode-connected PMOS operating in weak inversion (W.I.) (Fig. 2(a)); when VA < VB, the device behaves as a bipolar PNP parasitic transistor with a grounded substrate collector and a secondary lateral collector (Fig. 2(b)). The simulated curve of the incremental resistance as a function of the volt­ age applied to the pseudo-resistor is shown in Fig. 3, for the highest conductivity process corner (Fast). In the simu­ lations, a thicker-oxide for 2.5 V PMOS transistor from the IBM 130 nm CMOS process was used, with a long channel L 4011m and W 111m. For the simulation of this transis­ tor the PSP model wos used, suitable for simulations using very low drain voltages. Due to the characteristics of the =

=

� 107 ���� � � -0.5 -0.4 -0.3 -0.2 -0.1 __

__

( a)

�__�__�__�__�--3

__

0

!N(V)

0.1

0.2

0.3

0.4

0.5

Figure 3: Simulated incremental resistance for the pseudo­ resistor. thicker-oxide transistor, even under negative bias condition with small values of 6 V, the channel current is sufficiently high to determine the resistance of the pseudo-resistor, as shown in Fig. 3. Even though the operation region around 6V 0 is not appropriately characterized by most foundry­ supplied models, measured data presented in [16] and [17] show that the pseudo-resistances can be as high as Tn for very long channel PMOSFET in weak inversion or accumu­ lation. =

2.2 DC Feedback with Improved Linearity The pre-amplifier topology proposed is shown in Fig. 4. It consists of a fully-differential OpAmp with resistive atten­ uator on the feedback loop, which defines the signal excur­ sion over the pseudo-resistor. To avoid problems with leak­ age currents in the extremely high impedance nodes, the bulk terminal of the pseudo-resistor is connected to the re­ sistances, in a way that leakage currents of the order of pA do not contribute to an offset at the output. The gate ter­ minal is connected to a reference, making sure that the gate capacitance does not compromise the gain or linearity of the circuit. The equivalent resistance, in parallel with C2, as seen from node "A" is

Req

=

Rl +

(1 �:) RPR, +

(1)

where Rp R is the pseudo-resistor resistance discussed above. The high-pass pole of the system is defined by 1/27r ReqC2. It is important to observe that, establishing a feedback loop with DC gain greater than unity, the offset voltage at the input of the OpAmp will be present at the output multi­ plied by the factor (1 + R1/ R2). The OpAmp design must, therefore, guarantee a low offset voltage to avoid interfering with the functioning of the circuit. A rigorous analysis of the contribution of the pseudo-resistor to the non-linearity of the pre-amplifier is very hard, since there is no precise analytical model to describe the behavior of the transistor operating under such conditions. For that reason we present in this work a graphical analysis, obtained through simulation. Fig. 5 shows the simulated linearity of the proposed circuit, as a function of the R1/ R2 ratio, for different values of C2. In the electrical simulations, the

Gain Control

( b)

Figure 4: Proposed pre-amplifier with high-pass filter(a ) . Gain-control capacitor bank schematic ( b ) .

iIi'

� I f-

80 74 60 40 4

6

8

10

R/R2

12

14

16

18

20

Figure 5: Pre-amplifier linearity as a function of R1/ R2 ra­ tio, for different values of C2.

highest conductivity process corner was used, with an AC gain of 40 dB and sinusoidal input signal of 10 Hz and 20 m Vpp amplitude. To keep a compromise between area and offset, the capacitance C2 was defined as 280 fF, ensuring the OpAmp achieves the minimum desired THD of 74 dB ( necessary for 12 bits resolution ) , or 0.02%, calculated for the resistor ratio R1/ R2 12. The expected high-pass pole frequency in this case is about 112 mHz. =

2.3 Operational Amplifier Fig. 6 shows the schematic of the OpAmp used in the pre­ amplifier. The circuit is composed of a two-stage Miller transconductance amplifier ( OTA ) , which is more appropri­ ate for high gain, low noise and low offset applications, as well as high output voltage swing [20]. To provide the resis­ tive load in the feedback, the buffers shown in Fig. 7(a ) were used. These consist of a common-drain stage using native transistors from the technology (V T H � OV), to guarantee output swing with highest possible rail-to-rail excursion for the 1.5 V power supply. 2.4 Noise Analysis As long as a high gain is guaranteed by the first stage of the OTA, the total output noise of the OpAmp is dominated by the contribution of transistors Nh and N12 in Fig. 6. The noise spectral density generated by lvha.lb at the output of the pre-amplifier in closed loop is given by

(2)

1.5

0 -10 1il-2O "0

�"5

Vo-

>

c-30 'ro CJ -40

0

0.5

0

-50

�60mV 0

0.5

1

1.5

Vin(V) (a)

Figure 6: Operational amplifier schematic.

-60 105 106 107 108 109 1010

Frequency(Hz) (b)

Figure 8: Buffer DC transfer characteristic (a); Frequency response for a lOpF load (b).

+-�--oVcmfb

v� ± 0---1

AVdiJf Vocm

i----tt-----t-oVbias3

(a)

while the contribution of !vI2a.2b is given by 2 1 Kf2 gm2 4i2KBT , Sna2 2 +2 2 C'ox2 W2D 2 1m f2 Af gm12 gm2

(

)(

'

--

)

Af

=

C2 ' C1 + C2 + Ci

(4)

where Ci is the input capacitance of the OpAmp. Since the bank capacitances are always connected to ground or the input, the feedback attenuation is the same independently of the programmed gain. As long as Ci is kept sufficiently low in comparison with C1, the value of Af will be approximately 0.01, or the inverse of the pre-amplifier' s gain. 2.5 Common-Mode Feedback and Stability The CMFB scheme employed consists of a single common­ mode feedback loop, using the frequency compensation of the differential signal path, given by capacitance Ce, as pro­ posed in [18]. The common-mode output signal Vocm is ob­ tained in the attenuation loop itself, as shown in Fig. 4(a). The control common-mode signal is applied to transistor !V1s of Fig. 6. From Fig. 4 and Fig. 6, opening the loop at nodes

gm1 . Ra1 . AV2 . Aj,

(5)

--

where gm5-7 are the transconductances of !vis to !vh, re­ spectively, and R�l is the AC output resistance of the first stage from the common-mode signal point of view, which is slightly larger than Ra1 due to the cascode effect of !vh. To guarantee common-mode phase margin through the loop equal or greater than the differential-mode phase margin, we must satisfy

'

(3) where i is the thermal noise coefficient, KB is the Boltz­ mann constant, T is the absolute temperature, Kf is the flicker noise coefficient, mf is the flicker noise frequency ex­ ponent, C�x1 is the active gate capacitance per unit area, gm is the device transconductance and W and L are the width and length of the channel, respectively. Factor Af is the attenuation of the feedback loop. For medium and high frequencies, Af is given by

=

where gm1 is the transconductance of !Vh, Ra1 is the AC output resistance of the first stage, AV2 is the voltage gain of the second stage and Aj is the loop attenuation, given by (4). Opening the feedback loop at nodes B and B' (Fig. 4), the total gain of this loop is given by gmG , , (6) AVcm gm5' Ra1 . AV2 . gm7 =

(b)

Figure 7: OpAmp Buffer schematic (a); Low-gain amplifier for the CMFB circuit (b).

=

A and A' , the differential loop gain will be given by

(7) or, equivalently, (8) where N results from the choice of gm5 equal to N . gm7, such that !vI5 and !Vh for a current mirror with factor N. To reduce the voltage error at the input of the CMFB OTA, transistors !vI8 and !VIg are implemented with cascodes, not shown in Fig. 7 for simplicity. 3. CIRCUIT SIZING AND LAYOUT Due to the technology limitations, high resistances of the order of !VIr! result in a high area cost. So, resistance R1 is chosen as 500 kr!, and R2 results in 41 kr!. Capacitance C1 is 28 pF, composed of 4 parallel capacitors of 7 pF (Fig. 4(b)), allowing a programmable gain of 25, 50, 75 and 100

VIVo

The buffer has been sized to provide the necessary load cur­ rent, guaranteeing maximum output swing with bandwidth greater than 500 kHz (necessary for the closed loop sys­ tem to have a minimum bandwidth of 5 kHz), so as not to compromise the stability of the system. The input-output relationship of the buffer pair, for a 541 kr! load, is shown in Fig. 8(a) indicating that the buffer is able to achieve nearly the limits of supply. The buffer transfer function for a 10 pF load in parallel with the 541 kr! resistance is shown

: ::: ::: -- Gain 10-2

Figure 9: Pre-amplifier circuit layout.

10-1

10°

101

=

25VN 102

103

Frequency(Hz)

104

105

106

Figure 10: Amplifier frequency response for different gain configurations in worst-case process conditions.

in Fig. 8(b). It presents a bandwidth of 1.44 MHz, about three times the minimum gain-bandwidth product required for this amplifier. The OpAmp transistor sizing has been done to reduce the input stage noise to an acceptable level for the application. As a general rule, the RMS noise voltage inside the band­ width of the circuit must be less than 0.5VLSB (Least Signif­ icant Bit) of the AD converter. In our case, the pre-amplifier is designed for a 12-bit conversion system with full-scale volt­ age of 2 Vpp. Hence, an output noise RMS voltage below the 244 jJYRIv[S value is required. Using equations (2) and (3), together with the ACM MOSFET model equations, the de­ sign of the first stage was done to obtain a noise level below 244 /-lVRlvIs, keeping a compromise between area and en­ ergy consumption. The simplified model parameters of the thermal and flicker noise used in (2) and (3) were extracted through simulations using the BSIM4 transistor model, pro­ viding consistent results with series-parallel associations of transistors [21] required when large transistors are laid out as multi-finger fractured transistors. The noise calculated for the output of the pre-amplifier was 161 /-lV RMS. Due to the presence of the buffer, the second stage needs only to guarantee gain and signal excursion, since its load is small and allows it to operate with a very low current consump­ tion. In differential mode, the compensation capacitance Cc nec­ essary to stabilize the circuit in closed loop is 350 fF. How­ ever, satisfying the relationship given by (8) through the sizing of N and gm6 would result in a too low transcon­ ductance value for gm6, making the circuit too sensitive to mismatches in transistors lVha-b, lVha-b. So, the common­ mode and differential-mode stabilities were determined si­ multaneously through the choice of a larger value of Cc and the sizing of the OTA of Fig. 7(b), resulting in Cc 3.4 pF. The branches defined by lVIga-b were included to reduce the value of gm6 keeping gm7 constant. =

The layout of the pre-amplifier circuit, including the capac­ itor bank, is shown in Fig. 9, occupying a total area of 0.1 mm2 (277 /-lm x 377 /-lm). 4. RESULTS The simulated amplifier frequency response is shown in Fig.10. As specified, the high-pass cut-off frequency is well below the lower limit of useful EMG signals (0.5 to 500 Hz), still

Frequency(Hz)

Figure 11: Frequency spectrum and THD of a10Hz and 2Vpp sinusoidal output signal for typical (above) and worst­ case (below) process conditions.

N I N

G ill ·0 z

o (J) Il.

101

102

103

Frequency(Hz)

Figure 12: Power spectral density of simulated pre-amplifier input-referred noise. accounting for the frequency range of interest for ECG sig­ nal processing, which is 0.1 to 100Hz. Pre-amplifier band­ width is set by the OpAmp gain-bandwidth product, which is greater than 10 kHz. This allows the pre-amplifier to be used for measuring biomedical signals of higher frequency content, such as needle EMG. The simulated frequency spectrum responses for 1Hz to 1KHz sinusoidal input signals are shown in Fig. 11. We simulated both typical and worst process cases (Fig.11), for a 10Hz, 20mVpp input, with a 40dB gain. In the typical case, the THD obtained is 80.7 dB and, in the worst case, 74.7 dB, as expected. The total power consumption under 1.5V supply is 31.3 /-lW. Input-referred offset voltage of the operational amplifier is ±500/-lV for ±3a resulting in maximum output

Table 1: Performance Comparison of Biopotential Amplifiers [13]

[14]

[16]

[17]

[18]

[22]

This work*

Technology

1.5pm

0.13pm

1.5pm

0.5pm

0.13pm

0.13pm

0.13pm

Supply

±1.7V

1.5V

±2.5V

2.8V

IV

1.2V

1.5V

Power

27.2pW

1.5pW

80pW

7.56pW

12.1pW

1.92upW

31.3pW

Gain

40dB

37dB

40dB

40dB

40dB

47.5dB

28-40dB

HP Pole

15mHz

5Hz

14mHz

45Hz

0.05Hz

11.5Hz

0.112Hz

THD (input)

1% (17.4mVpp)

1% (400pVpp)

1% (16.7mVpp)

1% (7.3mVpp)

1% (lmVpp)

1% (3.1mVpp)

0.02% (20mVpp)

Input noise Band

3.6pVrms 20Hz-10kHz

5.5pV rms 5Hz-7kHz

2.2pVrms 0.5Hz-50kHz

3.06pVrms 45Hz-5.3kHz

2.2pV;·ms 0.05Hz-10.5kHz

3.8pV;·ms 1Hz-100kHz

1.93pV;'ms 0.5-500Hz

Area

0.2mm2

-

0.16mm2

0.16mm2

0.072mm2

0.08mm2

0.lmm2

* Only this work presents simulation results, all the others references present measured results. offset of 6.5mV. The simulated input-referred noise curve, in V2 /H z, is presented in Fig.12. It is dominated by flicker noise from DC to about 500Hz. Integrating the PSD from 0.5Hz to 500Hz (EMG band) results in 1.93 pV RMS, slightly larger than the estimated theoretical value of 1.61 pV RMS. In the wider 0.5Hz to 30KHz range (for all the relevant am­ plifier band) the total integrated noise power is 5.53 pV RMS. Table 1 shows a comparison between the estimated perfor­ mance of this circuit and other similar devices that have been reported in recent years. One can observe that the design technique we used in this work surpasses all of the others in the comparison in terms of output signal excur­ sion and linearity, with an effective use of the rail voltage. In terms of area, power consumption and noise, our design shows results that are equivalent to the others reported in Table 1. 5. CONCLUSION We presented a highly linear fully integrated sub-Hz high­ pass pre-amplifier for biomedical applications. By employing a resistive attenuator to limit the voltage swing on a PMOS pseudo-resistor, a large output swing can be achieved main­ taining high linearity. Simulations for an output swing of 2 Vpp show a THD of 74 dB (0.02%) under worst-case pro­ cess conditions. Even more linearity could be achieved by choosing a higher attenuation factor. The power consump­ tion of our design is very low 31.3 pW under a 1.5 V supply. Simulated total input-referred noise was 1.93 pV RMS in­ side the 0.5Hz to 500Hz frequency range. Configurable gain and high-pass cut-off frequency lower than 120 mHz enable the use of this pre-amplifier on different biomedical signals measured in differential mode, such as EMG and ECG. Fu­ ture works include the silicon bring up and testing of the IC prototype, as well as more accurate analysis of the pseudo­ resistors implementation. Acknowledgment

The authors would like to thank CAPES and CNPq for fi­ nancial support, MOSIS service for silicon prototyping, CI­ Brasil Program for simulation tools and to Oscar Mattia for helpful discussions and revisions.

6.

REFERENCES

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