On Efficient Design of LDPC Decoders for Wireless ... - Semantic Scholar

JOURNAL OF NETWORKS, VOL. 9, NO. 12, DECEMBER 2014

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On Efficient Design of LDPC Decoders for Wireless Sensor Networks Duc Minh Pham and Syed Mahfuzul Aziz School of Engineering, University of South Australia, Mawson Lakes, SA 5095, Australia Email: {duc.pham, mahfuz.aziz}@unisa.edu.au

Abstract—Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation in digital communication systems. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However,traditional hardware implementation of LDPC decoders require large amount of resources, rendering them unsuitable for use in energy constrained sensor nodes of wireless sensor networks (WSN). This paper investigates the use of short-length LDPC codes for error correction in WSN. It presents the LDPC decoder designs, implementation, resource requirement and power consumption to judge their suitability for use in the sensor nodes of WSN. Due to the complex interconnections among the variable and check nodes of LDPC decoders, it is very time consuming to use traditional hardware description language (HDL) based approach to design these decoders. This paper presents an efficient automated high-level approach to designing LDPC decoders using a collection of high-level modelingtools. The automated high-level design methodology provides a complete design flow to quickly and automatically generate, test and investigate the optimum (length) LDPC codes for wireless sensor networks to satisfy the energy constraints while providing acceptable bit-error-rate performance. Index Terms—Error Correction Coding; Wireless Communication; Wireless Sensor Networks; Digital System; FPGA

I.

INTRODUCTION

Low Density Parity-Check (LDPC) codes [1, 2] are known as the most powerful forward error correction codes with a bit-error-rate (BER) performance closed to the Shannon limit. LDPC codes have been proved to have better performance and several advantages over other error correction codes such as Turbo codes, Hamming codes, Reed-Muller and Reed-Solomon codes [2]. Because of excellent BER, LDPC-codes are extensively used in standards such as WiMAX, 10Gigabit Ethernet (10GBaseT), digital video broadcasting (DVB-S2) and expected to be part of many future standards [3, 4]. Although the decoding algorithm of LDPC is simple, hardware implementation faces several significant challenges. One of the challenges in implementation of fully parallel LDPC decoder is the complexity of the interconnections between the nodes inside the decoder [5]. Especially when the LDPC matrix becomes large, it is almost impossible and time consuming to manually © 2014 ACADEMY PUBLISHER doi:10.4304/jnw.9.12.3207-3214

connect and check the connections.In this paper, an automated high-level design methodology is introduced. We propose a design methodology that supports programmable logic design starting from high-level modeling all the way up to FPGA implementation using a collection of high-level modeling tools. The methodology has been used to design and implement LDPC decoders of various code lengths on FPGAs. The simulation and FPGA implementation results obtained are then used to determine suitable LDPC decoders for Wireless Sensor Networks (WSN), which consist of severely resource constrained sensor nodes. In recent years, WSNs have attracted significant research interests [6-8]. A WSN can be defined as a network of a large number of spatially distributed, small, low cost and low power nodes, which can sense the environment and wirelessly communicate the information gathered to other nodes. The collected information is forwarded, normally via multiple hops, to a sink (or controller or monitor) node that uses the information locally or transmits it to other networks (e.g., Internet) through a gateway. WSNs are normally comprised of scalar sensors capable of measuring physical phenomenon such as temperature, pressure, light intensity, humidity etc. [9]. The abovementioned applications do not have a high bandwidth requirement and are delay tolerant. Recently, several research works have been reported to add small sized and low-power CMOS cameras and microphones to the sensor nodes. Such Wireless Multimedia Sensor Network (WMSN), with the ability to gather multimedia information from the surrounding environment, is providing the impetus for extending the capabilities WSNs for many new applications such as advanced environmental monitoring, advanced health care delivery, traffic avoidance, fire prevention and monitoring, object tracking etc. However, in WMSN, with the large volume of multimedia data generated by the sensor nodes, both processing and transmission of data leads to higher levels of energy consumption. Energy consumption in transmitting large volume of multimedia data can be reduced by using energy-efficient and reliable transmission protocols [10] or reducing the amount of multimedia data [11]. Beside these approaches, efficient error correction decoders can be used to reduce the energy required for communication of the multimedia information. However, the amount of energy spent to transmit the redundant information

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required for error correction and the energy used to perform error correction should be less than the energy saved at the transmitter side for retransmission of erroneous information [12]. Several codes have been investigated for error correction in WSN, including Reed–Solomon codes, convolution codes, turbo codes and LDPC codes [13, 14]. Some preliminary results in [12, 15] suggest that LDPC codes are good candidates for WSN applications as they feature a significant coding gain compared with other codes. LDPC codes are known to achieve nearly the Shannon limit with long code length. However, parallel decoders for long LDPC codes require large hardware and energy consumption and therefore partially parallel decoders were introduced [16]. In WSN, the data exchanged between sensor nodes is usually small [10]. This raises the prospect of using short LDPC codes for error correction in WSN for without compromising the bit-error-rate (BER) performance significantly. Most of the previous works proposing error correction codes for WSNs assume that networks contain only two types of nodes: sensing nodes and base stations. Sensing nodes feature lower computational capabilities and lower available energy than base stations. Thus, sensing nodes send coded information to a central node which performs the decoding operations. In this paper, we investigate the possibility of implementing short length LDPC codes in WSNs where sensor nodes can both encode/transmit and receive/decode information. We show that that LDPC codes with small block length are adequate for typical throughput and data transmission requirements of WSNs. II.

LDPC CODES AND DECODING ALGORITHM

LDPC codes can be represented by an M x N sparse matrix, usually called H matrix. The H matrix contains mostly zeros and a small number of 1s [1, 2]. It can also be represented by a graph called bipartite or Tanner graph as shown in Fig. 1.

Figure 1. Tanner graph and LDPC matrix of a 5x10 (3,6) code

There are different algorithms which could be used for decoding purposes. We used the min-sum decoding algorithm [17], which is a special case of the sum-product algorithm [18]. Sum-product algorithm reduces the computational complexity and makes the decoder numerically stable [18]. The LDPC decoder consists of a number of variable nodes (v) and check nodes (c). In min© 2014 ACADEMY PUBLISHER

sum decoding algorithm, a variable node performs the operation given in equation (1) and passes the outputs to the check nodes.

Lcv 

R

mM ( v ) \ c

mv

 Iv

(1)

where, Iv is the input to variable node v, also known as Log Likelihood ratio (LLR), Lcv is the output of variable node v going to check node c, M(v)\c denotes the set of check nodes connected to variable node v excluding the check node c, Rmv is the output of check nodes going to variable node v. A check node receives messages from the variable nodes and performs the operation given by (2):

Rcv 

 sign( L

cv

)nN ( cmin ) \ v | Lcv |

(2)

nN ( c ) \ v

where, Rcv is the output of check node c going to variable node v. Every check node also checks whether the parity condition is satisfied by looking at the sign of the messages coming from the variable nodes. Until the parity conditions are satisfied at all the check nodes the messages are sent back to variable nodes otherwise the decoder stops the process. Min-sum decoding algorithm uses soft decisions. However, hard decision is taken on the new LLR (Iv). If the new LLR is negative then the output bit would be a 1 otherwise a 0. III.

AUTOMATED HIGH-LEVEL DESIGN METHODOLOGY

The proposed automated high-level design methodology provides a complete design flow to automatically generate and test complex LDPC decoders. As shown in Fig. 2, the methodology has two main parts, namely, automatic generation of decoder models and automatic testing of decoders (presented in Part B of this section). A. Automatic Generation of LDPC Models and HDL Codes The automatic LDPC model generation flow shown in Fig. 2 requires two inputs: LDPC library and LDPC matrix. The LDPC library contains two basic hand designed modules, check node (C-node) and variable node (V-node). The LDPC matrix can be preconfigured to any size for (3, 6)-regular LDPC code. 1) Design of Check Node and Variable Node The C-node has been designed in Simulink using builtin Simulink library blocks. It performs the operation given in (2). The main function of the C-node is to find the minimum of all the inputs to the C-node and to perform parity checks. Several approaches to design the C-node have been evaluated for hardware requirement and speed to choose the most optimized design for the automated design flow. For LDPC (3, 6) code, every Cnode has six inputs. First, the C-node was designed using (2), by comparing every set of five inputs separately, to find the minimum. In this approach the hardware

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requirement for the C-node is high due to the same comparisons being made multiple times [19]. An optimized find-minimum-function is presented in Fig. 3. In this design, a module called find3min is used to find the minimum of 3 sets of 4 inputs. For example, Min1234 is the minimum of input set {1, 2, 3, 4}. Each output of the find3min block is then compared with one more input to find the minimum of five inputs. As the outputs of every fin3min block are reused, this approach reduces the amount of hardware resources required to implement the find-minimum-function. Simulink model of the C-node is shown in Fig. 4. Comparison between the original C-node design in [19] and this optimized C-node design is given in Table I.

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TABLE I.

C-NODE DESIGN COMPARISON

Xilinx XC3S1200E Synthesis Results Slices Used 4-input LUTs Used Maximum delay Original C-node 105 186 12.87ns Optimized C-node 56 98 12.38ns Design

The V-node has also been designed in Simulink using the basic add block from the Simulink library. The Vnode has four inputs, the first three come from various check nodes and the fourth one is the raw LLR, which is an external input supplied by the host communication system. It performs the operation given in (1) and passes the outputs to the C-nodes it is connected to. Simulink model of V-node is shown in Fig. 5.

Figure 5. Simulink model of the variable node Figure 2. Automated LDPC design flow

Figure 3. Optimized find-mimimum-function for C-node

Figure 4. Simulink model of the check node © 2014 ACADEMY PUBLISHER

2) Auto-generation of Decoder Models The auto-generation of decoder models is accomplished using Matlab scripts. The Matlab scripts read the LDPC matrix and automatically instantiate the V-nodes and C-nodes to build the corresponding decoder model in Simulink. They also connect the V-nodes and C-nodes according to the LDPC matrix. The routing process is very simple but effective. Each input and output of the V-nodes and C-nodes are marked with a Simulink routing label. The routing labels are specified by the Matlab scripts to build the connections between nodes as required by the LDPC matrix. If a routing label of a V-node input has the same name as that of the routing label of a C-node output then Simulink will understand these two ports to be connected to each other. Fig. 6a shows the layout of the Simulink model of a (200,100) LDPC decoder after it is automatically generated. Fig. 6b shows a zoomed view of the interconnections inside the model. Once a Simulink decoder model is generated by the Matlab script, it can be used to automatically generate a HDL model using the Simulink HDL Coder tool. Either VHDL or Verilog can be chosen as the target HDL. The generated HDL code is vendor independent, and can be synthesized and implemented on most FPGAs.

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the PC sends these LLRs to the decoder via the USB module and receives the decoded LLRs back along with the parity information. The decoded LLRs are written into a separate file by the LabVIEW program and analyzed for correctness by a MATLAB program by comparing with the LLRs generated by simulation of the Simulink and/or VHDL models.

(a)

(b)

Figure 6. (a) Generated Simulink model of a LDPC decoder. (b) magnified view of the model in (a).

B. Automatic Testing Strategy The proposed automatic model generation process is complemented with a comprehensive automatic testing strategy. It comprises an automatic process of generating and encoding test data, inserting noise, quantization and application of the final test data to the decoder under test. The Matlab and Simulink environments used in this highlevel design methodology provide an efficient and fast mechanism to build a full test system for the entire design. The proposed testing strategy is comprehensive as it allows for testing the decoder at all possible levels of the hierarchy: Simulink model, HDL model and FPGA implementation. Fig. 7 shows the proposed testing strategy. The Matlab Test Data Generator module generates a sequence of LDPC encoded test data. These test data are written to text files, which are then supplied as inputs while executing the Simulink model, the HDL model as well as to run the decoder implemented on FPGA. After decoding is done in the three environments, the results are written to separate text files. The Matlab LDPC Test Data Analyzer module will compare the results and produce the report on the consistency or otherwise of the results. The Analyzer will also produce performance plot of the decoder, e.g. bit-error-rate (BER) as a function of Eb/N0. This scheme has been used to test and validate the decoder designs presented in this paper. IV.

Figure 7. Comprehensive automatic test and simulation flow

FPGA IMPLEMENTATION AND TESTING

We have successfully implemented and tested the decoders generated by our automation methodology on Xilinx FPGA boards. Fig. 8 illustrates the arrangement used for testing the designs. The hardware platform contains three modules: the USB communication module for communicating with the PC, the main FPGA module and the I/O module. As described in the automatic testing strategy, the LLRs generated by the MATLAB program are stored in text files. A LabVIEW program running on

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Figure 8. Hardware setup for testing LDPC decoders

V.

RESULTSAND ANALYSIS

A. Synthesis Results All the decoders generated by the proposed automation methodology are synthesizable for implementation on a

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range of FPGAs. Table II shows the FPGA resources required for fully parallel architectures of various decoder sizes. Because of the resource constraints of the Spartan 3E FPGA we used, an LDPC decoder with a maximum block length of 200 with 2-bit quantization (LLRs) was implemented and successfully tested. The proposed automated methodology can be used to implement decoders with larger block lengths and higher quantization levels as long as the target FPGA has the required amount of resources. The proposed automated model generation and testing regimes are fully parameterized for block length and quantization, making it a very flexible and efficient design and implementation method for investigating alternative design choices. TABLE II. Design

Xilinx FPGA

SYNTHESIS RESULTS

Synthesis Results SlicesUsed LUTs Used FFs Used Fmax

(50,25) XC3S1200E 3478 4-bit LLRs (100,50) XC3S1200E 6445 4-bit LLRs (200,100) XC3S1200E 4122 2-bit LLRs (200,100) XC5VLX110T 2450 4 bit LLRs (400,200) XC5VLX110T 4925 4-bit LLRs

6423

800

61.34 MHz

12591

1600

59.91 MHz

9856

800

83.2 MHz

17018

3200

153.45 MHz

34445

6400

152.34 MHz

comparison with LDPC designs reported in literature [16, 20-24]. The throughput (T) of the decoder is calculated as follows:

𝑇=

𝑟𝑎𝑡𝑒 ×𝑏𝑙𝑜𝑐𝑘𝑙𝑒𝑛𝑔𝑡 𝑕×𝑓𝑚𝑎𝑥

(3)

𝑁𝑖𝑡 ∗𝛾

We calculate the throughput (at 3.5dB Eb/N0) of the (200,100) decoder that was implemented on a Spartan 3E FPGA device (XC3S1200E). As per Table II, the blocklength is 200, code rate is 1/2and γ =1, where γ is the number of clock cycles needed to complete one iteration. Fig. 9 shows that at 3.5dB the average number of iterations (Nit) is approximately 3.7. From Table II, the maximum clock frequency for the selected FPGA device is 83.2MHz. Using these values in (3), the throughput of the implemented LDPC decoder at 3.5dB is 2.25Gbps. For decoders with higher block lengths implemented on high end FPGAs, much higher throughputs (exceeding 10Gbps) is possible.Fig.10 shows the BER performance obtained from the FPGA test and simulation results of a few LDPC decoders designed using the proposed methodology. As expected, it shows that the BER improves when the code length is increased. However, it is important to ensure that the resource requirement does not increase significantly leading to higher power consumption. BER vs Eb/No plot LDPC(100,50) 4bit - FPGA test LDPC(200,100) 2bit -FPGA test LDPC(400,200) 4bit - Simulink test

-1

10

-2

10 BER

B. Iteration Convergence Test The convergence characteristics of LDPC decoders implemented on FPGAs have been plotted. The number of iterations taken by each set of LLR is monitored by a counter on the FPGA and the final iteration count is sent to the PC. A Matlab script reads all iteration counts at each Eb/N0 and calculates the average iteration count. Fig. 9 shows the spread of the average number of iterations for a (200,100) LDPC decoder versus Eb/N0 with maximum iteration set to 10.

-3

10

Iter vs Eb/No plot 10 -4

Number of Iterations

LDPC (200,100) 2-bit LLRs - FPGA test

10

9

1.5

8

2.5 Eb/No

3

3.5

4

Figure 10. Performance comparison of various LDPC decoders

7 6 5 4 3 2

2

0

0.5

1

1.5

2

2.5

3

3.5

4

Eb/No Figure 9. Spread of iterations for a (200,100) LDPC design

C. Throughput and Algorithm Performance Test Because of the fully parallel architecture, the decoders presented in this paper have very good throughput in

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D. Analysis of theAutomatic High-Level Design Methodology As the LDPC design gets larger and larger, it becomes very difficult to manually code and connect all the variable and check nodes usinga hardware description language (HDL). The high-level automated design methodology presented in this paper reduces design complexity, effort and time drastically. In comparison with the work introduced in [19], this automation methodology has helped reduce the design time and effort dramatically. Importantly, italso greatly enhances the ability tomanage and reuse complex design blocks. Design reuse requires much less effort because changes are easily made at block level in Simulink. In addition, Matlab is a high-level programming language that is used

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much more widely than hardware description languages such as VHDL and Verilog. Therefore, designers without specific skills in HDLs are able to design complex digital systems without much problem. Even software engineers and algorithm developers are able to quickly implement and test their high-level designs due to the ability to automatically generate HDL descriptions from the Simulink models. This will surely offer great flexibility and efficiency in the design and reuse of complex LPDC decoders. VI.

IMPLICATIONS OF THE RESULTS FOR WSN

Recent applications of wireless sensor networks have highlighted the importance of energy efficiency in hardware processing in the sensor nodes [25]-[26]. The proposed automation methodology has been used to quickly design, test and analyze the characteristics of LDPC decoders of various code lengths targeting Xilinx FPGAs. The complete design flow, including synthesis, place and route has been performed using Xilinx ISE 14. Xilinx Power Analyzer has been used to estimate the power consumption. The dynamic power consumption results for all the tested decoders have been obtainedat 50 MHz and are shown in Table III. Typical leakage power for Spartan 3E FPGA (XC3S1200E) is 159mW and that for a Virtex 5 device (XC5VL50T) is 591mW. As per Table III, the largest LDPC code that fits into the low-power Spatan3E FPGA (XC3S1200E) is of length (200,100) with a 2-bit LLR. Its power consumption is lower than that of a decoder of length (100, 50) with a 4-bit LLR. The performance plot in Fig.10 shows that the (200,100) decoder with a 2-bit LLR can achieve higher BER performance than the (100, 50) decoder with a 4-bit LLR. Therefore, for emerging WSN applications [10]-[11], a (200,100) decoder with 2-bit LLR is the most suitable choice among the decoders shown in Table III. Recent techniques on reduced complexity LDPC algorithms [27]-[28] are likely to further improve the energy efficiency by reducing resource requirement and consequently the power consumption for LDPC decoding.

Fig. 10 shows that the BER of the (200,100) decoder with a 2-bit LLR is 10-3 at Eb/No=3.6dB. The Eb/No required to achieve this BER in an uncoded data stream (OQPSK) is over 7 dB, as shown in Fig. 11. This means that with LDPC coding the dB value of the transmit signal power can be reduced by half to achieve the same BER as that for an uncoded stream. This will lead to significant savings in transmission energy. The proposed (200,100) 2-bit LDPC decoder implemented on FPGA has a dynamic power consumption of only 57mW. This is comparable with the power consumption of a larger LDPC decoder of length (1008,504) synthesized on an ASIC [29], the power consumption of the latter being 33.14mW. The difference is that the results presented in this paper are from a practical FPGA implementation, and therefore the real hardware functions and performance have been tested and validated. However, in [29], the reported power consumption is from a synthesized design only. Moreover, ASIC implementations are costly, time consuming and not reprogrammable. Recently, several LDPC decoders have been proposed for wireless sensor networks [15, 29, 30]. However, all of them report results from synthesis of the designs using ASIC design approach, not practical test results from actual ASIC implementation. Therefore, none of them has been validated on hardware. TABLE III.

POWER CONSUMPTION RESULTS @25OC, 50MHZ

Design

Xilinx FPGA

(50,25) 4-bit LLRs (100,50) 4-bit LLRs (200,100) 2-bit LLRs (200,100) 4 bit LLRs

XC3S1200E XC3S1200E XC3S1200E XC5VL50T

Dynamic consumption (mW) 38 77 57 159

power

VII. CONCLUSIONS This paper has presented the designs and practical implementation results of short-length LDPC decoders for wireless sensor networks using a flexible automated methodology. FPGA test results have proved that the design methodology is efficient and error-free. The proposed methodology offers great advantages in terms of reduced design complexity, effort and time. It allows designers to quickly determine the trade-offs between shorter LDPC codes and shorter LLRs versus BER performance. The practical test results presented in the paper have demonstrated that short-length LDPC codes with small LLRs can be used for error correction at low power consumption while providing acceptable bit-errorrate performance. The results of this study are therefore useful to determine optimum LDPC codes for low power applications such as wireless sensor networks. REFERENCES

Figure 11. Uncoded WSN data stream with OQPSK

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[1] R. Gallager, "Low-density parity-check codes," IRE Transactions on Information Theory, vol. 8, pp. 21-28, 1962. [2] S. J. Johnson, "Introducing low-density parity-check codes," University of Newcastle, Australia, 2006.

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[3] M. Eroz, F. W. Sun, and L. N. Lee, "DVB-S2 low density parity check codes with near Shannon limit performance," International Journal of Satellite Communications and Networking, vol. 22, pp. 269-279, 2004. [4] T. Mohsenin and B. M. Baas, "Split-Row: A reduced complexity, high throughput LDPC decoder architecture," in International Conference on Computer Design, ICCD, San Jose, 2007, pp. 320-325. [5] A. Darabiha, A. C. Carusone, and F. R. Kschischang, "A bit-serial approximate min-sum LDPC decoder and FPGA implementation," in IEEE International Symposium onCircuits and Systems, ISCAS, Island of Kos, 2006. [6] D. Culler, D. Estrin, and M. Srivastava, "Overview of wireless sensor networks," IEEE Computer, Special Issue in Sensor Networks, vol. 37, pp. 41–49, 2004. [7] C. Buratti, A. Conti, D. Dardari, and R. Verdone, "An Overview on Wireless Sensor Networks Technology and Evolution," Sensors, vol. 9, p. 6869, 2009. [8] M. Tubaishat and S. Madria, "Sensor networks: an overview," IEEE potentials, vol. 22, pp. 20-23, 2003. [9] I. Akyildiz, T. Melodia, and K. Chowdhury, "A survey on wireless multimedia sensor networks," Computer Networks, vol. 51, pp. 921-960, 2007. [10] S. M. Aziz and D. M. Pham, "Energy Efficient Image Transmission in Wireless Multimedia Sensor Networks," IEEE Communications Letters, vol. 17, pp. 1084 -1087, June 2013. [11] D. M. Pham and S. M. Aziz, "Object extraction scheme and protocol for energy efficient image communication over Wireless Sensor Networks," Computer Networks, Elsevier, Online, July 2013. [12] E. Sanchez, F. Gandino, B. Montrucchio, and M. Rebaudengo, "Increasing effective radiated power in wireless sensor networks with channel coding techniques," in International Conference on Electromagnetics in Advanced Applications, ICEAA, 2007, pp. 403-406. [13] M. C. Vuran and I. F. Akyildiz, "Error control in wireless sensor networks: a cross layer analysis," IEEE/ACM Transactions on Networking, vol. 17, pp. 1186-1199, 2009. [14] M. Sartipi and F. Fekri, "Source and channel coding in wireless sensor networks using LDPC codes," in First Annual IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks, IEEE SECON, 2004, pp. 309-316. [15] A. D. G. Biroli, M. Martina, and G. Masera, "An LDPC Decoder Architecture for Wireless Sensor Network Applications," Sensors, vol. 12, pp. 1529-1543, 2012. [16] V. A. Chandrasetty and S. M. Aziz, "A highly flexible LDPC decoder using hierarchical quasi-cyclic matrix with layered permutation," Journal of Networks, vol. 7, pp. 441449, 2012. [17] J. Sha, et al., "An FPGA implementation of array LDPC decoder," in IEEE Asia Pacific Conference on Circuits and Systems, APCCAS, 2006, pp. 1675-1678. [18] S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications: Pearson-Prentice Hall, 2004. [19] S. M. Aziz and M. D. Pham, "Implementation of low density parity check decoders using a new high level design methodology," Journal of Computers, vol. 5, pp. 81-90, 2010. [20] T. Zhang and K. K. Parhi, "A 54 mbps (3, 6)-regular FPGA LDPC decoder," in IEEE Workshop on Signal Processing Systems, SIPS, 2002, pp. 127-132. [21] A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,"

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IEEE Journal of Solid-State Circuits, vol. 37, pp. 404-412, 2002. A. Darabiha, A. C. Carusone, and F. R. Kschischang, "Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity," in IEEE International Symposium on Circuits and Systems, ISCAS, 2005, pp. 5194-5197. V. A. Chandrasetty and S. M. Aziz, "An area efficient LDPC decoder using a reduced complexity min-sum algorithm," Integration, the VLSI Journal, vol. 45, pp. 141148, 2012. V. A. Chandrasetty and S. M. Aziz, "FPGA implementation of a LDPC decoder using a reduced complexity message passing algorithm," Journal of Networks, vol. 6, pp. 36-45, 2011. D. M. Pham and S. M. Aziz, "FPGA-based image processor architecture for wireless multimedia sensor network," in IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC, Melbourne, , 2011, pp. 100-105. D. M. Pham and S. M. Aziz, "An energy efficient image compression scheme for Wireless Sensor Networks," in IEEE Eighth International Conference on Intelligent Sensors, Sensor Networks and Information Processing, ISSNIP, Sydney, 2013, pp. 260-264. V. A. Chandrasetty and S. M. Aziz, "FPGA implementation of high performance LDPC decoder using modified 2-bit min-sum algorithm," in Second International Conference on Computer Research and Development, 2010, pp. 881-885. V. A. Chandrasetty and S. M. Aziz, "A reduced complexity message passing algorithm with improved performance for LDPC decoding," in 12th International Conference on Computers and Information Technology, ICCIT, Dhaka, 2009, pp. 19-24. M. Ismail, I. Ahmed, and J. Coon, "Low Power Decoding of LDPC Codes," ISRN Sensor Networks, vol. 2013, p. 12, 2013. J. S. Rahhal, "LDPC coding for MIMO wireless sensor networks with clustering," in The Second International Conference on Digital Information and Communication Technology and it's Applications , DICTAP, 2012, pp. 5861.

Duc Minh Pham received B.S. degree in electronic engineering from HCM National University of Technology, Vietnam in 2003 and M.S. degree in micro systems technology from the University of South Australia in 2008. Mr Pham is currently working as a Research Associate and doing his PhD at University of South Australia in the field of wireless multimedia sensor networks. He has strong industry experiences in system design for both FPGA and ASIC platforms. His research interests are in the fields of VLSI implementation of communication systems such as SoC for next generation networking, automation in VLSI design, FEC (Forward Error Correction), APS (Application Specific Processor), wireless sensor networks, coding theory, image and video processing. Syed Mahfuzul Aziz received Bachelor and Master degrees in electrical and electronic engineering (EEE) from Bangladesh University of Engineering & Technology (BUET) in 1984 and

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1986 respectively. He received a Ph.D. degree in electronic engineering from the University of Kent (UK) in 1993 and a Graduate Certificate in higher education from Queensland University of Technology in 2002. He was a Professor in BUET till 1999. Prof Aziz initiated and led the development of teaching and research programs in integrated circuit (IC) design in Bangladesh. In 1996, he was a visiting scholar at the University of Texas at Austin when he spent time at Crystal Semiconductor Corporation designing advanced CMOS integrated circuits. He joined the University of South Australia in 1999, where he is

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currently the discipline leader of EEE. He has been involved in many industry projects and has attracted funding from industry as well as reputed bodies such as the Australian Research Council (ARC), Australian Defence Science and Technology Organization (DSTO), and Cooperative Research Centre. He has authored over 120 research papers. His research interests include digital systems and IC design, wireless sensor networks, biomedical instrumentation and engineering education. Prof Aziz is a senior member of the IEEE and a member of Engineers Australia. He has received numerous professional and teaching awards including the Prime Minister’s Award for Australian University Teacher of the Year (2009). He reviews papers for a number of reputed journals including IEEE Transactions and journals published by the IET and Elsevier.