On Passivity of the Super Node Algorithm for EM

On Passivity of the Super Node Algorithm for EM Modeling of Interconnect Systems Maria V. Ugryumova

Wil H.A. Schilders

Department of Mathematics and Computer Science Eindhoven University of Technology, The Netherlands Email: [email protected]

Eindhoven University of Technology and NXP Semiconductors Eindhoven, The Netherlands Email: [email protected]

Abstract—The super node algorithm performs model order reduction based on physical principles. Although the algorithm provides us with compact models, its passivity has not thoroughly been studied yet. The loss of passivity is a serious problem because simulations of the reduced network may encounter artificial behavior which render the simulations useless. In this paper we find the reason of delivering non-passive models and propose a modified version of the algorithm which guarantees passivity. This is done by applying a passivity enforcement procedure after frequency fitting step within the algorithm. This allows to preserve passivity while keeping the main advantages of the algorithm. Finally numerical examples validate the proposed approach. Index Terms—electromagnetic modeling, interconnect system, model order reduction, passivity.

I. I NTRODUCTION Computer techniques have revolutionized the way in which electromagnetic problems are analyzed. In this paper we concentrate on Fasterix [1],[2],[3],[4], an EM tool for analyzing electromagnetic (EM) behavior of interconnect systems. Fasterix is used at Philips and NXP Semiconductors and has proved very successful for interconnect systems as printed circuit boards (PCB), the main application for which it was developed. As a first step in Fasterix a geometry preprocessor subdivides a given conductor of arbitrary geometry into quadrilateral elements and derives directly a lumped model. In this paper we refer to it as original circuit. Such circuit when observed from its ports, is equivalent to the interconnect system. The values of the mutual inductances, capacitors and resistors of this circuit are extracted using a quasi-static BEM and may be of the order of many tens of millions. Thus the direct use of this circuit is inefficient, because computer memory and CPU limitations imply that the interconnect system cannot realistically be simulated. As a model reduction step, Fasterix employs a compressed equivalent circuit (reduced circuit) which has a much smaller number of nodes and reducing the circuit analysis computations by many orders of magnitude. Nodes, at which the reduced circuit is built, are called super nodes. The super node algorithm (SNA) is a procedure in Fasterix to obtain a reduced circuit from the the original one. The advantage of the SNA is that it is inspired by physical insight into the models, and produces reduced circuits depending on the maximum predefined frequency. In Fasterix original and reduced circuits are generated once, i.e. do not

978-3-9810801-6-2/DATE10 © 2010 EDAA

have to be repeated for each time or frequency. Due to it Fasterix has proved to be orders of magnitude more efficient than a typical tool based on FEM (finite element method) [5] and BEM (boundary element method) [6]. Although the algorithm provides us with compact models, some of them suffer from instabilities which can be observed during time domain simulations [4], [7]. To overcome this problem, the model order reduction (MOR) technique PRIMA [8] which preserves passivity was successfully applied to some Fasterix models [9]. This approach appears to be useful if one is interested in input-output behavior of reduced models. However often it is needed to calculate radiation in Fasterix. For this goal realized reduced circuits have to be built on a subset of nodes (super nodes), which is inefficient to achieve by PRIMA. Later, in [10], a modified version of the SNA which guarantees passivity was suggested. It is based on modal approximation of admittance matrix [11],[12]. Unfortunately this approach is not efficient for reduction of large models: the synthesized reduced models are dramatically expensive for simulations. In this paper we analyze the algorithm and explain why it delivers non-passive circuits. Furthermore we propose a modified version of the algorithm which guarantees passivity. This is achieved by applying passivity enforcement technique [13] to the admittance matrix at the step where passivity might be lost. Synthesized reduced circuits have the same size as after applying the SNA and are suitable for further calculation of radiation in Fasterix. The proposed approach is validated by some numerical examples. II. C IRCUIT FORMULATION U SED IN FASTERIX Fasterix translates electromagnetic properties of the interconnect system up to a certain maximum frequency into a circuit which is described by the system of Kirchhoff’s equations (1) − (2). In [2] Kirchhoff’s equations are obtained from the electric field integral equations which are derived from Maxwell equations. (Similar derivation of Kirchhoff’s equations can be found in [14], chapter 8). Discretisation of the domain of the conductor into quadrilateral elements and specific choice of basic functions results in a system which has the appearance of Kirchhoff’s equations. The variables of the system represent potentials at the 𝜂 nodes and current in

the 𝜖 branches: (R + 𝑠L)𝐼 − P𝑉 = 0

(1)

𝑇

P 𝐼 + 𝑠C𝑉 = 𝐽,

(2)

where R ∈ ℝ𝜀×𝜀 is the resistance matrix, L ∈ ℝ𝜀×𝜀 is the 𝜖×𝜂 inductance matrix, P ∈ {1, 0, −1} is an incidence matrix, 𝜂×𝜂 C ∈ ℝ is the capacitance matrix, 𝐼 ∈ 𝐶 𝜖 is a vector of currents flowing in the branches, 𝑉 ∈ 𝐶 𝜂 is a vector of voltages at the nodes. Vector 𝐽 ∈ 𝐶 𝜂 collects the terminal currents flowing into the interconnect system. Value 𝑠 is a complex number with negative imaginary part: 𝑠 = −𝑗𝜔. The matrix elements of R, L, C and P are integrals and calculated by Fasterix. Matrices R, L are symmetric positive definite and C is symmetric positive semidefinite. It should be noted that (1)-(2) describe the interconnect system up to a certain frequency but do not correspond to modified nodal analysis (MNA) equations since R is not diagonal. In order to obtain the admittance matrix which describes the input-output behavior of the original circuit, we suppose that current 𝐽 flows only(through the )ports of the system (i.e. upon permutation 𝐽 𝑇 = 𝐽𝑝𝑇 𝐽𝑖𝑇 and 𝐽𝑖𝑇 = 0). Here index 𝑝 stands for external nodes (ports) and 𝑖 stands for internal nodes. Splitting similarly 𝑉 , P and C into correspondent blocks, we rewrite (1)-(2) as follows ⎞ ⎞⎛ ⎞ ⎛ ⎛ R + 𝑠L −P𝑖 −P𝑝 0 𝐼 ⎝ P𝑇𝑖 𝑠C𝑖𝑖 𝑠C𝑖𝑝 ⎠ ⎝ 𝑉𝑖 ⎠ = ⎝ 0 ⎠ . (3) 𝑇 𝐽𝑝 𝑉𝑝 P𝑝 𝑠C𝑝𝑖 𝑠C𝑝𝑝 Eliminating 𝐼 and 𝑉𝑖 from (3), one obtains admittance matrix Y(𝑠) of the original non-reduced circuit: ( ) ˜ + 𝑠C) ˜ −1 B𝑖 (𝑠) + 𝑠C𝑝𝑝 𝑉𝑝 , 𝐽𝑝 = B𝑇𝑜 (𝑠)(G (4) | {z } Y(𝑠)

where

˜ 𝑇𝑜 (𝑠) = B ˜= C

(

(

P𝑇𝑝

L 0 0 C𝑖𝑖

𝑠C𝑇𝑖𝑝 )

)

˜ = , G

˜ 𝑇𝑖 (𝑠) = ,B

(

(

R P𝑇𝑖

P𝑇𝑝

−P𝑖 0

)

−𝑠C𝑇𝑖𝑝

)

,

(5)

.

(6)

We will consider Y(𝑠) as the admittance of the original circuit which can be further used for comparison with reduced order models. III. S UPER N ODE A LGORITHM A. Admittance matrix of the super nodes circuit As it was discussed above, the original circuit described by (1)-(2) contains 𝜂 nodes (ports and internal nodes) and 𝜖 branches. In Fasterix the reduced circuit is built on the socalled super nodes, i.e. ports and a subset of internal nodes. Fasterix defines the super nodes in such a way that there exists a conducting path, no greater in length than a predefined small fraction of the minimum wavelength, between every point on the conductors and at least one of the super nodes. Such choice of super nodes provides that the reduced circuit can be further

synthesized with frequency independent elements. Since our main concern is the study of passivity we do not discuss procedures of selection of super nodes and calculation of R, L, C, P matrices. For more details, the reader is refer to [1], [15]. We will use the following notation: 𝑁 contains indices of nodes which are super nodes and 𝑁 ′ contains indices of all other nodes. Thus vectors 𝑉 , 𝐽 and matrices P, C in (1)-(2) can be partitioned into blocks, so (1)-(2) becomes ⎛ ⎞⎛ ⎞ ⎞ ⎛ R + 𝑠L −P𝑁 ′ −P𝑁 0 𝐼 ⎝ P𝑇𝑁 ′ 𝑠C𝑁 ′ 𝑁 ′ 𝑠C𝑁 ′ 𝑁 ⎠ ⎝ 𝑉𝑁 ′ ⎠ = ⎝ 0 ⎠ . 𝐽𝑁 𝑉𝑁 P𝑇𝑁 𝑠C𝑁 𝑁 ′ 𝑠C𝑁 𝑁 | {z } A

(7) where 𝑉𝑁 ∈ 𝐶 𝜂1 , 𝑉𝑁 ′ ∈ 𝐶 𝜂2 , 𝐽𝑁 ∈ 𝐶 𝜂1 , 𝐽𝑁 ′ ∈ 𝐶 𝜂2 , 𝜖×𝜂 𝜖×𝜂 P𝑁 ∈ {1, 0, −1} 1 , P𝑁 ′ ∈ {1, 0, −1} 2 , C𝑁 𝑁 ∈ ℝ𝜂1 ×𝜂1 , C𝑁 𝑁 ′ ∈ ℝ𝜂1 ×𝜂2 , C𝑁 ′ 𝑁 ′ ∈ ℝ𝜂2 ×𝜂2 . Matrix P𝑁 ′ has full column rank. It is supposed that no current flows into the nodes from the subset 𝑁 ′ : 𝐽𝑁 ′ = 0. If we consider the voltage in the super nodes as an input 𝑉𝑁 , and currents flowing into the system through them as an output 𝐽𝑁 , we come to the following system: ⎛ ⎞ ) ( ) )⎟ ( ⎜( R −P𝑁 ′ P𝑁 L 0 ⎜ ⎟ 𝑥 = 𝑉𝑁 , +𝑠 ⎜ ⎟ −𝑠C𝑁 ′ 𝑁 0 C𝑁 ′ 𝑁 ′ ⎠ 0 ⎝ P𝑇𝑁 ′ {z } {z } | | | {z } ˆ C

ˆ G

𝐽𝑁 =

( |

P𝑇𝑁

𝑠C𝑇𝑁 ′ 𝑁

{z

B𝑇 𝑜 (𝑠)

B𝑖 (𝑠)

) }

(8)

𝑥 + 𝑠C𝑁 𝑁 𝑉𝑁 ,

(9)

( )𝑇 where 𝑥 = 𝐼 𝑇 , 𝑉𝑁𝑇′ . It should be noted that in (8) matrix G is positive real, and matrix C is positive semidefinite. Eliminating 𝑥 from (7) or (8), one obtains that 𝐽𝑁 is linearly related to 𝑉𝑁 , i.e. ) ( ˆ + 𝑠C) ˆ −1 B𝑖 (𝑠) + 𝑠C𝑁 𝑁 𝑉𝑁 , 𝐽𝑁 = B𝑇𝑜 (𝑠)(G (10) | {z } Y1 (𝑠)

where Y1 (𝑠) is admittance matrix of the circuit on the base of all super nodes. It has the same structure as Y(𝑠) in (3) but different dimension. In order to carry out frequency (time) domain analysis of the reduced circuit, Fasterix simplifies Y1 (𝑠) by using frequency approximations and realize it as an RCL circuit. In the next section we will give a framework of these steps. B. Approximations of Y1 (𝑠) Depending on the frequency range of interest, three different methods can be distinguished to obtain approximation of Y1 (𝑠): low, high and full frequency range approximation. Below we consider two of them which will be used in this paper.

1) High frequency range approximation: was created for caring out simulations in frequency domain. The high frequency range approximation of Y1 (𝑠) is constructed as Y3 (𝑠) = 𝑠−2 Y𝑅 + 𝑠−1 Y𝐿 + Y𝐺 + 𝑠Y𝐶 ,

(11)

where Y𝑅 , Y𝐿 , Y𝐺 , Y𝐶 ∈ ℝ𝜂1 ×𝜂1 . Details about calculation of these matrices can be found in [2], [14]. Error is evaluated as ( ) ∣Y3 (𝑠) − Y1 (𝑠)∣ = 𝑂 (𝑖𝑘0 ℎ)2 , (12)

where ℎ denotes a mesh size, 𝑘0 is the free space wavenumber. Fasterix chooses ℎ such that 𝑘0 ℎ ≪ 1, which guarantees that Y3 (𝑠) approximates Y1 (𝑠) well in the range of interest. 2) Full frequency range approximation: was created especially for time domain simulations. In [14] the full frequency range approximation of Y1 (𝑠) is constructed as Y3 (𝑠) = Y𝑅𝐿 (𝑠) + 𝑠Y𝐶 ,

(13)

where Y𝐶 comes from the high frequency range approximation (11). Error is estimated as in (12). Y𝑅𝐿 can be presented in the pole-residue form: ( )−1 𝑇 Y𝑅𝐿 (𝑠) = P𝑇𝑁 Ψ Ψ𝑇 (R + 𝑠L)Ψ Ψ P𝑁 = ) ( ) ( 𝑛 ∑ Ψ𝑇 P𝑁 𝑥𝑖 𝑦𝑖∗ P𝑇𝑁 Ψ , 𝑛 = 𝜖 − 𝜂2 . (14) (𝑠 − 𝜆𝑖 ) 𝑖=1 𝜆𝑖 are the eigenvalues of the matrix pencil (Ψ𝑇 LΨ, −Ψ𝑇 RΨ). Matrix Ψ ∈ ℝ𝜖×𝜖−𝜂2 is such that its columns span the null space of P𝑇𝑁 ′ : P𝑇𝑁 ′ Ψ = 0, Ψ𝑇 P𝑁 ′ = 0.

(15)

It should be noted that since Ψ𝑇 LΨ and Ψ𝑇 RΨ are real and symmetric (case of Hermitian matrices) and −Ψ𝑇 RΨ is negative definite, 𝜆𝑖 ∈ ℝ and 𝜆𝑖 < 0. Moreover left and right eigenvectors 𝑥𝑖 , 𝑦𝑖 ∈ ℝ𝜂1 are equal. It is enough to conclude that Y𝑅𝐿 (𝑠) describes a stable system. Below we present the algorithm to obtain data for admittance Y𝑅𝐿 (𝑠) in (14). Algorithm 1. 𝜖×𝜂 INPUT: R ∈ ℝ𝜖×𝜖 , L ∈ ℝ𝜖×𝜖 , P ∈ {1, 0, −1} , 𝑁 , 𝑁 ′ 𝜂1 ×𝜂1 OUTPUT: H𝑖 ∈ ℝ , 𝜆𝑖 ∈ ℝ, 𝑖 = 1, . . . , 𝜖 − 𝜂1 𝜖×𝜂 𝜖×𝜂 1. Define P𝑁 ∈ {1, 0, −1} 1 , P𝑁 ′ ∈ {1, 0, −1} 2 ; 𝑇 𝜖×𝜖−𝜂2 such that P𝑁 ′ Ψ = 0 and 2. Calculate Ψ ∈ ℝ Ψ𝑇 P𝑁 ′ = 0; 3. A := Ψ𝑇 RΨ, B := Ψ𝑇 LΨ; 4. Solve generalized( eigenvalue ) ( problem) −A𝑥 = 𝜆B𝑥; 5. Compute H𝑖 := Ψ𝑇 P𝑁 𝑥𝑖 𝑥∗𝑖 P𝑇𝑁 Ψ , for 𝑖 = 1, ...𝜖 − 𝜂2 . At the step 4, calculation of eigenvalues 𝜆 and eigenvectors 𝑥 can be performed by QR or QZ methods (complexity 𝑂(𝑛3 )), [16]. However in order to build the reduced circuit described by Y3 (𝑠) and be able to carry out simulations in time domain, admittance Y3 (𝑠) has to be realized as an RLC circuit. A netlist of such circuit can be used in a circuit simulator program. In the next section we overview the procedure for realization used in Fasterix.

C. Frequency fitting and realization First we introduce the concept of branch admittance of a given admittance matrix Y(𝑠). Branch admittance between node 𝑖 and ground is defined by y𝑖𝑖 =

𝑛 ∑

Y𝑖𝑗 .

(16)

𝑗=1

Branch admittance between node 𝑖 and node 𝑗: y𝑖𝑗 = −Y𝑖𝑗 , 𝑖 ∕= 𝑗.

(17)

Let y3 (𝑠) denotes branch admittance of Y3 (𝑠). Since calculation of all eigenvalues 𝜆𝑖 in (14) may be a time consuming process (QR,QZ methods have complexity 𝑂(𝑛3 ), so for 𝑛 > 103 these methods are very time consuming), Fasterix first approximates y3 (𝑠) with 𝑚 < 𝑛 terms. A set of 𝑚 + 1 match frequencies, 𝑠𝑘 , is chosen. This set consists of some large negative values between maximum predefined frequency −Ω and − max(𝜆𝑖 ), and some small negative values between − min(𝜆𝑖 ) and 0. For each 𝑠𝑘 , corresponding admittance matrix has to be calculated. One of the possible options is to calculate the Y3 (𝑠𝑘 )’s for the large negative 𝑠𝑘 values by the high frequency approximation and for the small negative 𝑠𝑘 values by low frequency approximation. Solving the following set of 𝑚 + 1 equations 𝑠𝑘 y𝐶,𝑖𝑗 +

𝑚 ∑ 𝑙=1

˜ 𝑙,𝑖𝑗 H = y3,𝑖𝑗 (𝑠𝑘 ), 𝑘 = 1, ...𝑚 + 1. (18) (𝑠𝑘 − 𝜆𝑙 )

˜ 𝑙,𝑖𝑗 , 𝑙 = 1, . . . , 𝑚 is equivalent for the coefficients y𝐶,𝑖𝑗 and H to determine the approximation of y3 (𝑠) with 𝑚 < 𝑛 terms (usually 2 ≤ 𝑚 ≤ 8). The synthesized circuit consists of branches between every pair of circuit nodes. Each branch consists of 𝑚 parallel connections of a series resistor 𝑅 and inductor 𝐿, in parallel with a capacitor 𝐶. Thus for the branch 𝑙 (𝑙 = 1, . . . , 𝑚) between the circuit nodes 𝑖 and 𝑗 −1

−1

˜ 𝑙,𝑖𝑗 , 𝐿𝑙 = H ˜ 𝑙,𝑖𝑗 , 𝐶𝑙 = y𝐶,𝑖𝑗 . 𝑅𝑙 = −𝜆𝑙 H

(19)

Realization of the circuit in (19) corresponds to a general multi-port network realization based on Foster’s canonical form [17],[18]. In practice Fasterix omits R’s and L’s in the branches between each node and ground since they usually have very large values. D. Summary of the super node algorithm Below we present the SNA. First three steps are taken from the Algorithm 1. We skip the calculation of the capacitance matrix Y𝐶 (step 2) which can be found in [14]. Calculation of eigenvalues (step 3) is based on the algorithm developed by Parlett and Reid [19]. For implementation details the reader is referred to [20]. Algorithm 2 INPUT: R ∈ ℝ𝜖×𝜖 , L ∈ ℝ𝜖×𝜖 , C ∈ ℝ𝜂×𝜂 , P ∈ 𝜖×𝜂 {1, 0, −1} , 𝑁 , 𝑁 ′ OUTPUT: netlist of the reduced circuit; 1. Perform steps 1-3 of the Algorithm1;

2. Calculate Y𝐶 ∈ ℝ𝜂1 ×𝜂1 ; 3. Choose 𝑚. Calculate 𝑚 + 1 the smallest and the largest eigenvalues 𝜆 of the generalized eigenvalue problem −A𝑥 = 𝜆B𝑥; ˜ 𝑙,𝑖𝑗 , 4. Solving the set of 𝑚 + 1 equations in (18) for y𝐶,𝑖𝑗 , H 𝑖, 𝑗 = 1, . . . , 𝜂1 ; 5. Construct netlist according to (19). According to [2], the reduced circuit obtained after the Algorithm 2, when observed from its ports, is equivalent to the interconnect system up to the maximum frequency. E. Comparison with Krylov subspace methods Since Y(𝑠) in (4) is not in the first-order form, we cannot directly apply traditional MOR techniques [15]. By adding extra equations to the system (8)-(9), as it is done in [9], one can write voltage to current transfer in the familiar form: 𝐽𝑝 = (B𝑇 (G + 𝑠C)B) ⋅ 𝑉𝑝 , where B ∈ ℝ𝜂+𝜖+𝑝×𝑝 does not depend on 𝑠 any more and G, C ∈ ℝ𝜂+𝜖+𝑝×𝜂+𝜖+𝑝 . If one is only interested in the port behavior, one can use general MOR techniques. In [9], Prima and SVD-Laguerre algorithms shown good approximation with the original Fasterix systems in frequency and time domain while preserving passivity. However, if simulations of radiation have to be performed, the voltage at certain extra nodes (super nodes) are required. Treating super nodes as ports will lead to systems with many ports. Applying Krylov projections will automatically create fill-in in the reduced matrices, and as a result, synthesized model would have many electrical components (usually higher than the number of elements in the original circuit) [21].

TABLE I DATA FOR THE ORIGINAL AND REDUCED CIRCUITS OF THE TWO PRINTED STRIPLINES MODEL FROM FASTERIX model

ports

R

L

C

𝐿𝑚𝑢𝑡𝑢𝑎𝑙

time

original reduced

5 5

8 60

8 60

10 21

20 0

0.01 0.01

larger than in the original one. In this case it is not significant since initially the model is very small. For carrying out simulations we used PSTAR [22] which is Philips (NXP) simulator program. For transient analysis, a trapezoidal pulse having rise/fall times of 1 ps and pulse width of 1 ns is applied to the pins of the lower strip. A 50 Ω resistor R𝑜𝑢𝑡 is connected between two ports of the upper strip. The voltage is measured over R𝑜𝑢𝑡 and regarded as output. Figure shows the transient response at R𝑜𝑢𝑡 . It can be seen that simulation in time domain is unstable which can be explained by non-passivity of the reduced model. Indeed the pole-zero analysis of the reduced circuit detected a few unstable poles which means that the circuit is not passive. In the next section we will explain why the SNA delivers non-passive models and present a way to overcome this problem.

IV. N UMERICAL EXAMPLE The following Fasterix model will validate the problem with the SNA. The model consists of two printed striplines, which are parallel to each other. The striplines are 1 mm wide and the length is 15 mm. The model has five ports: 𝐼𝑁1 , 𝑂𝑈 𝑇1 , 𝐼𝑁2 , 𝑂𝑈 𝑇2 and 𝑂𝑈 𝑇3 . For the maximum frequency 1 MHz, Fasterix generates a mesh with 10 elements, see Figure 𝐼𝑉 . Four elements of the mesh are quadrilateral and six have the form of edges. Corresponding matrices R ∈ ℝ8×8 , L ∈ 𝕃8×8 and C ∈ ℂ10×10 in (1)-(2) are sparse. In order to build the

Fig. 1. Mesh for the two parallel striplines model (left) and the lowpass filter (right).

reduced circuit, Fasterix chooses 6 super nodes (𝜂1 = 6), they shown as black dots, and applies the SNA. In (13) Y𝐶 is indefinite with one negative eigenvalue, poles 𝜆𝑖 are real and stable. Five frequencies in the range from 0 till 6 MHz were chosen by Fasterix for frequency fitting. Data for the original and reduced circuits are presented in the table I. It can be seen that the number of elements in the reduced circuit is slightly

Fig. 2. Time response of the original circuit (red curve) and the reduced one (blue curve) by the SNA. Non passivity of the reduced circuit causes unstable simulations.

V. P OSITIVE REALNESS AND PASSIVITY An important property of general RLC circuits is passivity. Roughly speaking, a system is passive if it does not generate energy. Passivity is closely related to the positive realness of the transfer function; see e.g. [23], [8]. Admittance matrix Y(𝑠) is called positive real if the following three conditions are satisfied: 1. Y(𝑠) is analytic for all 𝑠 with 𝑅𝑒(𝑠) > 0 (i.e. there are no poles 𝜆 with 𝑅𝑒(𝜆) > 0), 2. Y∗ (𝑠) = Y(¯ 𝑠) for all 𝑠 ∈ ℂ, 3. Y(𝑠)+Y∗ (𝑠) ≥ 0 for all 𝑠 with 𝑅𝑒(𝑠) > 0 (i.e. Y(𝑠)+Y∗ (𝑠) is nonnegative definite for 𝑅𝑒(𝑠) > 0). Here 𝑠¯ denotes the complex conjugate of 𝑠 and * denotes the complex conjugate transpose. Condition (1) is satisfied if there are no right-half plane poles. Condition (2) is satisfied for circuits with real elements. Proving condition (3) usually requires clever matrix manipulations.

In the SNA, the admittance matrix plays the role of a system function. We will prove that admittance matrix Y(𝑠) of the original circuit and similarly Y1 (𝑠) are positive real however the synthesized circuit by the SNA is not necessarily passive. 𝑛×𝑛 be the set of 𝑛×𝑛 real symmetric positive definite Let 𝑆+ matrices. Definition A complex matrix A is said to be positive definite 𝑛×𝑛 . if A + A∗ ∈ 𝑆+ ] [ A11 A12 be a complex posiLemma 1: Let A = A21 A22 tive definite matrix. The Schur complement A𝑠 = A22 − A21 A−1 11 A12 of the block A11 of A is positive definite. Proof: From the fact that A is a positive definite matrix, it follows that A11 is positive definite and nonsingular. Now we notice that [ ] [ ]∗ I 0 I 0 ∗ (A + A ) = −A21 A−1 I −A21 A−1 I 11 11 ] [ ∗ A11 + A∗11 A12 − A11 A−∗ 11 A21 , (20) ∗ ∗ (A12 − A11 A−∗ A𝑠 + A∗𝑠 11 A21 ) where A𝑠 = A22 −A21 A−1 11 A12 . The left side of (20) is positive definite (note A + A∗ is multiplied on the left and on the right sides by invertible matrix; by Sylvester law of Inertia [16], the result is positive definite matrix). Thus A𝑠 + A∗𝑠 is positive definite as a principal minor of positive definite matrix. A𝑠 is the Schur complement of the block A11 of the matrix A. Theorem 5.1: Admittance Y1 (𝑠) in (10) is positive real. Proof: First, Y1 (𝑠) is analytic for all 𝑠 with 𝑅𝑒(𝑠) > 0. Indeed, all poles defined by generalized eigenvalue problem ˆ = C𝜆x ˆ ˆ is positive real, C ˆ is positive definite) are −Gx (G nonnegative. It can be easily checked that the second condition of positive realness holds true. To show that the third condition is satisfied, we notice that Y1 (𝑠) is the Schur complement of the block ( ) R + 𝑠L −P𝑁 ′ (21) P𝑇𝑁 ′ 𝑠C𝑁 ′ 𝑁 ′ of the matrix ( A defied in (7), ) which is positive definite: for each 𝑥𝑇 = 𝑥𝑇1 𝑥𝑇2 𝑥𝑇3 ∈ ℝ𝜂+𝜖 , 𝑥 ∕= 0 it follows 𝑥𝑇 (A + A∗ ) 𝑥 = 𝑥𝑇1 (R)𝑥1 > 0.

(22)

By Lemma 1, Y1 (𝑠) is positive definite. Similarly it can be proved that Y(𝑠) in (4) is positive real. Positive in (13) is not guaranteed: Y𝑅𝐿 (𝑠) = ( realness of Y3)(𝑠) −1 𝑇 P𝑇𝑁 Ψ Ψ𝑇 (R + 𝑠L)Ψ Ψ P𝑁 is positive real (to show it, see e.g. [8]), however in practice Y𝐶 might be indefinite. Moreover frequency fitting step in the SNA which is applied to Y3 (𝑠) may destroy positive realness and therefore passivity of the synthesized circuit. VI. PASSIVITY ENFORCEMENT Previous example has shown that simulation involving a fitted Y can sometimes lead to unstable simulations, even though the elements of Y have been fitted well in frequency domain using stable poles only. In order to overcome this problem we use a passivity enforcement technique presented

in [13]. In our case only a small correction needs to be done for the fitted Y3 (𝑠) to make it positive real. Indeed, by Theorem 1, the super nodes circuit described by Y1 (𝑠) is passive. The last approximation, Y3 (𝑠), approximates Y1 (𝑠) well till the maximum predefined frequency (Fasterix takes care that the error in (12) is small enough). Frequency fitting in (18) delivers also fine approximation of Y3 (𝑠) since the last one is described by only real poles (therefore there are no peaks in frequency domain need to be approximated). Thus the only disadvantage is that fitted admittance matrix Y3 (𝑠) with elements of the form 𝑛 ∑ 𝑐𝑚 Y(𝑠)𝑖𝑗 = + 𝑑 + 𝑠𝑒. (23) 𝑠 − 𝑎𝑚 𝑚=1 might not be positive real. It is a good idea to modify some or all parameters 𝑐𝑚 , 𝑎𝑚 ,𝑑 and 𝑒 in order to guarantee positive realness of (23) and therefore passivity of the circuit. That is exactly can be done by the algorithm in [13]. The idea of( the technique is) to modify vector of parameters 𝑥0 = 𝑐𝑚 𝑎𝑚 𝑑 𝑒 with a correction Δ𝑥 in such a way that the modified rational approximation Y(𝑠, 𝑥 ˜) with parameters 𝑥 ˜ = 𝑥0 +Δ𝑥 provides a passive system. Ideally we would like to find the correction in an optimal sense, namely minimizing the error between the original solution Y(𝑠, 𝑥0 ) and the fitted one Y(𝑠, 𝑥 ˜): Y(𝑠, 𝑥0 ) − Y(𝑠, 𝑥 ˜) → 0.

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In [13] approximation of Y(𝑠, 𝑥 ˜) can be written through the linearization of (23) as Y(𝑠, 𝑥 ˜) = Y(𝑠, 𝑥0 ) + MΔ𝑥. Thus MΔ𝑥 → Y(𝑠, 𝑥0 ) − Y(𝑠, 𝑥 ˜),

(25)

subject to the passivity constraint. The passivity constraint can be also written through the linearization between the eigenvalues of 𝑅𝑒 {Y} and the parameter Δ𝑥 as Δ𝜆 = RΔ𝑥 ≥ −𝜆.

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Based on (25)-(26) a least square solution Δ𝑥 can be obtained and added to 𝑥0 . The procedure is repeated untill all constraints have been satisfied. A code of this passivity enforcement technique [13] was written by B. Gustavsen in Matlab and available in public domain. We include this technique in the Algorithm 2 between steps 4 and 5. This allows us to keep the structure of reduced circuits unchanged and to guarantee passivity. VII. N UMERICAL EXAMPLES In this section the SNA with passivity enforcement correction will be analyzed on some Fasterix models. The algorithm was implemented in Matlab 7.5 and tested on Core 2 Duo 1.6 GHz PC. A. Two parallel striplines Figure 3 shows simulation in time domain of the passive circuit made in PSTAR. CPU run time for the SNA is 0.06 sec. while passivity enforcement procedure on 100 samples takes 1.06 sec. Time response of the synthesized passive reduced circuit matches well the original one.

Fig. 3. Time response of the original circuit (blue curve) and reduced passive one (red curve). TABLE II DATA OF THE ORIGINAL , REDUCED PASSIVE CIRCUITS OF THE LOWPASS FILTER MODEL

Model

ports

R

L

C

452

2763

Original

2

452

Reduced

2

19012 19012 4851

rithm delivers stable models, nevertheless we have shown that passivity is not always guaranteed. To overcome this problem, a passivity enforcement technique has been incorporated in the algorithm. The technique calculates a correction to the rational approximation of admittance matrix based on linearization and constrained minimization by Quadratic Programming. Due to this correction the modified SNA always delivers passive circuits which have exactly the same size as after applying the algorithm without passivity enforcement. Consequently the modified algorithm is also compatible for computation of radiation in Fasterix. Numerical examples validate the proposed approach. R EFERENCES

𝐿𝑚𝑢𝑡𝑢𝑎𝑙

time

50950

1011.7 s.

0

47.9 s.

B. Lowpass filter A 10 mm length piece of metal is considered, see Figure 𝐼𝑉 . The structure has two ports IN and OUT. For the maximum frequency 10 GHz, Fasterix generates a mesh with 𝜂 = 257 elements and 𝜖 = 452 common edges between each two neighboring elements. In order to build a reduced circuit, Fasterix chooses 98 super nodes (𝜂1 = 98). Table II shows comparison of the original and reduced circuits after applying the SNA with passivity enforcement. It can be seen that the reduced circuit has smaller amount of elements and simulation time of transient analysis in PSTAR was decreased significantly. For transient analysis, a trapezoidal pulse having rise/fall times of 1 ps and pulse width of 1 ns is applied between the two ports. A 50 Ω resistor R𝑖𝑛 is connected between the first port and the voltage source. A 50 Ω resistor R𝑜𝑢𝑡 is connected between the second port and ground. The voltage is measured over R𝑜𝑢𝑡 . Figure 4 shows that the signal response stays bounded in time domain. CPU run time for the SNA is 3.72 sec. and for passivity enforcement on 300 samples is 11.36 sec.

Fig. 4. Time response of the original model (blue curve) and reduced passive one (red curve).

VIII. C ONCLUSIONS In this paper an overview of a reduction technique used in the EM tool Fasterix, the SNA, has been presented. This algo-

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