898
IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 7, JULY 2011
Origin of Low-Frequency Noise in the Low Drain Current Range of Bottom-Gate Amorphous IGZO Thin-Film Transistors Christoforos G. Theodorou, Andreas Tsormpatzoglou, Charalabos A. Dimitriadis, Member, IEEE, Shahrukh A. Khan, Member, IEEE, Miltiadis K. Hatalis, Senior Member, IEEE, Jalal Jomaah, and Gerard Ghibaudo
Abstract—The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in the low drain current range. The noise spectra show generation–recombination (g-r) noise at drain currents Id < 5 nA, attributed to bulk traps located in a thin layer of the IGZO close to the conducting channel. At higher drain currents, a pure 1/f noise is observed. It is shown that the carrier number fluctuations are responsible for the 1/f noise due to trapping/detrapping of carriers in slow oxide traps, located near the interface with uniform spatial distribution. Index Terms—Amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs), carrier number fluctuation, generation–recombination (g–r) noise, low-frequency noise (LFN).
I. I NTRODUCTION
I
N DISPLAYS, thin-film transistors (TFTs) are used as switching elements in the active matrix over a large area. However, due to the high process temperature (> 350 ◦ C), amorphous Si and polysilicon TFTs are not readily available on low-cost flexible substrates. Currently, amorphous oxide TFTs have been attracting much attention due to their excellent electrical and optical characteristics [1]. In particular, amorphous indium–gallium–zinc oxide (a-IGZO) TFTs have shown high electron mobility and ON/OFF current ratio, good large area uniformity, visible light transparency, and sufficient electrical stability [2]. These properties make them suitable both as the switching devices of an active matrix as well as for the TFT circuits of integrated display drivers. Although there have been a number of reports on the electrical characterization of a-IGZO TFTs, little is known about their low-frequency noise (LFN) properties. In recent reports, in the above threshold range where the series resistance is important, the results have revealed 1/f noise as the dominant LFN source. The 1/f noise has been attributed to Manuscript received March 29, 2011; accepted April 6, 2011. Date of publication May 16, 2011; date of current version June 29, 2011. This work was supported by the program HRAKLEITOS II of the Greek Ministry of Education, Lifelong Learning and Religious Affairs. The review of this letter was arranged by Editor X. Zhou. C. G. Theodorou, A. Tsormpatzoglou, and C. A. Dimitriadis are with the Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece (e-mail:
[email protected]). S. A. Khan and M. K. Hatalis are with the Electrical and Computer Engineering Department, Display Research Laboratory, Lehigh University, Bethlehem, PA 18015 USA. J. Jomaah and G. Ghibaudo are with the IMEP-LAHC Laboratory, MINATEC, 38054 Grenoble Cedex 9, France. Digital Object Identifier 10.1109/LED.2011.2143386
the mobility fluctuations originating from the carrier-phonon scattering [3]–[5] and the carrier number fluctuation due either to the trapping/release of carriers in traps located in the gate dielectric near the interface [6] or to the superposition of generation–recombination (g-r) noise from traps in the aIGZO thin film with different time constants resulting in a 1/f spectrum [7]. Moreover, investigations of the 1/f noise in all operation regimes have been interpreted in terms of the carrier number fluctuation model in the subthreshold regime and the bulk mobility fluctuation model in the ohmic and saturation regimes [8]. In this letter, we present the noise properties of bottom-gate a-IGZO TFTs in the low drain current range, where the effect of the series resistance is negligible. The physical origin of the measured g–r noise arising from single trap level and 1/f noise is discussed.
II. E XPERIMENTAL The TFTs were fabricated on Si substrates, isolated with a 2-μm-thick thermally grown SiO2 layer [Fig. 1(a)]. First, 150-nm Mo was deposited forming the gate electrodes. A 100-nm-thick SiO2 was then deposited by PECVD at 300 ◦ C to form the gate dielectric. Then, a stack of 50 nm of IGZO and 50 nm of SiO2 were deposited sequentially by RF sputtering. The sputtering of the IGZO film was performed from a 150-mm target (1:1:1 molar ratio of In2 O3 : Ga2 O3 : ZnO). The IGZO/SiO2 stack was then lithographically patterned and etched by a combination of plasma etching (CF4 ) for the SiO2 layer followed by wet etching (dilute HCl) for the IGZO layer. Another SiO2 layer 70 nm thick was then RF sputter deposited to further passivate and protect the IGZO active channel region. Contact openings to gate, source, and drain (S/D) regions were accomplished by lithography and dry etching of the oxide layer. In order to improve contact resistance, the exposed S/D areas were treated by Ar plasma. Finally, Mo source and drain metallization was done by sputtering and subsequent lift-off. The completed devices were then annealed for 1 h at 300 ◦ C in N2 ambient. The devices were characterized using a computercontrolled system including a Keithley 6514 electrometer and two Keithley 230 voltage sources. Noise measurements were performed at room temperature with floating the substrate using SR760 fast Fourier transform spectrum analyzer and SR570 low-noise current preamplifier and CdNi batteries as bias sources to reduce any external LFN.
0741-3106/$26.00 © 2011 IEEE
THEODOROU et al.: ORIGIN OF LFN IN LOW DRAIN CURRENT RANGE OF BOTTOM-GATE A-IGZO TFT S
899
Fig. 2. (a) Drain current noise spectra of IGZO TFT, measured at drain voltage Vd = 0.1 V and different drain currents. (b) Extraction of g–r noise parameters Sg−r (0) and fc for Id = 0.3 nA.
Fig. 1. (a) Cross-sectional schematic of fabricated a-IGZO TFTs with backchannel passivation. (b) Id –Vg characteristics of a fabricated a-IGZO TFT, with back-channel passivation, channel width W = 80 μm, and channel length L = 10 μm, measured at Vd = 0.1 V.
III. R ESULTS AND D ISCUSSION Fig. 1(b) shows the transfer characteristic of a fabricated a-IGZO TFT with channel width W = 80 μm and length L = 10 μm, measured in the linear region (Vd = 0.1 V). Based on the standard MOSFET equation, the extracted device parameters are shown in the inset of Fig. 1(b). Fig. 2(a) shows typical plots of noise power spectral density SI versus frequency f , measured at different drain currents. At very low drain currents, the spectra show a g–r-type noise with a plateau at very low frequencies followed by a 1/f 2 decrease, related to trapping and detrapping processes of carriers at discrete traps with a dominant time constant τ . For drain currents Id > 5 nA, the g–r noise is overshadowed by a higher 1/f noise component. The physical origins of the g-r and 1/f noise are described in detail in [9] and [10], respectively. The g–r noise is described by the relation Sg−r = Sg−r (0)/[1 + (f /fc )2 ], where Sg−r (0) is the plateau of the g–r noise spectrum and fc is the corner frequency directly related to the trap time constant (τ = 1/2πfc ). For Id = 0.3 nA, the derived g-r noise parameters Sg−r (0) and fc are shown in Fig. 2(b). The dependence of g-r noise parameters Sg−r (0) and τ on Id are presented in Fig. 3, where a maximum is observed in both curves. The sublinear dependence of τ on Id suggests that the discrete trap centers responsible for the g-r noise are located in the bulk of the IGZO at some distance from the gate oxide/semiconductor interface, i.e., these are not interface states for which τ must be linearly dependent on Id [11]. The finding that τ is not constant but depends on Id indicates that
Fig. 3. Variation of Sg−r (0) and τ with drain current for the g-r noise in IGZO TFT with W/L = 80 μm/10 μm.
the g-r bulk trap centers are not homogeneously distributed over the thickness of the depletion region, but they are located in a thin layer of the depletion region, which influences the nearby carriers in the conducting channel [11]. Fig. 4 shows the plot of SI /Id2 versus Id of the 1/f noise measured at frequency f = 2 Hz and the corresponding (gm /Id )2 where gm is the TFT transconductance. The Hooge mobility fluctuation model predicts that SI /Id2 should vary as 1/Id [10], which is not valid as shown by the broken line in Fig. 4. However, the same trend is found for the quantities SI /Id2 and (gm /Id )2 , which indicates that the 1/f noise originates from carrier number fluctuations due to electron exchange between channel and traps located in the gate insulator close to the a-IGZO/SiO2 interface as in crystalline Si MOSFETs [10]. Similar origin for the 1/f noise was found also in polycrystalline, nanocrystalline, and amorphous silicon TFTs [12], [13]. It has been recognized that the interface of these TFTs is distinguished from that of the crystalline Si/SiO2 by comprising
900
IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 7, JULY 2011
IV. C ONCLUSION The origin of the LFN of a-IGZO TFTs has been investigated in the low drain current range. Two different sources of noise were identified: a g–r noise component at drain currents below 5 nA and a pure 1/f noise at higher drain currents. The g–r noise originates from bulk traps located in a thin layer of the depletion region, and the 1/f noise is due to the carrier number fluctuations in oxide traps with a uniform spatial distribution. ACKNOWLEDGMENT Lehigh University acknowledges the support from Versatilis LLC. Fig. 4. SI /Id2 versus Id data of the IGZO TFT measured at frequency f = 2 Hz (symbols) and the corresponding SV fb × (gm /Id )2 versus Id plot (solid line) with SV fb = 8 × 10−8 V2 /Hz adjusted to fit the data. Inset: Gate oxide trap density profile derived from the noise spectrum at Id = 30 nA.
the bulk traps, in addition to the gate oxide traps, i.e., channel material of higher disorder has a more profound effect on the gate dielectric trap properties. According to the carrier number fluctuation model, the drain current noise is given by [10] SI = Id2
gm Id
2 × SV fb ,
SV fb =
q 2 kT Nt 2 fα W LCox t
(1)
where SV fb is the flatband voltage spectral density, q is the electron charge, kT is the thermal energy, Cox is the gate capacitance per unit area, Nt is the density of the gate insulator traps, and αt is the tunneling attenuation coefficient of the electron wave function taken to be 108 cm−1 in the SiO2 [13]. From the obtained value of SV fb = 8 × 10−8 V2 /Hz in Fig. 4 and using (1), we found Nt = 2.3 × 1020 cm−3 eV−1 , which corresponds to the areal trap density of Nst = Nt /αt = 2.3 × 1012 cm−2 eV−1 . The obtained value of Nt is one to two orders of magnitude higher than those reported in previous work [6], [8], which is probably related with the lower electron mobility, i.e., the a-IGZO thin-film quality. To clarify the nature of the trap states responsible for the 1/f noise, we evaluated the surface state density Nss at the interface from the subthreshold slope, which includes both interface and bulk trap states near the midgap [14]. The obtained value is Nss = 3 × 1012 cm−2 eV−1 , which is close to the Nst value determined from the 1/f analysis, implying that the same trap states are likely involved. The generation of pure 1/f noise indicates uniform spatial distribution of the traps in the gate oxide [13]. The spatial trap distribution can be determined by converting the frequency to tunneling depth through the relation 1/2πf = τo exp(αt x), where τo is the time constant at the interface and x is the distance into the gate oxide from the interface. The typical value of τo is 10−10 s for traps distributed up to 5 nm [13]. The constant trap distribution profile is presented in the inset of Fig. 4.
R EFERENCES [1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, no. 7016, pp. 488–492, Nov. 2004. [2] T. Kamiya, K. Nomura, and H. Hosono, “Origins of high mobility and low operation voltage of amorphous oxide TFTs: Electronic structure, electron transport, defects and doping,” J. Display Technol., vol. 5, no. 7, pp. 273– 288, Jul. 2009. [3] I.-T. Cho, W.-S. Cheong, C.-S. Hwang, J.-M. Lee, H.-I. Kwon, and J.-H. Lee, “Comparative study of the low-frequency-noise behaviors in a-IGZO thin-film transistors with Al2 O3 and Al2 O3 /SiNx gate dielectrics,” IEEE Electron Device Lett., vol. 30, no. 8, pp. 828–830, Apr. 2009. [4] J.-M. Lee, W.-S. Cheong, C.-S. Hwang, I.-T. Cho, H.-I. Kwon, and J.-H. Lee, “Low-frequency noise in amorphous indium-gallium-zincoxide thin-film transistors,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 505–507, May 2009. [5] T.-C. Fung, G. Baek, and J. Kanicki, “Low frequency noise in long channel amorphous In–Ga–Zn–O thin film transistors,” J. Appl. Phys., vol. 108, no. 7, p. 074 518, Oct. 2010. [6] S. Jeon, S. I. Kim, S. Park, I. Song, J. Park, S. Kim, and C. Kim, “Lowfrequency noise performance of a bilayer InZnO–InGaZnO thin-film transistor for analog device applications,” IEEE Electron Device Lett., vol. 31, no. 10, pp. 1128–1130, Oct. 2010. [7] S. Kim, Y. Jeon, J.-H. Lee, B. D. Ahn, S. Y. Park, J.-H. Park, J. H. Kim, J. Park, D. M. Kim, and D. H. Kim, “Relation between low-frequency noise and subgap density of states in amorphous InGaZnO thin-film transistors,” IEEE Electron Device Lett., vol. 31, no. 11, pp. 1236–1238, Nov. 2010. [8] J. C. Park, S. W. Kim, C. J. Kim, S. Kim, D. H. Kim, I.-T. Cho, and H.-I. Kwon, “Low-frequency noise in amorphous indium-gallium-zinc oxide thin-film transistors from subthreshold to saturation,” Appl. Phys. Lett., vol. 97, no. 12, p. 122 104, Sep. 2010. [9] F. N. Hooge, “1/f noise sources,” IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1926–1935, Nov. 1994. [10] G. Ghibaudo, O. Roux, C. Nguyenduc, F. Balestra, and J. Brini, “Improved analysis of low frequency noise in field-effect MOS transistors,” Phys. Stat. Sol. (A), vol. 124, no. 2, pp. 571–581, Apr. 1991. [11] N. B. Lukyanchikova, M. V. Petrichuk, N. P. Garbar, L. S. Riley, and S. Hall, “A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization,” Solid State Electron., vol. 46, no. 12, pp. 2053–2061, Dec. 2002. [12] C. A. Dimitriadis, F. V. Farmakis, G. Kamarinos, and J. Brini, “Origin of low-frequency noise in polycrystalline silicon thin-film transistors,” J. Appl. Phys., vol. 91, no. 12, pp. 9919–9923, Jun. 2002. [13] E. G. Ioannidis, A. Tsormpatzoglou, D. H. Tassis, C. A. Dimitriadis, F. Templier, and G. Kamarinos, “Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise,” J. Appl. Phys., vol. 108, no. 10, p. 106 103, Nov. 2010. [14] A. Rolland, J. Richard, J. P. Kleider, and D. Mencaraglia, “Electrical properties of amorphous silicon transistors and MIS-devices: Comparative study of top nitride and bottom nitride configurations,” J. Electrochem. Soc., vol. 140, no. 12, pp. 3679–3683, Dec. 1993.
