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Propagation Delay Deviations due to Process Induced Line Parasitic Variations in Global VLSI Interconnects K. G. Verma and Raghuvir Singh

B. K. Kaushik and Manoj Kumar Majumder

School of Electronics, Shobhit University-Meerut, Meerut, INDIA [email protected]; [email protected]

Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee, INDIA [email protected]; [email protected]

Abstract- Process variation in current nanometer regime has recently emerged as a major concern in the design of very large scale integrated (VLSI) circuits including interconnect. Process variation leads to many uncertainties on circuit performances such as propagation delay. With the shrinking channel dimensions of MOSFET to nanometer scale, the performance of VLSI/ULSI chip becomes less predictable. The predictability of circuit performance may be reduced due to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper presents the variation of propagation delay through driver-interconnect-load (DIL) system due to various effects of interconnect parasitic. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies of 130nm, 70nm and 45nm. The comparison between these three technologies extensively shows that the effect of line resistive and capacitive parasitic variations on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is observed from 0.01% to 0.04% and -4.32% to 18.1% due to resistive and capacitive deviation of 6.1% to 25% respectively.

manufacturing process and the atomic scale control required for fabricating transistors. Although, process variability used to be a major concern for analog designers, but now it is also a foremost design issue [1-3] for a digital designers too and therefore its prediction is among highest priority. The impact of process variation on digital integrated circuit design and manufacture has become more critical while the complementary MOS (CMOS) circuits are continuing to shrink to the nanometer scale. Process variations with a random nature will directly result in changes in the physical structure of integrated circuits, thereby affecting their performance. In particular, the electrical performance of an integrated circuit is primarily affected by environmental and physical factors [4]. Environmental factors that occur during chip operation include power supply variations and temperature changes across the chip. Physical factors affected during fabrication include various parameters but they are not limited to interconnect line-width [5-7], metallic grain size [810] and transistor channel length [11-16]. Due to these effects of process variations, designers have to concentrate more on interconnect technology. The shrinking device sizes leads interconnect technology to global level. In global levels of interconnect, the device dimensions of VLSI chips have been aggressively reduced in the quest for improved speed, power, silicon area and cost characteristics [17-19]. Semiconductor technologies with feature sizes of several tens of nanometers are currently under development. As per International Technology Roadmap for Semiconductors (ITRS) [20], the future nanometer regime circuits will contain more than ten billion MOSFETs and will operate at clock speeds well over 20GHz. It is now undoubtedly understood that distribution of robust and reliable power and ground lines; clock; data and address; and other control signals through interconnects in such a high-speed, high-complexity environment is a tough task. The overall performance of any high-speed chip is extremely dependent on interconnects, which connect different macro cells within a VLSI/ULSI chip [21-24]. Due to ever increasing integration density and clock frequency, uncertainties linked with parameter variations

Keywords: Process variation, interconnects, VLSI, parasitic, propagation delay.

I.

INTRODUCTION

Deep sub-micron (DSM) technology allows packing billions of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) within a single chip. However, it is very difficult to fabricate extremely small transistors with same characteristics. As the feature size continues to decrease in advanced CSM nodes, the capability to forecast various characteristics of manufactured transistor is worsening. This is because of the increased complexity of the semiconductor

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emerge as a primary concern for VLSI chip design, especially in nanometer regime. Aggressive scaling of CMOS technology in sub-130-nm nodes has created huge challenges. Typically, the source of variations includes process-induced and environmental variations. The main sources of random process variation are random dopant fluctuation (RDF), line edge roughness (LER) and oxide thickness variation (OTV). Variations due to fundamental physical limits, such as RDF and LER, are increasing significantly with technology scaling [25-27]. Moreover, manufacturing tolerances in fabrication processes are not scaling at the same speed as the transistor’s channel length, due to process control limitations (e.g., subwavelength lithography) [25-27]. Therefore, within-die statistical process variation deteriorates with succeeding technology generations. This paper considers the effect of process-induced line parasitic variations on propagation delay. In current DSM technology, a major challenge of variability has been faced by semiconductor industry [25]. In addition, digital circuits show an increased sensitivity to process variations due to low-power and low voltage operation requirement, which may fail to meet timing constraints. The feature sizes are going to be reduced with increased variability. Obviously, there are other technological opportunities for aggressive scaling when more variability can be tolerated. This will lead to better and cheaper products (provided the quantities are large enough). Designers have to make the resulting variability which is sufficiently harmless by using suitable architectures and topologies. The challenge of Electronic Design Automation (EDA) is to provide accurate and efficient procedures to enable designers to understand the effect of pertinent process variability on their design. Increasing process variations can affect electrical parameters of interconnects (e.g. capacitances) and further influence circuit performance and functionality. Due to the process variation, interconnect technology parameters (ITP) are varying substantially. For the sake of simplicity, researchers consider variations in metal thickness, metal width and interlayer dielectric thickness. The typical distribution of interconnect technology parameters can be observed for permittivity, inter level dielectric thickness, metal height and metal width [26]. The variation is especially large in the ILD (Inter Level Dielectric) thickness and metal line width. Their variations have a definite impact to the total line capacitance and interline coupling capacitance and result in variation of the signal delay. Apart from these process variations, the on chip interconnect variations (OCV) are concerned with variation of interconnect width and height which results in variation of both resistance and capacitance. The delays ascribed to interconnect are becoming more dominant as geometries shrink, particular consideration should be made for accurate analysis of interconnect variations. Advanced interconnect processes involve with the use of multiple dielectrics. Erosion is the additional means for variations and is a function of line space and density. Two additional sources of variation are the Chemical Mechanical Polishing (CMP) process and proximity effects in the photolithography and etch processes. Variation

in the CMP process results from the difference of hardness of the interconnect material and that of the dielectric. Ideally the CMP process will remove the unwanted copper, leaving only lines and vias. The photolithography and etch proximity effects are shown in micro loading effects as the etch process step tends to over-etch isolated lines. Diffraction effects and local scattering in photolithography may tend to over expose densely spaced lines and under expose isolated lines. Tiling and metal slotting have been added as design rule requirements to mitigate these effects by minimizing the density gradient. Different tiling algorithms will give varying results, but the smaller the density gradient, the smaller the variations that will be seen on the die [28]. The organization of this paper is as follows. Section II describes the interconnect models. Monte Carlo analysis of Driver load interconnects (DIL) system is discussed in section III. Section IV describes the Monte Carlo based simulation results. Finally, section V draws a brief summary. II. INTERCONNECT MODELS Interconnect can be modeled as either lumped or distributed form of RC (resistance-capacitance) or RLC (resistance-capacitance-inductance). In DSM technology, lumped models are no longer capable of satisfying the accuracy requirements. It is well accepted that simulations of a distributed RC model of interconnect matches more accurately the actual behavior in comparison to lumped RC model [2124]. In similar fashion, a distributed RLC model (Fig. 1) outperforms the lumped RLC model in terms of accurate modeling of the behavior of a line. A distributed RLC model of interconnect, known as transmission line model, becomes the most accurate approximation of actual behavior of circuit [21]. The transmission line analogy for interconnect considers signal propagation as a wave propagation over interconnect medium. The transmission line model represents the transmission line as an infinite series of two-port elementary components, each representing an infinitesimally short segment of the transmission line. The distributed resistance R and inductance L are represented by a series resistor and a series inductor, respectively. Similarly, the capacitance C and conductance G of the dielectric material separating the two conductors is represented by a shunt capacitor C and a shunt resistor between the signal wire and the return wire. The model consists of an infinite series of elements, and that values of the components are specified per unit length. R, L, C, and G may also be functions of frequency. The line voltage V(x) and current I(x) can be expressed in the frequency domain as [29], (1)

(2)

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and the characteristic impedance is: (8) The solutions for V(x) and I(x) are: (a)

VN+1 RN IN+1

LN

RN-1

V2 R1

LN-1

(9)

L1 V1

IN CN

(10)

CN-1

C2

C1

(b) Fig. 1 (a) Single lump of an RLC model (b) N-Segment RLC interconnects with G neglected.

When the elements R and G are negligibly small, transmission line is considered as a lossless structure. In this hypothetical case, the model depends only on L and C element which greatly simplifies this analysis. For a lossless transmission line, the second order steady-state Telegrapher's equations are [29]:

· ·

0 0

(3)

(4)

The constants and must be determined from boundary conditions. In contrast to distributed RC model, where the signal diffuses from source to destination governed by the diffusion equation. In the wave mode, a signal propagates by alternatively transferring energy from electric to magnetic fields, or equivalently from capacitive to inductive nodes. Interconnect models must incorporate distributed self and mutual inductance to accurately estimate interconnect time delay, power dissipation, crosstalk and other parameters of significance. The evolution of various models with time is shown in Fig. 2. It is assumed that leakage conductance ‘g’ equals to ‘0’, which is true for most insulating materials such as SiO2, sapphire etc. Dealing with inductance requires efficient extraction methods. Presence of inductance also increases the processing time of computer-aided design (CAD) tools. Usually, interconnect circuits which are extracted from layouts, contain a large number of nodes that make the simulation highly CPU intensive. Distributed coupled RLC models become necessary even for the early design stages. Rtot = rℓ and Ctot=cℓ

These are wave equations which have plane waves with equal propagation speed in the forward and reverse directions as solutions. The physical significance of this is that electromagnetic waves propagate down transmission lines and in general, there is a reflected component that interferes with the original signal. These equations are fundamental to transmission line theory. If R and G are not neglected, the Telegrapher's equations become:

rΔz

rΔz

cΔz

ℓ

rΔz

cΔz

cΔz

z

(a)

(5)

Rtot = rℓ, Ltot=lℓ and Ctot=cℓ

(6)

ℓ rΔz

lΔz

cΔz

where,

rΔz

lΔz

cΔz

rΔz

lΔz

cΔz

(7)

z (b) Fig. 2 Development of interconnect models (a) RC model; (b) RLC model.

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III.

IV.

MONTE CARLO ANALYSIS OF DIL SYSTEM

The analysis has been carried out in this work takes into account a Driver-Interconnect-Load (DIL) system as shown in Fig. 3, which is further shown in Fig. 4 with RLC interconnect line. The driver is an inverter gate driving an interconnect. The propagation delay of a DIL system is dependent on various physical parameters which are prone to process variation. In this analysis, the driver is subjected to process variations for three different technologies of 130nm, 70nm and 45nm. To obtain statistical information on how much the characteristics of a circuit can be expected to scatter over the process, Monte Carlo analysis is applied. Monte Carlo analysis performs numerous simulations with different boundary conditions. It chooses randomly different process parameters within the worst case deviations from the nominal conditions for each run and allows statistical interpretation of the results. In addition to the process parameter variations, mismatch can be taken into account as well, providing a more sophisticated estimation of the overall stability of the performance with respect to variations in the processing steps. In most cases the parameters on which the assumptions for the mismatch based are worst case parameters. A proper layout and choice of devices can significantly improve scatter due to mismatch. In order to obtain reasonable statistical results, a large number of simulations are needed, leading to quite long simulation times. Using Monte Carlo simulations, this work analyzes the effect of resistive and capacitive line parasitic variation of interconnect due to process variation on the propagation delay of DIL system. The propagation delay variations through DIL system are observed for process variations in three different technologies.

m11 z=ℓ

τ

RLC Interconnect

Vin

CL

m12

RESULTS AND DISCUSSIONS

Monte Carlo simulation results are observed for deviation in propagation delay with change in line parasitics. Table-I shows variation in propagation delay due to deviations in capacitance for 130nm, 70nm and 45nm fabrication technologies. It is clearly observed that the variation in propagation delay is almost same for all process technologies of 130nm, 70nm and 45nm. These results which can also be noticed in Fig. 5, are in sharp contrast to observation made in previous research works related to process variations in oxide thickness [30], driver width [31], and threshold variations [32]. Previously, it was observed that in presence of significant variations of device model parameters, the variations in performance parameter such as delay was severely affected. The comparison between different technologies show that as feature size shrinks the process variation becomes a dominant factor and subsequently raises the variation in delays. Contradictorily, as per results it is observed that although the deviation in delay is more pronounced with increase in line capacitance variation, but these variations have almost same magnitude as the process technology changes from 130nm to 45nm. The delay variations are from -4.32% to 18.1% due to capacitive deviation of -6.1% to 25%. TABLE I VARIATION IN PROPAGATION DELAY DUE TO DEVIATION IN CAPACITANCE FOR 130NM, 70NM AND 45NM FABRICATION TECHNOLOGY % Variation in capacitance -6.08 -2.43 -2.33 -0.29 1.19 2.6 5.28 5.53 7.63 24.92

Propagation Delay Variation (130nm) -4.64 -1.87 -1.79 -0.2 0.83 1.82 3.71 3.87 5.3 17.93



Fig. 3 Driver Interconnect Load (DIL) System

m11

τ

Vin m12

Rtot = rℓ, Ltot=lℓ and Ctot=cℓ z=ℓ ℓ rΔz lΔz rΔz lΔz rΔz lΔz cΔz

cΔz

CL

cΔz

z Fig. 4 DIL system with RLC interconnect line

Fig. 5 Plot showing percentage deviation in propagation delay with respect to process induced capacitance variation.

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TABLE II VARIATION IN PROPAGATION DELAY DUE TO DEVIATION IN RESISTANCE FOR 130NM, 70NM AND 45NM FABRICATION TECHNOLOGY % Variation in Resistance -6.09 -2.44 -2.33 -0.29 1.19 2.6 5.29 5.53 7.63 24.92

Propagation Delay Variation (130nm) -0.01 0 0 0 0 0 0.01 0.01 0.01 0.04

Propagation Delay Variation (70nm) -0.01 0 0 0 0 0.01 0.01 0.01 0.01 0.04

Propagation Delay Variation (45nm) -0.01 0 0 0 0 0.01 0.01 0.01 0.01 0.04

Now, Table-II shows variation in propagation delay due to deviations in resistance for different fabrication technologies. It is demonstrated that the variation in propagation delay is almost same for all process technologies. These results (Fig. 6) are again in sharp contrast to observations made by previous research works where the variations in performance parameter such as delay is severely affected with reduction in feature size for higher technologies. Previous researches illustrated that with shrinking feature sizes process variation turned out to be dominant and subsequently raised the variation in delays. Contradictorily, our results observe that the deviation in delay is extremely small for variation of line resistance even upto 25% in global VLSI interconnects domain. Moreover, these variations are in same magnitude as the process technology changes from 130nm to 45nm. The delay variations were

from -0.01% to 0.04 % due to resistive deviation of -6.1% to 25%.

Fig. 6 Plot showing percentage deviation in propagation delay with respect to process induced resistance variation.

V.

CONCLUSION

This research work evaluates the effect of process induced interconnect resistive and capacitive parasitic deviation on propagation delay. These effects are observed

for process corners of 130nm, 70nm and 45nm technologies. Monte Carlo simulations are run using distributed DIL model. The comparison between these three technologies interestingly demonstrates that the effect of line resistive and capacitive parasitic variation on propagation delay has almost uniform trend as device size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is from 0.01% to 0.04% for a variation of line resistance from -6.1% to 25%. Similarly the observed delay variations are from -4.32% to 18.1 % due to capacitive deviation of -6.1% to 25%. REFERENCES [1]

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