Pulse Width Modulation Based On Phase Locked Loop

Pulse Width Modulation Based On Phase Locked Loop P. Wisartpong, J. Koseeyaporn, and P.Wardkein Department of Telecommunication Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok, 10520 THAILAND [email protected] Abstract- A new circuit structure which improves performance of a pulse width modulator is proposed in this paper. The proposed PWM circuit is based on a phase locked loop (PLL) system where the input signal is fed to combine with the output of a phase detector (PD). which it achieve a high accuracy PWM output. In addition , we also use R-S flip-flop and monostable circuit as a phase detector which give rise to get a PWM modulator that wide input range. The experimental results agree well with analytical results.

I.

INTRODUCTION

It is well-known that modulation is one of many important processes in communication systems, for example, AM, FM, PM, ASK, FSK, PSK, PAM, PPM, and PWM. Among various modulation techniques whose carrier is a square wave, PWM has played an important role, not only in communication system but also in other fields. For example, in power electronic field, PWM is used to be DC-to-DC converter, and DC-to-AC converter. In control system, PWM is employed to control motor speed. Additionally, it is used for a class D power amplifier in acoustic system. In literature review, most researches were focused on PWM signal generating [1,4,5]. The methods used for generating PWM can be categorized into two main groups. The first group is natural sampling PWM whereas the other group is uniform sampling PWM. In general, natural sampling PWM is most widely used. This is because its circuit is small and simple. Also, a S/H circuit is not required as it must be in the uniform sampling PWM counterpart. To generate natural sampling PWM signal, two schemes can be accomplished. The first scheme employs a saw-tooth signal which is either directly compared with an information signal, or first combined with an information signal before comparing the combined signal with a constant signal (DC voltage). It is found that modulation index of the method which directly compares a sawtooth signal with an information signal is more easily controlled than that of the other technique. It is noted that modulation index is a duty cycle of PWM for the zero input signal. For the second scheme, a triangular wave is used. Similarly to the sawtooth case, it can be directly compared with an information signal or first combined with an information signal before comparing the combined result with a constant signal. It should be noted that the method which directly compares a triangular wave with an information signal will result in a PWM signal with a constant carrier frequency whereas the other scheme

provides a PWM signal whose carrier frequency is varied with an information signal. No matter what a sawtooth signal or a triangular wave is employed for generating natural sampling PWM signal, one major drawback of this method is, however, inevitable. It is found that interference noise can cause error in duty cycle of the PWM signal. To improve this advantage, various new methods have been studied and proposed by many researchers. For example, M. Siripruchyanun et al. proposed a PWM signal generating circuit using CCII [1]. In 2001, M. J. Nasila reported the patent name “Phase Locked Loop Pulse Width Modulation System” in the US, which is the PWM construction with phase locked loop and the constant carrier PWM signal is obtained [2]. Later in 2005, Y. Zheng and his colleague also proposed PWM signal generating with phase locked loop technique but the proposed circuit was complicated [3]. In this paper, a method for PWM signal generating based PLL technique is proposed. Although the concept of the proposed circuit is quite similar to that of M. J. Nasila but these techniques are differ in the position of input signal feeding. In the proposed circuit, the input signal is fed to the loop filter rather than fed to the VCO as used in [2]. The mathematical analysis of the proposed circuit will be given to illustrate the improved performance over that of [2]. Especially, the proposed method provides less error in duty cycle of PWM signal than that of [2]. The organization of this article is given as follows. The brief review of PLL is discussed in section II. In section III, the phase shifter and PWM that is proposed by [2] is described and analyzed. Later, the proposed phase shifter and PWM based on PLL are discussed in section IV. In addition, the R-S flip-flop phase detector is explained in section V. The experimental results are demonstrated in section VI. Finally, the conclusions are given in section VI II. PRINCIPLES OF PLL The block diagram in Fig. 1 is a conventional phase locked loop (PLL), which is composed a phase detector (PD), a loop filter or a low pass filter, a VCO, and an integrator. It is noted that the notations in Fig. 1 are

φo (t ) = ωit + θi +

B ωr ωi − K K

(6)

Therefore, φD (t ) = φi (t ) − φo (t ) =

φo (s )

Laplace transform of phase input function φo (t ) Laplace transform of phase error ve (t )

vL (s )

Laplace transform of loop filter output vL (t )

ωL (s )

Laplace transform of frequency output of VCO ωL (t ) Transfer function of loop filter

F (s ) ωr (s )

Laplace transform of frequency running of VCO

kd

Gain of phase detector

ko

Gain of VCO

A B

Gain of loop filter Gain of integrator

(7)

A block diagram of a phase shifter and a PWM proposed in [2] is depicted in Fig. 2 where a summing amplifier used to feed the input signal (VC) is placed between a loop filter and a VCO.

Laplace transform of phase input function φi (t )

ve (s )

; K = ABkd ko .

III. ANALYTICAL PHASE SHIFTER AND PWM [2]

Figure 1. Block diagram of a conventional PLL.

φi (s )

ωi B ωr − K K

Figure 2. Block diagram of a phase shifter and PWM [2].

From Fig. 1, the relationship of the system can be written as F (s )Bkdkoφo (s ) F (s )Bkdkoφi (s ) B ωr (s ) + φo (s ) = + . s s s

(1)

By substituting a transfer function of the loop filter as F (s ) =

ABkd koφo (s ) ABkd koφi (s ) BVC ko B ωr (s ) + φo (s ) = + + . s (1 + Gs ) s (1 + Gs ) s s

F (s ) =

(2)

(3)

By taking inverse Laplace transform to both sides of (3), it thus becomes d 2φo (t ) d φo (t ) d ω (t ) G + + K φo (t ) = K φi (t ) + B ωr (t ) + BG r . dt 2 dt dt

(4)

Since ωr (t ) is not a function of time, the first and second derivative of this term (shown in the right-side of (4)) are zero. Therefore, 2

G

d φo (t ) d φo (t ) + + K φo (t ) = K φi (t ) + B ωr (t ) . dt 2 dt

(5)

From (5), the solution for φo (t ) can be determined by solving this differential equation. In general, φo (t ) is composed of two parts which are homogeneous solution (natural response) and particular solution (forced response). For this work, only steady state response is of interest, the natural response is therefore ignored. To determine the forced response, let φi (t ) be assumed as φi (t ) = ωit + θi where ωi is an input frequency. Then φo (t ) = at + b where a, b are constant. By replacing φi (t ) and φo (t ) into (5), hence

A , let K = ABkd ko then (8) is rewritten to be 1 + GS

Gs 2φo (s ) + s φo (s ) + K φo (s ) = K φi (s ) + BVC ko + sGBVC ko + B ωr (s ) + BGs ωr (s ).

For convenience, let K = ABkd ko then (2) is rewritten to be Gs 2φo (s ) + s φo (s ) + K φo (s ) = K φi (s ) + B ωr (s ) + BGs ωr (s ) .

(8)

By substituting a transfer function of the loop filter as

A , into (1), it then yields 1 + GS

ABkd koφo (s ) ABkdkoφi (s ) B ωr (s ) + φo (s ) = + . s (1 + Gs ) s (1 + Gs ) s

From Fig. 2, the relationship of the system can be written as

G

(9)

d 2φo (t ) d φo (t ) + + K φo (t ) dt 2 dt

= K φi (t ) + BVC ko + B ωr (t ) +

GBkod (VC ) dt

+ BG

d ωr (t ) . dt

(10)

But ωr (t ) is actually constant, the first and second derivative of this term thus (shown in the right-side of (10)) are zero, hence G

d 2φo (t ) d φo (t ) + + K φo (t ) = K φi (t ) + BVC ko + B ωr (t ) . dt 2 dt

(11)

In similar to the analyst of the PLL as shown in Fig. 1, the φo (t ) and error phase voltage ( φD ) are φo (t ) = ωit + θi +

BVC ko B ωr ωi + − K K K

(12)

where φD (t ) = φi (t ) − φo (t ) =

ωi BVC ko B ωr + − K K K

; K = ABkdko .

(13)

From (13), it is seen that the error phase voltage ( φD ) is directly proportional to input signal (VC ). It implies that if

VC is a time varying signal then phase difference will not

only depend on information input VC but also depend on the first derivative of VC as shown in (10). This leads to error of phase difference from the input signal. For a time varying input signal, the relationship between VC and φD in term of transfer function is obtained as given by Bko [1 + j ωG ] (K − ω 2 ) + j ω   

φD (ω) =

φD (ω ) =

Bko 1 + ω G 2

(K − ω 2 )

=

ωi BVC ko B ωr + − K K K

; K = ABkd ko .

φD (ω) =

Bko (K −G ω 2 ) + j ω   

(21)

Where magnitude and phase respectively are φD (ω) =

2

(15)

+ ω2

   ω  . ∠φD (ω) =  tan−1(ωG ) − tan−1   (K − ω 2 )    

(16)

IV. THE PROPOSED PHASE SHIFTER AND PWM The proposed circuit structure is shown in Fig. 3. When it is compared with the circuit of [2], it is seen that summing amplifier used to feed the input signal (VC) is instead placed between a phase detector and a loop filter.

Figure 3. Block diagram of the propose phase shifter.

The relationship of the system shown in Fig. 3 is given by ABkdkoφo (s ) ABkdkoφi (s ) BVC ko B ωr (s ) . + φo (s ) = + + s (1 + Gs ) s (1 + Gs ) s (1 + Gs ) s

Bko 2

(K − G ω 2 )

+ ω2

,

  ω  ∠φD (ω) = − tan −1   (K − G ω 2 )   

To alleviate problem of error phase difference, a modified circuit structure is proposed which will be analyzed in the following section.

d 2φo (t ) d φo (t ) + + K φo (t ) dt 2 dt = K φi (t ) + BVC ko + B ωr (t ) + BG

d ωr (t ) . dt

In this section, a phase detector using an R-S F/F and a mono-stable multi-vibrator is described. Conventionally, phase difference is detected by using an Ex-OR gate where output of an Ex-OR gate is a PWM signal whose a carrier frequency is twice of a reference signal. However, it is found that phase detector based an Ex-OR gate can detect phase only in range 0 – 180 (or – 90 to 90) degree. To increase range of phase detection, a new circuit structure of phase detector by using a R-S F/F and a mono-stable multivibrator is thus employed as shown in Fig. 4. As diagram shown in Fig. 5, the wide positive pulse of ( φi ) and ( φo ) signal are decreased by mono-stable multi-vibrator circuit and then fed to S and R position of the R-S flip flop, respectively.

(17)

(18)

In similar to the analyst of the PLL as shown in Fig. 1, the

where

BVC ko B ωr ωi + − K K K

(19)

(23)

V. R-S FLIP-FLOP PHASE DETECTOR

φo (t ) and phase difference voltage ( φD ) are φo (t ) = ωit + θi +

(22)

By comparing (15) of [2] with (22) of the proposed circuit, it is seen if K  ω , φD (ω ) of [2] shown in (15) will vary with frequency of the input signal VC . But for the proposed circuit, φD (ω ) shown in (22) is less sensitive to frequency the input signal VC . As described, the proposed circuit is therefore superior to the circuit in [2], especially in error of phase difference.

Let K = ABkd ko then, G

(20)

Similarly, the transfer function of VC and φD is

(14)

where magnitude and phase of φD (ω) are 2

φD (t ) = φi (t ) − φo (t )

Figure 4. R-S flip-flop phase detector.

Figure 5. Timing diagram of a phase detector.

In this experiment, the input signal is a 1Vp-p sinusoidal signal whose frequency is varied from 7 kHz to 12 kHz. The results of total harmonics distortion obtained from those described circuits (a) – (c) are illustrated in Fig. 8. It is obviously seen that the proposed circuit is superior to the circuit of [2]. In addition, the results obtained from (b) and (c) in Fig. 8 imply that the phase detector using an R-S F/F and a multi-vibrator provides more improvement in performance of the proposed circuit than that of using an EX-OR gate.

VI. EXPERIMENTAL RESUTLS Firstly, the phase-detector circuit based R-S F/F is examined with various DC voltage values where output signal represents phase shifting. As can be seen in Fig. 6, the phase detector using R-S F/F is able to detect phase from 350 to 10 degree for 0.5 to 3 input DC voltage, respectively. It is obvious that this circuit provides wider range of phase shift than that of using an EX-OR gate. Later, the proposed circuit is tested with a triangular wave whose frequency is 15 kHz where the PWM’s carrier frequency (the output signal of phase detector) is set at 200 kHz. The generated PWM signal is demonstrated in Fig. 7. Moreover, to compare the performance of the proposed circuit in term of phase distortion with the circuit proposed in [2], the following circuit structures are employed : (a) The circuit proposed by [2] (see Fig. 2) where a phase detector used is based on an EX-OR gate. (b) The proposed circuit (see Fig. 3) where a phase detector used is based on an EX-OR gate. (c) The proposed circuit (see Fig. 3) where a phase detector used is based on an R-S F/F.

Figure 8. Compared results of total harmonics distortion.

VII. CONCLUSIONS In this paper, a new structure of the PWM circuit based on PLL is presented. The mathematical analysis and experimental results of the proposed circuit shows that this circuit provides superior performance than the compared circuit. In addition, a phase detector based an R-S F/F and a multi-vibrator is employed in the proposed circuit. It provides wider range of phase detection compared to that of using an EX-OR gate. The compared results of total harmonic distortion clearly confirm the improved performance of the proposed circuit over the compared circuit structures. ACKNOWLEDGMENT The authors would like to thank Telecommunication Engineering Department, MUT, for encouragement.

Figure 6. Phase shifting versus input DC voltage.

REFERENCES [1] M. Siripruchyanun, P. Wardkein, W. Sangpisit, “A simple pulse width modulator using current conveyor,” TENCON 2000. Proceedings, vol. 1, pp. 452-457, 2000. [2] M. J. Nasila, “Phase-Locked Loop Pulse-Width Modulation System,” United States Patent, Patent No. US6208216B1, 27 Mar. 2001. [3] Y. Zheng; C.E. Saavedra, ”Pulse width modulator using a phase-locked loop variable phase shifter,” IEEE International Symposium on Circuits and Systems (ISCAS2005), Page 3639 - 3642 Vol. 4, 23-26 May 2005. [4] J.M. Goldberg and M.B. Sandler, “New High Accuracy Pulse Width Modulation Based Digital-to-Analog Convertor/Power Amplifier”, IEE.Proc.-Circuits Devices Syst., Vol.141, No.4, pp.315-324. August 1994. [5] Mehran Mirkazemi-Moud, Barry W. Williams, and Tim C. Green, A Novel Simulation Technique for the Analysis of Digital Asynchronous Pulse Width Modulation”, IEEE Transactions on Industry Applications, Vol.30, No.5, September/October 1994.

Figure 7. Input signal and PWM signal of the proposed circuit.