Self-Checking Test Circuits for Latches and Flip-Flops

Self-Checking Test Circuits for Latches and Flip-Flops Renato P. Ribas1,2, Yuyang Sun1, André I. Reis2, André Ivanov1 1

2

University of British Columbia 2356 Main Mall Vancouver, BC, V6T 1Z4, Canada

Federal University of Rio Grande do Sul Av. Bento Gonçalves, 9500 Porto Alegre, RS, 91501-970, Brazil

[email protected], [email protected], [email protected], [email protected] Abstract—This work proposes design strategies applicable to selftest circuits for the functional validation of latches and flip-flops. The proposed methodology is also useful for, delay test and power consumption analysis that can also be performed over the circuits under test. Moreover, the evaluation of the impacts on circuit operation due to power supply variations and nanometer aging effects can be explored through the self-timed execution mode by monitoring the run frequency. The self-timed and self-checking characteristics make the proposed solutions very attractive for testing standard cell libraries as well as for comparing different implementations of such storage elements. We have validated the addressed strategies at transistor level through electrical simulations. Keywords- test circuit, digital design, flip-flop, latch, cell library.

I. INTRODUCTION Most ASIC designs rely on a cell based methodology. Predesigned cell libraries are reused to build more complex digital circuits and systems. The use of a cell based methodology implies in a pre-validation of all cells available in a target library before applying the cells in consumer application products. Such verification must be done for every combinational gate (AND, OR, AOI,…) and storage element (latches and flip-flops) available in the library. This verification process has to take into account the functionality, timing performance and power consumption of each cell. As a consequence, it is necessary to verify the cells for all possible input stimuli that may occur on the cells during their normal operation inside application circuits. Furthermore, the pre-validation of cell libraries may include the evaluation of their robustness in terms of power supply variation, IR drop, input pin coupling noise, process parameters variation and aging effects, like NBTI and TDDB. In standard cell libraries, three groups of logic gates typically co-exist: (1) inverters/buffers; (2) combinational cells and (3) sequential cells. Inverters and buffers are easily tested by using ring oscillators. A test circuit for evaluating and validating general sets of combinational cells has been proposed in [1]. Storage elements (or sequential cells), in turn, are considerably more complex to validate due: (1) to the data previously memorized in the circuit; and (2) to the dependency on the ongoing input signal states and transitions. The presence of both synchronous and asynchronous input signals makes this validation even more difficult.

The task of cell validation is different from characterization processes, which are normally carried on semiconductor devices. In this work there is no intention to correlate all the individual timing and power data from electrical simulation with on silicon experimental measurements. Standard cell libraries are extensively characterized through electrical simulations for different operating conditions of input signal slope and output capacitive load, different design corners (process parameters, operating temperature, power supply voltage), and even in terms of different noise bump profile interference. Timing, power and noise cell modeling are then built from this simulated data and represented through equations and look-up tables. It is impractical to verify all that information. The contribution for cell validation presented in this paper is of a different nature. First, it is assumed that cell models are usually validated by correlating the performance of test circuits with static timing analysis and power estimation, provided by IC design environments. Secondly, we provide a design strategy that creates test circuits where the instantiation of cells is more favorable to perform the validation efficiently. Prior works on test of latches and flip-flops have focused mainly on speed performance, metastability and noise analysis [2-5]. However, in terms of standard cell library validation, the primary issue is the correct functionality of the cells. In our work, we demonstrate that the full functional verification of single D-type latch and D-type flip-flop can represent a very complex task, in particular when the use of test equipment and external generation of test vectors are aimed to be minimized. Moreover, the self-timed circuit operation and the self-checking feature allow a continuous delay test procedure (for aging effects) and automatic pass/fail detection (auto stopping due to circuit failure) [1]. The test and characterization of latches and flip-flops remains of interest due to the importance of these cells in ASIC designs and due to the challenges associated to their evaluation. In [6], Nedovic et al. proposed a test circuit for on-chip measurement of timing characteristics and power consumption. However, this approach is not suitable for full functional verification when asynchronous set and reset signals are present in the cell under test. Al-Assadi [7] presents a detailed analysis of all possible faults in D-latches and master-slave flip-flops, where the fault modeling of storage elements and the impact in the functionality of sequential circuits are discussed. However, resistive opens are

c 978-1-4577-1056-8/11/$26.00 2011 IEEE 210 2011 IEEE 17th International On-Line Testing Symposium

critical faults in latches and flip-flops because they are not easily detected by functional tests in normal circuit operation, being usually observed through delay test according to the impact in the timing characteristics of cells [8]. The identification of potential faults in the internal feedback loops, observed in static memorization elements, can also be quite complex. This is due to the fact that such loops are necessary only for long term storage. Thus, very low frequency operation of clocked storage elements can be applied to verify for losses (or change) of data. For this kind of verification, besides the self-timed operation mode, the proposed circuits also run in synchronous mode, controlled by an external clock signal. This mode allows a kind of static evaluation of data retention, and it is also useful as a diagnosis step to identify errors in the test circuits. Finally, in terms of power dissipation analysis, the synchronous operation mode allows the evaluation of the cells under a specific operating frequency. The obtained data can be then correlated to power estimation data provided by the IC design flow, in order to validate the cell power model built from electrical simulation measurements. Static consumption, in turn, can be verified through manual (or very low frequency) external clock signal for all possible steady states at each cell under test. For that, the test circuit must cover all such possible input/output static values of the cell under test. Section II discusses the test circuit for a D-type latch, while a flip-flop is treated in Section III. Section IV summarizes the contributions of this work. II. D-LATCH WITH SR D-type latches, with or without asynchronous set and reset signals, can be seen as generic latches available in cell libraries. Considering the enable signal (E) activated at high level (logic value 1), with asynchronous set (S) and reset (R) signals also activated at high logic value, the functional behavior can be described as indicated in Fig. 1. S 1 0 0 0 1

R 0 1 0 0 1

E x x 0 1 x

D x x x (0,1) x

Q 1 0 Q-1 (memorize) D (transparency) (not applied)

Figure 1. D-type latch with set and reset: symbol and truth table.

Analyzing the functional behavior in terms of possible output signal transitions related to a single transition in the input pins (D, E, S and R), the following possibilities arise. For a positive (low-to-high) transition at the output Q, the transition can result from: a) a positive transition at the input D, when E is activated and asynchronous signals (S and R) are deactivated; b) the activation of enable signal E, when output Q is low and input D is high, with both S and R signals deactivated; c) the activation of set signal S, when output Q is low and with asynchronous reset R deactivated;

d) the deactivation of reset signal R, when enable E is activated and input D is high (set signal S deactivated). Fig. 2 illustrates the test circuit proposed for a D-latch cell. It is a particular shift-register with twelve latches whose enable signal polarity alternates at every couple of latches. The enable of all latches is controlled by the same signal Ei. Moreover, besides a general reset to initialize the entire chain, some stages (L01, L03, L06, L10 and L11) also have their set and reset pins activated by the specific signals Si and Ri, respectively. The functionality of this particular shift-register is illustrated in Table I, according to the input stimuli (Si, Ri and Ei) indicated in this table. The ‘IC’ column represents the initial condition of the circuit (general reset action).

Figure 2. Test circuit for functional verification of D-type latch.

In terms of functional test coverage, two different situations may be analyzed: (1) the steady state values, and (2) the expected output transitions according to a signal transition in a single input. The proposed circuit provides the verification of all these possible static and transition situations. The steady states, described in Fig. 1, appear in different cell instantiations at different moments during the shift-register operation. Table II.a indicates when each steady state occurs, i.e., the time step Tn as indicated in Table I, and in which latch instantiation Ln (as depicted in Fig. 2) it is observed. The situation when both set and reset signals are activated has not been considered (last row in Table II.a). The possible output signal transitions are also identified in different instantiations at different moments, as shown in Table II.b. If one of these transitions fails, then the functional behavior of the shift-register, as described in Table I, is invalid. In terms of unexpected output transitions that can occur due a latch cell failure, the number of possibilities is quite large and the proposed circuit is able to verify around 50% of these. TABLE I – BEHAVIOR DESCRIPTION OF THE TEST CIRCUIT IN FIG. 2. Tn 00 01 02 03 04 05 06 07 08 09 10 11 12

IC 1 0 0 0 0 0 0 0 0 0 0 0 0

Si 0 1 0 0 0 0 0 0 0 0 0 0 0

Ri 0 0 0 0 0 0 0 1 0 0 0 0 0

Ei Q01 Q02 0 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0

Q03 0 1 0 0 1 1 1 0 1 1 0 0 0

Q04 0 1 0 0 1 1 1 0 1 1 0 0 0

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Q05 0 0 0 0 0 1 1 1 1 1 1 0 0

Q06 0 1 1 0 0 1 1 0 0 1 1 0 0

Q07 0 1 1 1 0 0 1 0 0 0 1 1 0

Q08 0 1 1 1 0 0 1 0 0 0 1 1 0

Q09 1 1 1 1 1 0 0 0 0 0 0 1 1

Q10 1 1 1 1 1 0 0 0 0 0 0 1 1

Q11 1 1 1 1 1 1 0 0 0 0 0 0 1

Q12 1 1 1 1 1 1 0 0 0 0 0 0 1

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The input signals (Si, Ri and Ei) of the test circuit are generated according to the output data [Q01,Q02,..,Q12], by a specific logic block. For instance, the Si signal goes high when the output data is equal to [111111110000], shown as occurring at time Tn = 06 in Table I. A similar procedure is done for inputs Ri and Ei, according to the expected behavior shown in Table I. These signals can be synchronized by an external clock by using a flip-flop barrier at each one. As a result, only two external signals are required to stimulate the test circuit. These are the external clock and the general reset signal for initialization. The correct circuit operation can be verified by simply monitoring the internal signals Si, Ri and Ei. The circuit monitoring can be simplified by exploiting a self-timed architecture approach. The handshake control of this self-timed circuit is done naturally by the logic block that provides the signals Si, Ri and Ei. This means that the circuit operation switches from the synchronous mode to the self-timed operation by simply avoiding the flip-flop barriers mentioned before. This is a useful feature that provides a selftimed and self-checking circuit primarily for pass/fail test, but also for delay test and continuous operation for aging degradation evaluation and power supply variation analysis. Any circuit error stops automatically the self-timed computation. TABLE II – TEST COVERAGE OF D-LATCH WITH ASYNCHRONOUS SET AND RESET: (A) STEADY STATES; (B) POSSIBLE OUTPUT TRANSITIONS. (B) (A) Tn 4 2 3 2 2 1 1 1 1 1 7 7 7 7 na

Ln 6 6 3 1 3 3 6 1 3 11 1 6 11 3 -

S 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1

R 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

E 0 0 0 0 1 1 0 0 1 1 0 0 1 1 x

D 0 0 1 1 0 1 0 1 0 1 0 1 0 1 x

Q 0 1 0 1 0 1 1 1 1 1 0 0 0 0 (?)

Tn 1 1 1 2 7 7 7 8 3 4 2 3 -

Ln S R E D Q-1 6 ↑ 0 0 0 0 1 ↑ 0 0 1 0 3 ↑ 0 1 0 0 3 ↓ 0 1 0 1 1 0 ↑ 0 0 1 6 0 ↑ 0 1 1 3 0 ↑ 1 1 1 3 0 ↓ 1 1 0 6 0 0 ↑ 0 1 3 0 0 ↑ 1 0 4 0 0 1 ↑ 0 4 0 0 1 ↓ 1 - ↑ 0 1 1 0 - 0 ↑ 1 0 1

Q ↑ ↑ ↑ ↓ ↓ ↓ ↓ ↑ ↓ ↑ ↑ ↓ na na

III. D-FLIP-FLOP WITH SR Similarly, a D-type flip-flop with asynchronous set and reset signals (DFFSR) can be considered as representative of a generic flip-flop cell available in a cell library. Its normal operation is summarized in Fig. 3. Considering the behavior of such cell in terms of the possible output signal transition related to a single transition at the input signals (D, Ck, S and R), the following analysis can be done for a DFFSR. A positive transition (low-to-high) at the output Q results in the following cases: • the activation of set signal S, if output Q is low and while asynchronous signal R is deactivated (irrespective of the state of inputs D and Ck);

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•

the activation of clock signal Ck, if output Q is low and input D is high, and when asynchronous signals (S and R) are deactivated. S 1 0 0 0 1

R 0 1 0 0 1

Ck ↑ (0,1,↓) -

D (0,1) -

Q 1 0 D (update) Q-1 (memorize) (not applied)

Figure 3. D-type flip-flop with set/reset: symbol and truth table.

In the case of a flip-flop test, we propose a modified 5-bits upcounter. This means that the flip-flop under test is instantiated five times in a counter structure. The standard counter behavior is already a good test circuit to verify the output transitions related to clock signal transitions. However, the different situations related to the asynchronous set and reset transitions must be also verified. For that, two jump procedures in the normal operation of the up-counter are provoked, as illustrated in Table III. The ‘state 1’ goes directly to the ‘state 2’ by activating the reset of bit 4 and bit 2, and the set signal of bit 3 and bit 1. This occurs when the clock signal is 0 or 1 according to the value of bit 5. A conventional counter already presents all the possible steady states and output transitions related to the flip-flop inputs Ck and D. These are indicated in Table IV with a ‘V’ mark. Besides these common characteristics, the proposed modified counter also presents the four possible transitions for the asynchronous set and reset signals. For instance, as shown in Table III, in ‘state 1’ the set transition of bit 4 (Q4) and bit 2 (Q2) corresponds to the transitions when Ck is low, and input D in these flip-flops is low and high, respectively, at this moment. In turn, ‘state 3’ represents the set transitions when Ck is high, and input D of the related cells is currently low and high, respectively, for the same bits. Similarly, the reset transitions for different input states of D and Ck are observed in bit 3 and bit 1 of this counter. The coverage of steady states and possible flipflop output transitions is illustrated in Table IV (time step Tn and flip-flop instantiation Fn). Furthermore, to complete the steady state coverage, as seen in Table IV.a, the fifth counter bit is set when the counter data is [11111] and Ck is high. The set activation (S5) of this bit (Q5) is removed after Ck goes 0. It corresponds to the time steps 46 and 47 in Table III (column Tn). The coverage of unexpected transitions by using the proposed modified up-counter is around 50%. Further work is necessary to develop means to improve this level of coverage. One way to design a self-timed test circuit is to use more than one counter in order to compare their data before applying a new input transitioning provided by a handshake control block. Notice that, in this case, each counter represents one cell under test. This is illustrated in Fig. 4. The handshake circuit works as follows. For the first counter, the logic decision for control signals (Ck_1, SR_1 and S5_1) depends on the data_1 value and the jump states indicated in Table III. For instance, Ck_1 goes high if all individual clocks are low, all counters data are equal, and data_1 is different from ‘state_1’ and ‘state_3’. For other

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TABLE IV. TEST COVERAGE OF D-TYPE FLIP-FLOP WITH SET AND RESET: (A) STEADY STATES; (B) POSSIBLE OUTPUT TRANSITIONS. (B) (A)

bits, the control signals (Ck_i, SR_i and S5_i) follow the precedent ones, going high if data(i) is different from data(i-1), and going low if data(i) is equal to the precedent one. Moreover, the self-timed circuit design can be slightly modified to run in a synchronous operation mode. This can be done by simply including flip-flop barriers in the control signals of the first counter (Ck_1, SR_1 and S5_1). The synchronous version is useful for measuring the power consumption in relation to an operating frequency. It is also useful for a step-bystep execution, allowing for a kind of diagnosis mode for fault analysis and leakage power dissipation.

Tn 47 11 46 34 11 11 34 34 (error) (error) (na)

TABLE III – MODIFIED UP-COUNTER FOR FUNCTIONAL VERIFICATION OF D-TYPE FLIP -FLOP WITH ASYNCHRONOUS SET AND RESET SIGNALS. Tn

IC

00 01 02 03 … 09 10

1 0 0 0 0 0 0

S[4,2] R[3,1] 0 0 0 0 … 0 0

11 12 13 … 32 33

0 0 0 0 0 0

1 0 0 … 0 0

0 0 0

34 35 36 … 43 44 45 46 47 48 49 50 51/01 52/02 53/03 …

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 … 0 0 0 0 0 0 0 0 0 0 0 …

0 0 0

S5 Ck D1 Q1 Q2 Q3 Q4 Q5 0 0 0 0 0 0

0 0

0 0 0 1 1 0 0 0 0 0 0

0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 1 0 … … … 1 0 1 0 1 0 0 1 0 1 up-counting jump 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 … … … 0 1 0 0 1 1 0 1 0 1 up-counting jump 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 … … … 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 1 0 … … …

0 0 0 0

0 0 0 0

0 0

0 0 state 1

1 1 1

0 state 2 0 0

0 0

1 1 state 3

1 1 1

1 state 4 1 1

1 1 1 1 1 1 0 0 0 0 0

1 1 1 1 1 1 0 0 0 0 0

S 0 1 1 1 1 0 0 0 0 1 0 1

R Ck D Q 0 x x 0/1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 x x 0 1 x x 1 1 x x (?)

Tn 11 11 34 34 11 11 34 34 -

Fn 4 2 4 2 1 3 1 3 V V

S ↑ ↑ ↑ ↑ 0 0 0 0 0 0

R Ck D Q-1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 ↑ 0 0 1 ↑ 0 1 1 ↑ 1 0 1 ↑ 1 1 1 0 ↑ 0 1 0 ↑ 1 0

Q ↑ ↑ ↑ ↑ ↓ ↓ ↓ ↓ ↓ ↑

IV. CONCLUSIONS As an extension to the work reported in [1] for combinational gates, this work presents the design of self-timed and selfchecking circuits primarily for pass/fail test of latches and flipflops. This means that, if the circuit is confirmed to be functioning correctly, then the cells under test can be considered to be fully functional. Any error and unexpected transition should automatically stop the circuit execution. The proposed methodology requires minimum interference of external circuit stimuli (input test vectors generation) due to the self-timed property. Additionally, the self-timed operation allows the monitoring of aging effects through as well as evaluating the impact of power supply variation and delay test, for instance. ACKNOWLEDGMENTS Research partially funded by CAPES Brazilian agency. The author Renato P. Ribas would also like to thank UBC and NSERC for the post-doctoral stage. REFERENCES [1] R. P. Ribas, S. Bavaresco, N. Schuch, V. Callegaro, M. Lubaszewski, and [2] [3] [4] [5] [6] [7]

Figure 4. Self-timed circuit composed by counters under test for evaluation of Dtype flip-flop with set and reset.

Fn V 5 2/4 5 2/4 3 1 3 1 -

[8]

A. I. Reis, “Contributions to the evaluation of ensembles of combinational logic gates,” Microelectronics Journal, vol. 42, no. 1, Jan. 2011. pp.371-81. M. Alioto, E. Consoli, and G. Palumbo, “Flip-flop energy / performance versus clock slope and impact on the clock network design, IEEE Trans. Circuits and Systems I, vol. 57, no. 6, June 2010. pp.1273-86. F. Mu, and C. Svensson, “Selt-tested self-synchronization circuit for mesochronous clocking,” IEEE Trans. Circuits and Systems II, vol. 48, no. 2, Feb. 2001. pp.129-40. A. Cantoni, J. Walker, and T.-D. Tomlin, “Characterization of a flip-flop metastability measurement method,” IEEE Trans. Circuits and Systems I, vol. 54, no. 5, May 2007. pp.1032-40. C. Dike, and E. Burton, “Miller and noise effects in a synchronizing flipflop”, IEEE J. Solid-State Circuits, vol. 34, no. 6, June 1999. pp.849-55. N. Nedovic, W. Walker, and V. G. Oklobdazija, “A test circuit for measurement of clocked storage element characteristics,” IEEE J. SolidState Circuits, vol. 38, no. 8, Aug. 2004. pp.1294-304. W. K. Al-Assadi, Y. K. Malaiya, and A. P. Jayasumana, “Faulty behavior of storage elements and its effects on sequential circuits,” IEEE Trans. VLSI, vol. 1, no. 4, Dec. 1993. pp.446-52. V. H. Champac, A. Zenteno, and J. L. García, “Testing of resistive opens in CMOS latches and flip-flops,” Proc. European Test Symp., pp.34-40, 2005.

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