University of Wales. P.O. Box 917. Cardiff, CF2 1XH ... pattern generation, illustrating our approach with a basic example circuit and corresponding results. The.
GENERATING TEST PATTERNS FOR VLSI CIRCUITS USING A GENETIC ALGORITHM
M. J. O'Dare and T. Arslan School of Electrical, and Electronic Engineering University of Wales P.O. Box 917 Cardiff, CF2 1XH U.K.
Indexing terms: Genetic algorithms, Test pattern generation
In this letter we present the development of a technique that utilises genetic algorithms, for generation of test patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list .
Introduction: With increasing complexity of VLSI circuits there is a constant requirement for efficient methods of automatic test pattern generation [1,2]. Genetic algorithms (GAs) have proven effective in other VLSI applications, including cell placement [3], compacting randomly generated test sets [4], and channel routing [5]. The GA is an adaptation of the biological genetic process [6-8], producing optimal solutions by manipulation of a population of binary strings governed by a selection system biased towards superior solutions. This letter introduces a methodology that has been adapted to implement GAs in test pattern generation, illustrating our approach with a basic example circuit and corresponding results. The test set produced by the GA may be passed to automatic test equipment (ATE) for stimulation of the inputs of a test circuit, a pass or fail response may then be produced.
Implementation: A population of binary strings (chromosomes) are created by random generation of each bit (gene), the chromosome length is equal to the number of inputs (n) to our test circuit, and therefore forms our test pattern. The possible number of combinations for the chromosome is 2n. Each chromosome in our population is evaluated for its efficiency as a test pattern (fitness). This is achieved by simulation of the current circuit model, an output response for each test pattern is obtained for a faultfree circuit. Fault simulation is performed by setting each node within the circuit to a logic '1' and then logic '0', in order to simulate a stuck-at-one and a stuck-at-zero fault condition respectively. In each case the circuit output is compared to that of the fault-free response, if the simulation causes an observable change in the state of the circuit output then the current fault condition is said to be detected. The chromosome that detects the most faults (the fittest) is the first entry into the test set. A global record table is established to record the faults that have been detected by the chromosomes in our test set, the table reflects the fault coverage of the test set and provides necessary information for our fitness function. A basic overview of the fitness function is presented in figure 1., for successive generations a scoring system is employed by our fitness evaluation function. During simulation the GA uses the information within the global record table to award relatively higher scores to chromosomes that detect faults within the circuit that have not been previously detected by members of the current test set. The fittest member of the population for each generation is then entered into the test set, and the information in the global record table is updated. However, a chromosome is only entered if it improves the fault coverage for the circuit, this procedure also eradicates the possibility of duplication.
Fig. 1 Fitness Function
The fitness value assigned to a chromosome determines its probability of selection as a parent, the higher the fitness value the greater the probability of the chromosome being selected to engage in crossover (reproduction). We achieve this by implementing the roulette wheel method of selection [7,8]. Our GA uses two point crossover, with a crossover rate of 100% [7], two points within the length of the chromosome are generated at random, the portions that reside between these two points are exchanged between the parent chromosomes producing two new chromosomes as offspring. New characteristics are introduced by random modification or replacement of bits within a chromosome, this process is referred to as mutation [7,8].
Results and Discussion: As an example, the GAs performance is illustrated with the 18 input circuit shown in figure 2. The test set produced is shown in column 2 of table 1., the third column represents the total fault cover of all test patterns entered up to that point, the information being updated as each new pattern is entered into the set. On this occasion the GA has produced 16 test patterns that provide 100% fault coverage for our circuit, this information is represented graphically in figure 3. A similar response was achieved in experimenting with larger circuits of more than 17 gates, and inputs ranging from 8 to 26. For 25 passes of the GA, between 15 and 19 test patterns were produced for the example circuit. The last two columns of the table reflect the contents of the GA's global record table, and show the stuck-at faults that are detected by each test pattern. For example, the first test pattern in our test set has a fault coverage of 15%, detecting potential stuck-at-zero faults on nodes f,l, and q, and potential stuck-at-one faults on nodes 3,6,9,13,14,15 and out. The last fault condition to be detected by this test set was input a stuck-at-one. Figure 2. illustrates the logic state of each node of our circuit in a fault-free state, with test pattern 15 applied to the circuit inputs. The output in the fault-free state is observed to be '1', however, if input a experienced a 'stuck-at-one' fault condition, the output would clearly change state to logic '0', allowing the fault condition to be detected. The state of the relevant nodes for this condition are shown in bold typeface in figure 2.
Fig. 2 Example Circuit
Table 1. Results of example circuit (Fig. 2) Various methods of crossover were considered, one point crossover [7,8] was initially implemented but did not perform to our satisfaction, leading us to experiment with two-point crossover which produced a higher fault coverage, in a shorter time. Different mutation rates [7] were implemented until 100% fault coverage was achieved, finally setting the mutation probability at 2.5%.
Fig. 3 Fault Coverage
Conclusions: For all of our test circuits the GA produced effective test sets with high fault coverage. The maximum time taken for producing the test patterns for the set is under two minutes on a 386 PC running at 33 MHz.
References 1
LALA P. K.,
Fault Tolerant & Fault Testable Hardware Design, Prentice/Hall International,
London, 1985. 2
RUSSELL G., KINNEMENT D. J., CHESTER E. G., AND McLAUCHLAN M. R.,
CAD for VLSI, Van
Nostrand
Reinhold, U.K., 1985. 3
HEGDE U. AND ASHMORE B., A
Feasability Study of Genetic Placement, Texas Instruments Technical
Journal, Vol. 9, No. 6, Nov-Dec 1992, pp. 72-82. 4
AYLOR J.H., COHOON J.P., FELDHOUSEN E.L AND JOHNSON B.W.,
A Genetic Algorithm For
Compacting
Randomly Generated Test Sets, International Journal of Computer Aided VLSI Design 3, 1991, pp. 259-272. 5
BUTTITTA B., ORLANDO P., SORBELLO F. AND VASSALLO G., Monreale:
A New Genetic Algorithm For
The Solution Of The Channel Routing Problem, IEEE proceedings, CH3001-5, 1991, pp 462-466. 6
HOLLAND J. H.,
Adaptation in Natural and Artificial Systems, Univ. of Michegan Press,
Ann Arbor, 1975. 7
GOLDBERG D. E.,
Genetic algorithms in search, Optimisation and Machine Learning, Addison-
Wesley, Reading, 1989 8
DAVIS L.,
Handbook of Genetic Algorithms, Van Nostrand Reinhold, New York, 1991.
Simulate model circuit for current chromosome
Is count < population length
Y Set successive bits to '1' and '0' and compare with fault free circuit
N
Calculate fittest chromosome and enter into test set
Update global record table Does Circuit output change N Y Consult global record table and score as necessary
Figure 1
Repeat for next bit
a b c d e f
g h i j k
(0) (1)
(0)
q r
B
2 (1)
C
3 (1)
D
4 (0)
10 (1)(0)
13 M
(1)(0)
(0) (0)
16 P
(1)(0)
(0) (0)
K
(0) (1)
E
11 (1)
N
5 (1)
14 (0)
(1) 6 F
(0)
(1) G
(1) n (1) o p
J
(1)
l (0)
m
1 (0)(1)
A
(1)
H
(0)
7 (1)
out L
12 (0)
8
Q O
15 (0)
(1)
(0,1) Fault-free response (0,1) Input a stuck-at-one
(0) I
(0)
(1)(0)
9 (1)
Test patterns
Circuit inputs abcdefghijklmnopqr
Percentage fault cover
Stuck-at-0 faults detected
Stuck-at-1 faults detected
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
001001100001110010 110100110000001101 110100110100011111 110000111100111101 101101110100101100 011010111100111000 100101111100110000 011011111000101101 101111010100110100 101100111100011110 111000110100111101 011111100110111000 001001100100111010 101101111110011100 101111100101110100 011000000110111000
15% 30% 47% 58% 68% 78% 82% 85% 88% 91% 92% 94% 95% 97% 98% 100%
f,l,q 6,11,14,16,out a,b,d,g,h,j,1,2,4,5 3,10,13,16,out 9,12,15,out e,g,h,m,n,o,4,5,7,8 9,12,15,out g,h,i,r,4,5 6,11,14,16,out 3,10,13,16,out a,b,c,g,h,j,1,2,4,5 k,m,n,o,7,8 6,11,14,16,out 9,12,15,out l,m,n,p,7,8 3,10,13,16,out
3,6,9,13,14,15,out i,j,k,l,5 9,10,11,13,14,15,16,out c,d,e,2 n,q,r,7 3,11,12,13,14,15,16,out o,p,q,r,8 3,9,11,13,14,15,16,out g,k,l,4 b,e,f,1 10,11,13,14,15,16,out 3,6,12,13,14,15,16,out h,k,l,4 m,q,r,7 3,6,12,13,14,15,16,out a,e,f,1
Table 1
Percentage Fault Cover
100 90 80 70 60 50 40 30 20 10 0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Test Patterns
Figure 3
