Semiconductor device and timing control circuit

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Jul 31, 2001 - Foreign Application Priority Data. Jun. ... 327/161. See application ?le for complete search history. (56
USO0RE40205E

(19) United States (12) Reissued Patent Funaba et al. (54)

(45) Date of Reissued Patent:

SEMICONDUCTOR DEVICE AND TIMING CONTROL CIRCUIT _

(75) Inventors: Seiji Funaba, Chryoda-ku (JP); Yoji Nishio, ChiyOda-ku (JP); Yuichi Okuda, Chryoda-ku (JP); Yoshlnobu Nakagome, chlyoda-ku (JP) 73

( )

Assi nee: El ida Memo

g

P

ry,

2/2002 Hashimoto ................ .. 327/158 4/2002 Akioka et a1. . 365/194

6,525,585 B1 *

2/2003

JP

y ( )

Flled:

11427062

JP

Aug‘ 23’ 2002 Related U-s- Patent Documents

JPO Notice of Reason of Refusal dated Oct. 26, 2007, in Japanese W1th Engl1sh translatron.

6,269,051

_

JUL 31, 2001 09/640 670

Primary ExamineriTan T. Nguyen (74) Attorney, Agent, or FirmiReed Smith LLP; Stanley P.

Filed.

Aug 1,8 2000

Fisher, Esq.; Juan Carlos A. Marquez, Esq. (57) ABSTRACT

.

,

Division of application No. 09/563,160, ?led on May 1,

[Control on the speed of operation of a delay loop from the

2000, now Pat. NO. 6,212,127.

output of a variable delay circuit to a delay control input

(52) (58)

thereof is performed. For example, frequency-dividing cir

Foreign Application Priority Data

Jun. 18, 1999

(51)

_

Issued: APPI' NO‘:

U.S. Applications:

(30)

10/1997

* cited by examiner

Patent No.:

.

(62)

10/1997

11-127063

OTHER PUBLICATIONS

Reissue of: (64)

Iida et a1. ................. .. 327/279

FOREIGN PATENT DOCUMENTS 10412182 0/1996 10-283060 4/1997

JP JP

Inc., Tok 0 JP

Apr. 1, 2008

6,351,166 B2 * 6,366,507 B1 *

(21) Appl. No.: 10/226,019 (22)

US RE40,205 E

(10) Patent Number:

cuits are respectively placed at the input and output of the

variable delay circuit. A signal obtained by frequency

(JP) ......................................... .. 11-171864

dividing a signal outputted from the variable delay circuit is

Int. Cl. GIIC 11/4076

supplied to one input of a phase comparator through a

(2006.01)

dummy delay circuit, and a signal obtained by frequency dividing the input of the variable delay circuit is supplied to 327/ 161

the other input of the phase comparator. Phase control is performed according to the result of comparison between the

Field of Classi?cation Search ................ .. 327/161

phases of both signals.] Control on the speed of operation of

US. Cl. ..................... .. 365/194; 365/233; 327/158;

a delay loopfrom the output ofa variable delay circuit to a

See application ?le for complete search history. (56)

delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the

References Cited

input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the

U.S. PATENT DOCUMENTS 5,430,394 A

*

5 939 913 A * 5’987’6l9 A

7/1995

McMinn et a1.

variable delay circuit is supplied to one input ofa phase . . .

.......... .. 327/292

8/1999 Tomita

* “H999

'''

327/l58

comparator through a dummy delay circuit, and a signal

' ' ' " 713/401

obtained by frequency-dividing the input of the variable

327/149

delay circui’ is Supplied Z0 [he 01h” MP1” of [he Phase comparator Phase control is performed according to the

5,990,714 A * 11/1999 Takahashi ...... 6,128,248 A 10/2000 Idei et a1‘

6,134,182 A * 10/2000 P110 et al. ................. .. 365/194 6,269,051

B1

*

7/2001

Funaba et a1.

......

. . . ..

mull OfCO/WPWI'SOn between [he Phases Ofbolh Signals

365/233

6,333,875 B1 * 12/2001 ShinoZaki et al. ........ .. 365/194

15 Claims, 25 Drawing Sheets

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Sheet 6 0f 25

US RE40,205 E

U.S. Patent

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Sheet 7 0f 25

US RE40,205 E

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Sheet 8 0f 25

US RE40,205 E

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Sheet 11 0f 25

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