SET to RESET Programming in Phase Change Memories - IEEE Xplore

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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 10, OCTOBER 2006

SET to RESET Programming in Phase Change Memories Ilya V. Karpov and Sergey A. Kostylev

Abstract—Experimental data on details of SET (crystalline) to RESET (amorphous) transition are presented for Ge2 Sb2 Te5 (GST) nonvolatile memory cell. It is shown that the main source of heat for a SET to RESET transition is the GST bulk and interface regions instead of the contacting electrode. A small-contact-area electrode is used primarily to supply current into and minimize heat loss from the chalcogenide. Increasing bottom contact resistivity offers a scaling path for RESET current with no electrical penalties. Index Terms—Chalcogenide, Ge2 Sb2 Te5 (GST), ovonic unified memory (OUM), phase change memory (PCM).

I. I NTRODUCTION

S

INCE 2000, there has been an increasing focus to understand chalcogenide-based phase change materials for nonvolatile memories [1]–[8]. In this letter, we present a new understanding of the fundamental parameters of the ovonic unified memory (OUM) through experimental results and discuss the role of a small-contact-area electrode and chalcogenide bulk in SET to RESET programming. II. E XPERIMENTAL R ESULTS AND D ISCUSSIONS Fig. 1(a) shows the resistance–current (R–I) characteristics of a SET and RESET OUM device, which uses a breakdown layer (BDL) [9]. To change a cell state from SET to RESET, a current pulse is required. For pulsewidths ranging from 30 ns to 5 ms, the RESET resistance is strongly affected only by the pulse current amplitude and does not depend on the pulse width. In [9], it is indicated that SET to RESET programming is determined by power and not by the energy supplied to the cell. In Fig. 1(b), the current–voltage (I–V ) characteristic for SET device changes slope and begins to merge with I–V for RESET device at 0.5 mA. This part of the I–V for RESET device is characterized by a dynamic resistance caused by the appearance of a high-current filament [10]–[12]. As the filament differential resistance is close to zero, the device’s dynamic resistance (dVOUM /dIOUM ) is commonly associated with the contacting electrode resistance [11]. Sharing a common I–V between initially SET and initially RESET devices indicates that chalcogenide in both devices is in a disordered state, i.e., in melt state for SET device and in amorphous Manuscript received March 2, 2006; revised July 19, 2006. The review of this letter was arranged by Editor S. Chung. I. V. Karpov is with Intel Corporation, RN3-01, Santa Clara, CA 95052 USA. S. A. Kostylev is with Ovonyx Technologies, Inc., Rochester Hills, MI 48306 USA. Digital Object Identifier 10.1109/LED.2006.882527

Fig. 1. Typical (a) R–I and (b) I–V of OUM device. Open squares represent device initially in RESET state, and open diamonds represent device initially in SET state.

state for RESET device, when a filament is formed. Thus, in Fig. 1(b), 0.5 mA marks the point at which chalcogenide melting begins to occur and where the filament produced results in equivalent dynamic resistances for both an initially SET and initially RESET device. For currents of 0.5–1 mA, the device is still in a SET state after the programming pulse terminates and the filament disappears, because the crystalline part shunts the amorphous. As programming current rises, more volume becomes amorphous, and at current above 1.2–1.5 mA for Fig. 1, a sufficient volume is in a high-resistance amorphous state and the device transitions into RESET state. We would like to point out that “melting point” was introduced in [4] as a point on the R–I curve [Fig. 1(a)] when device resistance begins to rise. It is clear that, at this point, all contact area should be covered with amorphous material. We instead refer to the start of melting as an inflection point of the I–V of initially SET device [Fig.1 (b)]. The dependence of SET to RESET programming currents and power allocation in Ge2 Sb2 Te5 (GST) and interface regions were evaluated as a function of temperature. I–V and R–I were recorded at different temperatures (0 ◦ C–100 ◦ C) on a BDL device, which is similar to the one presented in Fig. 1. The power dissipated in the contacting electrodes was calcu2 dV /dI. This power was subtracted from the lated as IRESET entire device power (IRESET · VOUM ), resulting in the power dissipated in the GST bulk plus interface. This power is also equivalent to the product of the programming current IRESET and device holding voltage (Vh ). Fig. 2 shows the dependence of programming current [Fig. 2(a)] and power [Fig. 2(b)] with temperature. One can see in Fig. 2(b) a stronger dependence on temperature for the power dissipated in chalcogenide bulk and interface: less programming power is required to reset the device at elevated temperatures, resulting in smaller power dissipation in the GST and interface regions. On the other hand,

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KARPOV AND KOSTYLEV: SET TO RESET PROGRAMMING IN PHASE CHANGE MEMORIES

Fig. 2. (a) R–I of OUM device taken at different temperatures. (b) Power at IRESET dissipated in contacts (open diamonds) and chalcogenide plus interface (open squares). IRESET is defined as the programming current which results in a saturated value of resistance for RESET device.

the power dissipated in contacts at reset programming current does not strongly depend on temperature. To further investigate the driving force behind SET to RESET transitions, the dependence of IRESET on the bottomelectrode (BE) resistivity (ρ) was studied. In this experiment, the BE deposition process was changed intentionally to increase its resistivity for two different cell types [2], [5]. If the SET to RESET transition is caused by Joule heating of the resistive BE, then IRESET √ is expected to drop with increases in BE resistivity as 1/ ρ [13]. This trend is seen in Fig. 3(a), where, for both cell types, an increase in BE resistivity results in a reduction of IRESET . Moreover, the device voltage is dropped mostly across the BE during programming. This voltage drop (i.e., IRESET · RBE , where √ RBE is the BE resistance) should rise approximately as ρ. But in both cell types, no change in the BE voltage drop was observed, as shown in Fig. 3(b). This observation can be understood if we consider that heat is dissipated mostly in the chalcogenide rather than in the resistive BE. If we assume that all of the heat generated in chalcogenide at SET to RESET transition is conducted through a cylindrical BE, then we can write that IRESET · Vh,chal /A = −K∇T , where K is the electrode’s thermal conductivity, Vh,chal is the holding voltage in chalcogenide derived from thickness dependence of Vh [11], A is the BE area, and ∇T is the temperature gradient between the molten chalcogenide and thermal ground in a cell during programming. For an ideal case where no interfacial layer is present between the chalcogenide and the BE and assuming Wiedemann–Franz relationship between thermal conductivity and electrical conductivity IRESET · RBE = C1 /Vh,chal , where C1 is a coefficient independent of BE resistivity. Indeed, as shown in Fig. 3(b), the voltage drop across the BE (IRESET · RBE ) does not depend on BE resistivity. In this case, the results indicate that an increase in electrode resistance offers a path in reducing IRESET without raising the device voltage. Furthermore, it also supports our earlier suggestion that power dissipated in chalcogenide and interface (if any), rather than Joule heating in the contacting electrodes, causes the SET to RESET transition. Finally, we propose a simple metric to assess OUM cell efficiency which, to first order, is independent of the contact area and thermal resistance of the small-area resistive contacting

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Fig. 3. (a) RESET current and (b) BE voltage drop at RESET current versus resistance of small-area resistive BE for two OUM cell types. Resistance is determined from the device’s dynamic resistance (dVOUM /dIOUM ) [11] [see Fig. 1(b)].

Fig. 4. Programming efficiency of six different types of OUM cells. 1) Smallcontact-area BE was formed by sublithographic contact hole filled with chalcogenide on top of resistive thin plate BE [2]. 2) and 3) Small-contact-area BE was formed by patterning sublithographic contact hole filled with resistive metal in contact with flat chalcogenide film [13]. 4) Sublithographic contact hole was filled with resistive metal, partially recessed, and then filled with chalcogenide [8]. 5) Breakdown device [9]. 6) Lateral cell [14].

electrode. This metric can be used to compare different cell architectures, i.e., cell efficiency = power dissipated in chalcogenide only/total power = (Pchal )/(PBE + Pinterface + Pchal ) = Vh,chal /(Ireset · dV /dI + Vh ).

(1)

The OUM cell efficiency was calculated from electrical measurements for different cell types (Fig. 4). This result suggests a dependence of programming efficiency on cell architectures.

III. C ONCLUSION It is shown that power dissipated in chalcogenide and interface rather than Joule heat from the BE is the main cause of the SET to RESET phase transition. The BE plays the role of current supplier and a “cooler” (as opposed to a heater) to insulate the programming volume from a thermal sink. The weak dependence of device voltage on BE resistivity opens the possibility of an alternative path in reducing RESET currents without the penalty of higher voltages. A larger resistivity does not necessarily result in the highest device efficiency. Thus, device efficiency is affected by cell architecture.

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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 10, OCTOBER 2006

ACKNOWLEDGMENT The authors would like to thank C. Kuo, T. Lowrey, and G. Atwood for their technical discussions. R EFERENCES [1] S. Ovshinsky, “Amorphous materials—The key to new devices,” in Proc. IEEE CAS, 1998, vol. 1, pp. 33–39. [2] S. Lai and T. Lowrey, “OUM—A 180 nm nonvolatile memory cell element for stand alone or embedded applications,” in IEDM Tech. Dig., 2001, pp. 803–806. [3] S. Lai, “Current status of phase change memory and its future,” in IEDM Tech. Dig., 2003, pp. 255–258. [4] A. Pirovano, A. L. Lacaita, A. Benvenuti, S. Hudgens, and R. Bez, “Scaling analysis of phase-change memory technology,” in IEDM Tech. Dig., 2003, pp. 699–702. [5] K. Kim, J. H. Choi, J. Choi, and H.-S. Jeong, “The future prospect of nonvolatile memory,” in VLSI Symp. Tech. Dig., 2005, pp. 88–94. [6] F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Maragon, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Gasagrande, P. Cappelletti, and R. Bez, “Novel µTrench phase change memory cell for embedded and stand-alone non-volatile memory applications,” in VLSI Symp. Tech. Dig., 2004, pp. 18–19.

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