Time-Domain Simulation of Quantization Noise Mixing and Charge Pump Device Noise in Fractional-N PLLs Maciej Kucharski1 , Frank Herzel1 , and Dietmar Kissinger1,2 1
2
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany Technische Universit¨at Berlin, Einsteinufer 17, 10587 Berlin, Germany Email:
[email protected]
Accepted version. Citation for the original published paper: 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), Grenoble, France, Jun. 2015, pp. 1-4, DOI: 10.1109/NEWCAS.2015.7182079 Go to article abstract page on IEEE Xplore. c 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any
current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Abstract—In this paper we model phase noise and spurious tones (spurs) for a fractional-N phase-locked loop (PLL) with static phase offset. The phase detector (PD) input-output characteristic around the bias point is approximated by a parabolic function. Using a MATLAB code, phase noise spectrum and fractional spurs are calculated as a function of slope and curvature of the PD characteristic. The dependence of the PLL output spectrum on PD nonlinearity and rms phase error at the PD input is discussed and compared with theoretical results. A close agreement with theoretical predictions is observed.
I.
I NTRODUCTION
Fractional-N PLLs are important for frequency synthesis with a low phase noise. They relax the trade-off known from integer-N PLLs where the frequency step ∆ fout is equal to the sampling frequency fs at the phase detector (PD) input. This dependence limits phase noise performance and settling speed considerably if a fine ∆ fout is required. A fractional-N architecture solves the problem by employing an additional subcircuit. This block switches the division ratio N in such a way that an average fractional number is synthesized. It can be realized by means of an accumulator or a Σ∆ modulator (SDM). The latter is preferable due to its capability of quantization noise shaping. However, fractional spurs affect the spectral purity of the output spectrum. This is especially critical for space applications, where a spur level below 65 dBc/Hz is required over a wide tuning range [1]. Minimization of spurs and phase noise requires accurate modeling of quantization noise folding in the nonlinear PD. The problem of noise folding in the nonlinear PD was discussed in [2] and [3]. Due to the PD nonlinearity at the origin of the input-output characteristic, in-band phase noise and spurs can be excessive. A solution of this problem is a static phase offset obtained by a DC current at the charge pump (CP) output [4]. Far from the origin, the PD characteristic can be approximated by a parabolic function [5].
In a Σ∆ fractional-N PLL the following noise sources often dominate the output noise: VCO phase noise, reference phase noise, CP device noise, and quantization noise of the SDM. Time-domain PLL noise modeling of VCO and reference has been presented in [6]. A realistic simulation of PLL phase noise also requires modeling of charge pump device noise and quantization noise, which is the topic of this paper. II.
F RACTIONAL -N PLL WITH
STATIC PHASE OFFSET
One possible approach to improve PD linearity is to shift its operation point to a larger phase error offset by applying a DC current source to the CP output [4]. This is shown in Fig. 1, where the nonlinearity is much exaggerated. The PD is biased in a more linear region where only the UP current will respond to the difference by changing its width. This is done by adding a DC current source at the CP output (Fig. 2). In locked state the entire current flowing into the loop filter should be equal to zero for the control voltage to remain constant. Hence, the DC current source forces the CP to operate at a higher duty cycle to compensate the charge. Since the PLL employs an SDM it is difficult to describe the system behavior within an analytical model. In every cycle the division ratio is changed which inevitably results in an instantaneous phase error, even if the circuitry is noiseless. For an ideal phase detector the average CP output current I is a linear function of the phase deviation from the steady state average phase error φ0 at the PFD input. The linear PD gain is then given by ICP (1) KPD = 2π where ICP is the CP current in the ON state. Taking the PD nonlinearities into account in the lowest order, I is a parabolic function of deviation φ from mean phase φ0 and reads β (2) I = KPD φ + KPD φ2 2
where β represents the PD nonlinearity [5]. The quantity β is the normalized curvature of the PD input-output characteristic at the PD operating point and is given by d2 I . dI β= . (3) dφ2 dφ The linear term in (2) produces the quantization noise spectrum that is shaped by the used SDM. Most noise power is located at high frequencies where it can be sufficiently attenuated by the loop filter. The quadratic term, however, describes the downfolded quantization noise which results in an elevated in-band phase noise plateau. A parabolic approximation seems to be reasonable for a PD operating in the shifted region (Fig. 1). As shown in [5], the in-band phase noise due to SDM noise folding in the nonlinear PD is proportional to β 2 provided that a DC offset current is employed at the CP output for PD linearization. The PD input-referred noise reads for Gaussian noise β 2 σφ4 SPD = (4) 2fs where σφ denotes the standard deviation of the phase error in radians at the PD input due to rapidly changing division ratio. Note, that the reduction of β by a factor of two reduces this phase noise contribution by 6 dB. At the PLL output PD noise is given by 2 out SPD = SPD |H| (5) where H is the transfer function from the PLL input to the output.
Fig. 2. Phase detector architecture for a fractional-N PLL with phase offset.
Fig. 3.
Block diagram of the second-order charge-pump PLL.
comes from a highly stable crystal oscillator. The CP output current I(t) flows in the low-pass filter and produces the VCO control voltage V (t). The phase error at the PD input reads φe (t) = φREF (t) − φDIV (t).
(6)
The phase error φe (t) produces a current I(t) = KPD φe (t)
(7)
where KPD denotes the linear PD gain in A/rad. The resulting VCO output frequency reads fVCO (t) = KVCO V (t)
(8)
where KVCO is the VCO gain in Hz/V. By combining these equations, we obtain an equation for the phase error, which represents a damped oscillation [7] Fig. 1.
III.
dφe (t) d2 φe (t) + 2γ + ω02 φe = 0 2 dt dt
Shifting of the PD operating point to a more linear region.
T IME - DOMAIN ANALYSIS OF CP DEVICE NOISE
In order to investigate the CP noise contribution to the PLL phase error a closed-loop time-domain analysis was performed. We consider a linear, time-invariant continuous-time model for simplicity. For the same reason, we assume a first-order loop filter, which consists of a resistor R in series with a capacitor C. The resulting second-order PLL model is shown in Fig. 3. Here, the output phase φVCO is divided by N , which is the average division factor in fractional mode. SDM quantization noise is omitted in the model. The divided output phase φDIV is then compared with the reference phase φREF , which usually
(9)
where γ=
πKPD KVCO R N
is the damping factor, and r ω0 =
2πKPD KVCO CN
(10)
(11)
is the natural angular frequency. In the next step, we consider a current noise source in parallel with the loop filter. We assume white Gaussian noise to model the CP device noise.
TABLE I.
T IME - DOMAIN SIMULATION PARAMETERS PLL parameters
fVCO
fs
N
ICP
10.00004 GHz
100 MHz
100.0004
1 mA
KVCO
R
C
SCP
200 MHz/Hz
1 kΩ
100 pF
10−22 A2 /Hz
phase error, which is then converted to current pulses in a nonlinear PD. A fast Fourier transform (FFT) is then performed to obtain the PSD of the current. The spectrum is multiplied by a corresponding transfer function to obtain the corresponding phase noise contribution at the PLL output.
Numerical parameters ∆t τ T 10 ns 0-10 µs 10 ms
Transforming (9) into a set of two integral equation we obtain Z t ωe (τ )dτ φe (t) = 0
2πRKVCO i(t) Z N t
−
0
(12) 2πKVCO 2γωe (τ ) + ω02 φe (τ ) + i(τ ) dτ CN
where i(t) is a generated CP white noise current with a given power spectral density (PSD). To solve the system of integral equations we use the predictor-corrector method [8]. In order to calculate the spectrum of the output phase error we consider the steady-state autocorrelation function (ACF) for the VCO output phase Z T −τ 1 Rφ (τ ) = lim φVCO (t + τ )φVCO (t) dt (13) T →∞ T − τ 0 From the Wiener-Khinchin theorem we obtain the two-sided PSD of the phase [9] Z ∞ Rφ (τ )e−j2πf τ dτ. (14) Sφ (f ) = −∞
All parameters used in the simulation are listed in the Table I.
Fig. 4.
Block diagram for the proposed nonlinear noise analysis.
V.
N UMERICAL RESULTS
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IV.
T IME - DOMAIN ANALYSIS OF QUANTIZATION NOISE FOLDING
In fractional mode, at each reference cycle the output frequency is divided by a different factor so there is almost always a phase error at the PD input, even if the PLL is noiseless and operates in steady state. This is due to the SDM which toggles between different integer values, thereby producing quantization noise. In case of a linear PD this noise would be suppressed by the loop filter. However, a nonlinear PD folds the quantization noise back to lower frequencies and deteriorates the in-band phase noise. In order to investigate the effect of the PD nonlinearity on the output phase noise, a fast time-domain analysis is performed according to [2]. The PD characteristic around the steady state operating point is approximated by a parabolic function as described by (2). The simulation scheme is presented in Fig. 4. A third-order single-loop SDM generates random numbers n so that the average equals F , which is the fractional part of the total division ratio. Delay and subtracting units determine a difference of RF pulses, which are swallowed by the SDM for each reference cycle. Subsequently, it is compared with a phase that would be expected if the loop was truly phase-locked. The difference is an instantaneous
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Frequency Offset (Hz) Fig. 5. Simulated phase noise spectrum due to charge pump device noise using FFT of the output phase (solid) or the FFT of the ACF (dashed), respectively.
Fig. 5 shows the simulated phase noise due to white CP noise calculated from the output phase or from the ACF of the output phase, respectively. For the latter case, the CPU time was only slightly higher, while the accuracy of the result is obviously improved in comparison to FFT of the output phase. Fig. 6 shows the phase noise spectrum for a near-integer division ratio with two or one divide-by-two circuits (DTC) between VCO and programmable divider, respectively. In the first case, the programmable divider ratio is varied around 25 and in the latter case around 50, which halves the variation of the total divider ratio around N = 100. The elimination of one DTC reduces this noise contribution including spurs by 12 dB. This was expected from (4), since with halving the variations of the total division ratio the rms phase error σφ at the PD input is also halved, and the in-band noise is ∝ σφ4 . In other words, if one DTC can be saved due to a high speed of the programmable divider the fractional spurs are expected to be
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reduced by as much as 12 dB. The improvement of the in-band phase noise by omitting the DTC will be smaller due to other phase noise contributions. As evident from Fig. 7 the fractional spurs are reduced by 20 dB if the nonlinearity parameter β is lowered by a factor of 10. This is expected from theory, since the folded quantization noise is proportional to β 2 according to (4). The same reduction was expected for the level of fractional spurs, since these spurs and the folded quantization noise result from the same effect, namely, the noise folding in the nonlinear phase detector. Note that for both cases in Fig. 7 an offset current at the CP output was assumed. The case without DC offset is not considered here, since the PD characteristic would not be differentiable at φ = 0, β according to (3) would not even exist, and the phase noise would be excessive [4]. VI.
C ONCLUSIONS
We have presented a time-domain approach for phase noise and spur modeling in a fractional-N PLL with emphasis on charge pump device noise and quantization noise folding. A stochastic integral equation for phase and frequency of the PLL output signal was derived and solved numerically for a
4
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Frequency Offset (Hz)
Frequency Offset (Hz)
Fig. 6. Simulated phase noise spectrum due to quantization noise for a PLL frequency of 10.00004 GHz and a sampling frequency fs = 100 MHz with (a) 1:4 prescaler and (b) 1:2 prescaler between VCO and programmable divider.
3
10
(b) Fig. 7.
Simulated output spectrum for (a) β=0.02 and (b) β=0.002.
white noise current at the charge pump output. By exploiting the Wiener-Khinchin theorem, we calculated the corresponding contribution to the PLL phase noise spectrum from the steadystate autocorrelation function of the PLL output phase. Phase noise and fractional spurs due to SDM quantization noise have been calculated numerically for a second-order phase detector nonlinearity. An excellent agreement with the predictions of an analytical model was obtained. In summary, we believe that the major impact of our work will be to reduce the number of design cycles when developing integrated fractional-N PLLs with a low level of in-band phase noise and spurs. R EFERENCES [1] H. Telle, A. Koelnberger, and H.-V. Heyer, ‘Development of a flexible synthesizer module with a fractional-N PLL in SiGe BiCMOS technology and an external VCO for wideband S- to Ka-band applications,’ in Proceedings of ESA/ESTEC Micro- and Millimeter Wave Technology and Techniques Workshop 2014, Noordwijk, The Netherlands, Nov. 2014, pp. 1-8. [2] B. De Muer and M. S. J. Steyaert, ‘On the analysis of ∆Σ fractional-N frequency synthesizers,’ IEEE Transactions on Circuits and Systems II: Analog Digit. Signal Processing, vol. 50, pp. 784-793, Nov. 2003. [3] T. A. D. Riley, N. M. Filiol, Q. Du and J. Kostamovaara, ‘Techniques for in-band phase noise reduction in ∆Σ synthesizers,’ IEEE Transactions
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on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, pp. 794-803, Nov. 2003. H.-M. Chien, T.-H. Lin, B. Ibrahim, L. Zhang, M. Rofougaran, A. Rofougaran, and W. J. Kaiser, ‘A 4GHz fractional-N synthesizer for IEEE 802.11a,’ 2004 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, Jun. 2004, pp. 46-49. F. Herzel, S. A. Osmany, and J. C. Scheytt, ‘Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs,’ IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, Aug. 2010, pp. 1914-1924. F. Herzel and M. Piz, ‘System-level simulation of a noisy phase-locked loop,’ in Proceedings of the 13th European Gallium Arsenide and other Compound Semiconductor Application Symposium, Paris, France, Oct. 2005, pp. 193-196. R. P. Feynman, R. B. Leighton, and M. Sands, The Feynman Lectures on Physics, p. 25. Addison-Wesley, 1964. W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical recipies, second ed., Cambridge Univ. Press, 1992. C. W. Gardiner, Handbook of stochastic methods, vol. 13, second ed., Springer, 1983.
