340 Whittemore Hall, FERMAT Lab. Blacksburg, VA, 24060, USA. {hiren, shukla}@vt.edu. Abstract. As SystemC gains popularity as a modeling language.
Towards A Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models Hiren D. Patel and Sandeep K. Shukla Virginia Polytechnic Institute and State University 340 Whittemore Hall, FERMAT Lab Blacksburg, VA, 24060, USA {hiren, shukla}@vt.edu Abstract As SystemC gains popularity as a modeling language of choice for system-on-chip (SOC) designs, heterogeneous modeling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models are simulated through a non-deterministic Discrete-Event simulation kernel, which schedules events at run-time. This sometimes results in too many delta cycles hindering the simulation performance of the model. The SystemC language also seems to target this simulation kernel as the target simulation engine making it difficult to express different Models Of Computation (MOC) naturally in SystemC. In an SOC model, different components may need to be naturally expressible in different MOCs. Some of these components may be amenable to static scheduling based simulation or other pre-simulation optimization techniques. Our goal is to create a simulation framework for heterogeneous SystemC models, to gain efficiency and ease of use within the framework of SystemC reference implementation. In this work, we focus on Synchronous Data Flow (SDF) models, where the rates of data produced and consumed by a data flow node/block are known a priori. Compile time knowledge of these rates allow the use of static scheduling resulting to significant improvement in simulation efficiency. We propose source level hints to be provided by the model designer to help express SDF more naturally and to make the new simulation kernel execute special functionalities. Our experiments show significant improvement in simulation time over the original models.
1. Introduction Embedded system design for coming generations must support a diverse range of computing applications. These
include demands placed by mobile, sensing, entertainment and biomedical applications. The computing platforms for these applications often contain a large number of heterogeneous computing elements, ranging from small handheld devices, smart sensors, and actuators up to large, multithreaded multi-processors that must work together to accomplish diverse end-to-end goals. These promote the need for the design of more complex and often heterogenous systems in both form and function. With increasing use of hardware & software co-design methodologies designers have flexibility in accommodating certain functionality in either software or hardware, thereby allowing the designer the choice for a variety of hardware. Also, a single chip can perform multiple functions such as network processors, that handle regular processor functionality as well as network protocol functionality. These varied functionalities of complex system-on-chip (SOC) embedded systems often are best modeled as a hierarchy and composition of distinct Models Of Computations (MOCs) [1]. Another important aspect of today’s embedded systems is that these systems are embedded in environments with which they interact through both discrete and continuous interactions. For example, a pace-maker may be placed inside a human body where it senses continuous signals, and behaves with discrete control. As a result, continuous time and other discrete MOCs need to be modeled and simulated together. It is well accepted that the gap between the product complexity and the engineering effort needed for its realization is increasing drastically, commonly known as the productivity gap. Many factors contribute to the productivity gap such as the lack of design methodologies, modeling frameworks & tools, hardware & software co-design environments and so on. Due to this increase in productivity gap, industries experience an unaffordable increase in design time making it difficult to meet the time-to-market. One of the solutions proposed by many to mitigate the
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productivity crisis is raising levels of abstraction for design entry, modeling and simulation. System Level Design Languages (SLDL) for SOC and embedded system design have gained considerable attention in the research community and industry alike due to the rising complexity of designing such systems. Heterogeneous and hierarchical system modeling and the ability to exploit the hierarchy and heterogeneity during all phases of the design including modeling and validation is difficult. In our view, there lies the greatest challenge in providing a high level modeling and simulation framework for such systems. The problems are: 1. To be able to express different MOCs through the modeling framework to express heterogeneity, 2. The ability to model behavioral hierarchy which may cut across various MOCs, (note that structural hierarchy is not enough, behavioral decomposability comes through behaviorial hierarchy), and 3. To provide efficient simulation framework that can exploit the different MOCs and hierarchy.
other MOCs such as Continuous Time, Process Networks, and Finite State Machines. Along with the implementation of more MOCs we are undertaking a task to restructure the Application-Protocol Interface to better suit a heterogeneous modeling environment. This restructuring will enable us to create hierarchical models and simulate them. Another important research direction we plan to follow is to exploit the behavioral hierarchy in hierarchical structure of the models to make simulation more efficient for complex SystemC models. We present Table 1 with the simulation gains. In case of models such as Converter model in Table 1, the efficiency gain is limited because the parts of the model amenable to SDF modeling constituted only about 15% of the model, as evidenced by profiling data.
Table 1. Simulation gains in % over Original models Model FIR
22
76
FFT
38
74
Sobel
11
52
Converter
5
13
2. Our Contributions in this Paper We approach these problems by making SystemC [2] a heterogeneous and truly hierarchical modeling and simulation framework. SystemC is a System Level Design Language which we choose for its popularity and endow it with capabilities of expressing various MOCs and better simulation performance. An SLDLs modeling expressiveness refers to the constructs, language and design guidelines that facilitate complete description of a system with appropriate MOCs, whereas simulation efficiency is measured by the time a model takes to simulate from start to end. As a proof of concept we implemented the Synchronous Data Flow (SDF) MOC [4, 3]. We plan on working on more general Application-Protocol Interfaces and MOC extensions to SystemC kernel. Our new SDF kernel is interoperable with SystemC’s Discrete-Event (DE) kernel providing designers with the capability to model and simulate complex heterogeneous models constructed from a collection of DE and SDF models. It is natural that by extending the simulation kernel, we not only improve the modeling expressiveness of SystemC to naturally construct models for SDF, but we also make simulation more efficient. Since, we can express SDF models better in SystemC the kernel can interpret these SDF models differently and execute them using static scheduling as opposed to dynamic scheduling that the DE kernel employs, enhancing simulation efficiency. No effort to our knowledge has attempted at implementing kernel-level solutions for multi-MOC modeling for SystemC and we believe in being the first at investigating this issue. Nonetheless, we do not plan to stop by simply showing the proof of concept by implementing the SDF kernel, but also started working on kernel-level development
SystemC Non-threaded SDF
3. Conclusion We believe that we are opening up an avenue through which SystemC can be developed into a heterogeneous and hierarchical modeling and simulation environment for better construction of complex designs. Our initial efforts will be followed by releasing our enhanced SystemC kernel to the SystemC user community. We also plan to submit our changes and proposed changes to the SystemC standards committee for review.
References [1] E. A. Lee and A. L. Sangiovanni-Vincentelli. Comparing Models of Computation. In In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pages 234–241, 1996. [2] OSCI. SystemC . Website: http://www.systemc.org. [3] H. D. Patel. HEMLOCK: HEterogeneous ModeL Of Computation Kernel for SystemC. Master’s thesis, Virginia Polytechnic Institute and State University, December 2003. Website: http://fermat.ece.vt.edu/hiren/thesis.pdf. [4] H. D. Patel and S. K. Shukla. Towards A Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models. Technical Report 200301, FERMAT Lab Virginia Tech., 2003.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-2097-9/04 $20.00 © 2004 IEEE
