VHDL Code Generator based on Component Diagrams with JavaScript and Object Serialization Christyowidiasmoro, Thomas Schumann Department of Electrical Engineering, Hochschule Darmstadt-University of Applied Sciences Birkenweg 8, D-64295 Darmstadt, Germany
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Abstract— Hardware description language (HDL) such as VHDL have made it possible for circuit and board designs to be done without resorting to paper, allowing computers to manage the design database and automate the translation between various representation of the system. Although VHDL modeling can provide a bonanza of benefits, VHDL models must be used effectively to reduce overall development costs. VHDL developers need to understand all of VHDL modeling theory including syntax and language structures to develop an electronic component. A tool to translate designed component diagram to synthesizable VHDL code is needed to solve this problem. In this paper, we present such a tool which is used to generate VHDL code based on given parameters and can be directly analyzed and synthesized. This tool provides a graphical user interface that allows the user to select a digital component, customize their parameter and generate the VHDL code.
Keywords: VHDL code generator, synthesizable VHDL code, object serialization, component diagram
1. INTRODUCTION The computer-aided engineering revolution of the last 20 years has made tremendous strides in reducing the time to develop electronic systems and components and in increasing the complexity of their functions while at the same time reducing their size, power, and weight. Modern hardware designers typically use Hardware Description Languages (HDLs) to express designs at various level of abstraction. HDLs such as VHDL have made it possible for circuit and board designs to be done without resorting to paper, allowing computers to manage the design database and automate the translation between various representations of the system. VHDL was developed to provide a standardized and technology independent way to describe formally the behavior and structure of digital electronic systems. It offers the technical means to provide functional, timing, and other specifications for digital electronic systems in a form that will be useful long
after the original system is delivered. Technology independence permits the separation of the behavior function (plus timing) from its implementation, which makes incorporating new technology easier [1]. Designers are looking for a fast direct way to convert the visualized design to HDL code directly in order to simulate and implement it. In this project, we have developed a visualization tool allowing users to build a digital system out of a digital component library. Those components are then getting transferred to synthesizable VHDL code. For this purpose a dynamic script is needed to generate the custom VHDL code at run time. The proposed language to meet this need is JavaScript. We also propose the use of object serialization in Java to convert the libraries into a sequence of bits so that it can be stored on a server. So it is possible to access the libraries for any user who is online. In the next sections, we discuss related work concerning parameterized modules for VHDL languages. We also describe a state-of-the-art tool for VHDL code generation, the Simulink® HDL Coder. Then we will introduce our tool, the DiaHDL, describing the difference in the used library language and working environment compared to the Simulink Coder. Finally we highlight the advantages of our tool to the competitor. . 2. RELATED WORK 2.1. Library of Parameterized Modules (LPM) The LPM standard is an extension to the Electronic Design Interface Format (EDIF), which is an industrystandard syntax for transferring designs between the tools of different EDA vendors. The LPM provides an architecture-independent library of logic functions or modules that are parameterized to achieve scalability and adaptability without sacrificing efficiency [2]. Designer can vary the parameters to represent a wide variety of logic functions. The LPM is supported by most EDA tool vendors, for an example by Altera®. The LPM in Altera presently contains 25 functions with the following features: 1. Architecture-independent design entry 2. Efficient design mapping
3. Tool-independent design entry 4. Specification of a complete design Each of those functions can be parameterized. For example, the lpm_counter function allows the user to create counters with a bit width ranging from 1bit to 256 bits [3].
2. DiaHDL Visualization Tool, that converts the component diagram to VHDL code. This tool provides a graphical user interface that allows the user to select a component, customize their parameters and generate the VHDL code.
3.1. JHO File Library 2.2. Simulink HDLCoder Simulink HDL Coder is a toolbox extension from The MathWorks® and Mentor Graphics® Corporation to generate HDL code from Simulink models, Embedded MATLAB code, and Stateflow charts. Simulink HDL Coder generates bit-true, cycleaccurate, synthesizable Verilog and VHDL code and test benches. Its can generate Verilog code that complies with IEEE 1364-2001 standard and VHDL code that complies with IEEE 1076 standard [4]. Simulink HDL Coder allows us to: 1. Select from multiple HDL architectural implementations for commonly used block. 2. Select the subsystem for HDL code generation 3. Reuse existing IP HDL code (with EDA Simulator link products) 4. Generate simulation and synthesis scripts. Simulink HDL Coder also generates HDL test benches that help us verify the generated HDL code using HDL simulation tools.
3. DiaHDL TOOL STRUCTURE DiaHDL is a tool which generated synthesizable VHDL code out of a component diagram. This tool was developed under the constraint that any user who is online is able to use the tool. The design can be stored on a password-protected server so that coworkers can access the design at any time and any place. Figure 1 shows the whole structure of DiaHDL. DiaHDL allows users to interactively explore the component libraries, build a digital system out of those component libraries, and generate a synthesizable VHDL code.
The architecture of the JHO File Library contains Parameterized VHDL Code, JavaScript, Entity Description, and Custom Configuration. The translation from VHDL code to parameterized VHDL code is straight forward. On every section that can be customized we need to insert notation % before and after each parameter. The following example shows the translation from VHDL generic code to parameterized VHDL code. generic ( BIT_WIDTH: INTEGER := 8 );
We need to change “8” into %BIT_WIDTH% so that the value of bit width can be customized at visualization tool. generic ( BIT_WIDTH: INTEGER := %BIT_WIDTH% );
The second example shows how to create parameterized VHDL code for FIR Filter coefficients. The generic code looks like the following: constant coef: array_coef := (0,3,6,0,-3);
We need to change all coefficients into one parameter. In our case we name this parameter %COEF%. The parameterized VHDL code looks like the following: constant coef: array_coef := (%COEF%);
After creating parameterized VHDL code, we need to create the custom configuration. This is nothing but the list of all parameters used in the parameterized VHDL code. For the above mentioned examples we would get the following custom configuration: [0] BIT WIDTH: Integer [1] COEFFICIENT: Integer List
Fig. 1 DiaHDL structure
DiaHDL was implemented using Java under web environment. It is composed of two different modules interacting together: 1. JHO File Library, which contains parameterized VHDL code and JavaScript to create VHDL code dynamically. This file is stored in Java object serialization format.
Scripting language is needed to connect the parameterized VHDL code and the custom configuration. There are many scripting language that can be used to process this. But among existing scripting languages, we have chosen the JavaScript Language because of its ability to work with the Visualization Tool programmed in Java. The
following JavaScript code provides this connection for the example of the parameterized bitwidth.
Figure 2 shows the complete library of the JHO Structures and generation of the JHO File Library using the marshalling process.
templates.put(“BIT_WIDTH”, properties.get(0).getValue());
3.2. DiaHDL Visualization Tool As you can see in here, if this script is executed then the parameter BIT_WIDTH in the VHDL code will be replaced by the value of the custom configuration, which is indexed by [0] in this example. The JavaScript to process the coefficients of the FIR filter is a bit different. With our JavaScript users are able to directly copying the filter coefficients from MATLAB® Filter Toolbox to custom configuration, without taking care of formatting. JavaScript converts automatically floating point representation to integer values.
DiaHDL Visualization Tool is a module which is designed to convert a designed component diagram to VHDL code. Conversion is done by running the JavaScript which takes the user parameters out of the configurations structures that is part of JHO file library. Generated VHDL code depends on the parameter that is given by the user. Fig. 3 shows the whole structure of DiaHDL Visualization Tool. The unmarshalling technique is required to read the JHO file library. Unmarshalling is method for extracting a data structure from a series of bytes [6].
var coefs = new Array(); var str = properties.get(1).getValues(); coefs = str.split(“,”); for (var i in coefs) { coefs[i] = parseInt(coefs[i]); } templates.put(“COEF”, coefs.join(“,”));
The first three lines are used to get value of the custom configuration, which is indexed by [1] in this example. parseInt function is used to convert each value of coefficient into integer value. And the last line replaces the COEF with the values of all coefficients as integer values. Fig. 3 DiaHDL Visualization Tool
Entity Description and Custom Configuration is required by the Visualization Tool to create the image of a component diagram. The following code shows an Entity Description of a FIR Filter:
port ( Clock : IN std_logic; Reset : IN std_logic; FilterIN : IN std_logic_vector(BIT_WIDTH-1 downto 0); FilterOUT : OUT std_logic_vector(OUT_WIDTH-1 downto 0) );
Fig. 2 Generation of the JHO File Library
Finally the parameterized VHDL code, JavaScript, entity description, and custom configuration need to be packed and stored as a JHO File Library. So we developed a Java class, named JHO Structures, which contains the complete library, because Java requires a class for object serialization. Then marshalling concept is used to create the JHO File Library [5].
Fig. 4 shows the component diagram of that entity description, displayed with DiaHDL Visualization Tool. The Custom Configuration is displayed on a different window within the tool.
REFERENCES
Fig. 4 Component diagram of FIR filter DiaHDL Visualization Tool also provides signals which are used to connect different component diagrams. Name and bit width of the signals can be customized by the user. Fig. 5 show us examples of signal at the DiaHDL Visualization Tool.
Fig. 5 Signals in DiaHDL
VHDL code can be generated based on digital system design provided by user. DiaHDL Visualization Tool will execute the JavaScript for each component diagram and analyze the system design which may consist of many component diagrams and signals. The JavaScript for each component diagram will read all the configuration values and apply those values into the parameterized VHDL code. Finally the tool provides the VHDL code of the complete system design consisting of code for the top-level entity and all the components.
4. CONCLUSIONS We presented in this paper a tool generating behavioral VHDL code from graphical representation of a digital system. We have implemented this tool in Java. Similar industrial tools are available, but to our best knowledge they cannot be used online. The advantage of our tool is that each member of a design project can have access to the design at any time and any place. We believe our tool provides a friendly graphical user interface that can be used effectively in simulation and synthesis of digital circuits.
[1] IEEE Standard 1076-1993, IEEE Standard Description Language Based on the VHDL Hardware Description Language, 1993. [2] LPM Quick Reference Guide, December 1996. [3] Quartus II, Altera Tools, http://www.altera.com/ products/software/quartus-ii/, 2009. [4] The MathWorks Inc. Simulink hdl coder. Technical report, The MathWorks Inc., September 2006. [5] L. Opyrchal and A. Prakash. Efficient Object Serialization in Java, ICDCS 99 Workshop on Middleware, June 1999. [6] Javadoc Tool Home Page http://java.sun.com/ j2se/javadoc/
