Zero-voltage-switching technique in high-frequency off ... - IEEE Xplore

ZERO-VOLTAGE-SWITCHING TECHNIQUE IN HIGH-FREQUENCY OFF-LINE CONVERTERS'

Milan M. Jovanovic, Wojciech A. Tabisz, and Fred C. L e e

Virginia Power Electronics Center Department of Electrical Engineering Virginia Polytechnic Institute & State University Blacksburg, Virginia 24061

ing properties, the load range is rather limited. Full-wave mode of operation, which can be achieved by adding a diode in series with each switch (71. is not practical [6.7] because the series diode hinders the transfer of charge stored in the transistor's output capacitance to the external circuits. Thus, the MOSFETs no longer achieve a true zero-voltage switching.

ABSTRACT The characteristics and limitations o f the half-bridge zero-voltageswitclied (ZVS) quasi-resonant converters (QRCs) are described. A novel multi-resonant switch concept i s proposed for the half-bridge topology to improve the ZVS-QRC's load range. Experimental results for 300 75 W zero-voltage-switched quasi-resonant and multi-resonant converters operating in the frequency range of 2 MHz to 8 MHz are presented.

In ZVS-QRCs the freewheeling diodes are operated under zerocurrent-switching conditions, Since the junction voltages are abruptly changed during switching, the junction capacitances tend to oscillate with the resonant inductance resulting in high-frequency ringing and power dissipation.

v,

The performances of ZVS-QRCs can be drastically improved by the introduction of the multi-resonant technique [8,9]. This technique enables both the active switches (power MOSFETs) and the passive switches (diodes) to operate with zero-voltage switching. In zerovoltage-switched multi-resonant Converters (ZVS-MRCs), junction capacitances of all semiconductor devices are utilized to form a multi-resonant network. This technique minimizes parasitic oscillations of all forms and is capable of achieving zero-voltage switching even at no load.

I. INTRODUCTION High-frequency operation in off-line power conversion offers higher power density and faster transient response. To operate at higher frequency, it is necessary to minimize switching losses. The zerocurrent-switching technique [ I ] has been demonstrated to achieve high-frequency, high-efficiency operation for quasi-resonant off-line converters [2]-[5]. In the zero-current-switched quasi-resonant converters (ZCS-QRCs), the current of the transistor is shaped by a resonant network, so that it is reduced to zero prior to turn-off t o eliminate turn-off losses. Although ZCS-QRCs can operate at relatively high frequencies, several limitations exist. The maximum switching frequency is limited to 1-2 MHz by the undesired capacitive turn-on loss. Here the energy stored in the junction capacitance of the MOSFET is dissipated into the device during turn-on. Furthermore, the switching frequency for lighter loads is significantly reduced, resulting in lower crossover frequency and slower transient response. This is particularly true when the converter is operated in half-wave mode [I], [4], [5]. The frequency range and transient response can be improved by operating a converter in full-wave mode [ I ] , [ 5 ] . However, full-wave mode is difficult to implement at high frequencies due t o the slow recovery of the MOSFET's body diode [5].

This paper presents analysis, design, and experimental results of two half-bridge off-line converters implemented with both ZVS quasi-resonant and ZVS multi-resonant techniques The merits and limitations of these two techniques are discussed and the comparisons are made with respect to efficiency, load range, and operating frequency range 11. HALF-BRIDGE ZERO-VOLTAGE-SWITCHED QUASI-RESONANT CONVERTER

The circuit diagram of a half-bridge ZVS-QRC is shown in Fig. 1. Resonant capacitors C, and C, represent the output capacitances of the MOSFET switches, whereas D, and D, represent the body diodes of the switches. L is the total resonant inductance It consists of the transformer leakage inductance and external inductance which can be added t o increase the total value of L.

The zero-voltage-switching (ZVS) technique [SI is proposed t o overcome the limitations of the ZCS technique. Switching turn-on losses of the power switches are eliminated by shaping the transistor's voltage waveform so that the voltage reduces to zero prior to turn-on. This enables the zero-voltage-switched quasi-resonant converters (ZVS-QRCs) to operate at approximately 10 MHz [7]. Contrary to the ZCS-QRCs. the switching frequency of ZVS-QRCs is increased at light loads. Thus, it is possible to implement converters with high crossover frequencies and much improved dynamic responses One common drawback of the ZVS technique when applied to single-ended converter topologies is the inherent high voltage stress across the switching transistor. Therefore, practical converter topologies for off-line applications are those that employ multiple switches such as push-pull and bridge-type topologies where the voltage across the off switch is automatically clamped by the conduction of its complementary switch. The halfbridge ZVS-QRC topology has been chosen t o demonstrate the feasibility of off-line high-frequency operation The converter is operated in the half-wave mode To maintain zero-voltage switch-

To simplify the analysis it is assumed that: a)

the output filter inductance is sufficiently large t o be approximated by a current source with a value equal to output current

I, ; b)

the voltage drop across switches is negligible

the

conducting

semiconductor

~

c)

the switching times of the transistors are zero,

d)

switches Q, and Q, are identical so that C, = C, = C

A. Principle of Operation Figure 2 shows equivalent circuits of the HB ZVS-QRC in the four topological stages. Circuit waveforms are shown in Fig 3. At the end of the conduction period of transistor Q1. the voltage across C, is zero, whereas the voltage across C, is equal to supply voltage V, . The output current I, flows through D,, and the primary current is /,/N. where N is the transformer's turns ratio.

This work was supported by Digital Equipment Corporation and Virginia Center for Innovative Technology. *

23 CH2504-9/88/0000-0023 $1.00 0 1988 IEEE

T

vs

Fig. 1.

Half-bridge zero-voltage-switched converter (HI3 ZVS-QRC)

Fig. 2.

Equivalent circuit of the H 6 ZVS-QRC topological stages: a) capacitor-charging stage [To, TI] b) resonant stage IT,, T2J c) inductor-discharging stage [T2. T.J d) constant-current stage [T3, TJ

quasi-resonant

in four

Fig. 3.

Capacitor-charging stage [To, T,], Fig.2.a. At t = To (Fig. 3). transistor Q1 is turned off and the circuit enters the capacitor-charging stage, shown in Fig. 2.a. After Q1 is turned off, constant primary current I0/N is diverted from Q1 to C,. As a result, voltage across C, increases linearly, whereas voltage across C, decreases at the same rate. The total load current still flows through D R l . This stage terminates at t=T, when voltage vc2 decreases to V,q/2.

Circuit waveforms of the Hi3 ZVS-QRC. Note that the switch voltages (vel, vc2) are clamped t o V,. The dashed portion of the sinusoidal switch voltages indicates how the voltages would look like if there were no clamping.

v c l ( t ) seco "s IoZn sin . r 2 N

Resonant stage [ T I , T2J, Fig.2.b At t=Tl. the transformer's primary winding voltage becomes negative and rectifier DR2 begins to conduct. Now, capacitors C, and C, and inductor L form a series-resonant circuit. The voltage vc2 continues to decrease below Vs/2 in a resonant manner. Since a negative voltage is applied across L , the primary current starts t o decrease. To maintain constant output current I,, both rectifiers D,, and DR2 conduct simultaneously and the transformer secondary is shorted as shown in Fig. 2.b. Equations describing the switch voltages and primary current are:

~ ,~

VS Iozn vC2(t)seco sin mot 2

N

~

t

,

IO

Ipr,m(t) = 7cos mot

I

where w 0 = I/= is the resonant frequency and Zn = the characteristic impedance.

24

(1.a) (1.b) (1.c) is

This stage ends when voltage vcl becomes Vs and voltage vc2 becomes zero. Subsequently, transistor Q2 should be turned on to achieve a lossless turn-on. From Eq. (1.b) it follows that a zerovoltage-switching condition requires that

I,z

>vs2

N n-

or, in the normalized form, M =

where IONis the normalized output current Inductor-discharging stage

IT2, T,J,

Fig. 2.c.

When vc2 becomes zero at t = T2 (Fig. 3), antiparallel diode D, starts conducting. A constant voltage (-Vs/P) is applied across L and the primary current decreases linearly Transistor Q2 should be turned on before the primary current begins to flow in the negative direction at t = T'3. The stage terminates at t=T3 when ip,,, becomes - lo/N. Constant-current stage [T3,

fcon

Td, Flg. 2.d.

f0

At t = T3, rectifier D ,, turns off and output current Io flows through DR2. Therefore, the primary current of lo/N flows through switch Q2 . Capacitor voltage vc2 is zero, while vcl is equal to Vs. The stage ends when Q2 is turned off by the gate-drive circuit which initializes a new conversion cycle with the same sequence of operations.

Fig. 4.

DC voltage-conversion ratio of the HE ZVS-QRC as a function of the normalized conversion frequency.

Typically, the input data for the design of a converter include: - input voltage range Vyln, VFax - output voltage V, - output current range /PIn,/Pax - minimum conversion frequency

The analytical expression for the dc voltage-conversion ratio is [I21

Ti,"

where

Using Eqs. (6.a)-(6.c) and the input data, it is possible to determine values for the resonant components (C, = C, = C, L ) . For today's devices, CO,, is in the range of 35-500 pF (at Vd,=25 V) with lower values corresponding to high-voltage devices (2200 V) and, consequently, with a relatively high on-resistance [ I O ] .

(4)

(5)

Solving Eqs. (6.a)-(6.c), the following conditions for resonant-tank components can be found.

and f,,, is the conversion frequency. fo is the resonant frequency, Vo is the output voltage, Vs is the supply voltage, Z, is the characteristic impedance, R, is the load resistance, and r is the normalized load resistance.

1 I,"" C < 2nf0 N

I Vs

Figure 4 shows the dc voltage-conversion ratio as a function of the conversion frequency with the normalized load resistance as the running parameter. Equations (7.a) and (7.b) are represented graphically in Figs. 5 and 6, which show the maximum resonant capacitor, ,C , and minimum inductance L,,,, respectively, as functions of the input voltage V,. assuming a constant resonant frequency, fo = 5 MHz.

B. Design Considerations Since the HB ZVS-QRC uses the junction capacitance of the MOSFET as the resonant component, the minimum value of the resonant capacitance is limited by the availability of devices with the desired characteristics. In fact, certain trade-offs have to be made regarding conversion frequency, load range and efficiency.

From Figs. 5 and 6, the following can be observed: for a given minimum primary current (/#In IN). CmaXdecreases as the input voltage increases, for a fixed input voltage, ,,C , decreases as the minimum primary current decreases, relatively large resonant inductance is needed to accomplish zero-voltage switching with a lighter load

The design of the resonant tank is based on the following equations.

From Eq. (7 a ) , it can be observed that a higher resonant frequency requires a smaller resonant capacitance. Since the resonant capacitance is the output capacitance of the MOSFET, the choices for the value of C are limited. Figure 7 shows the dependance of the output capacitance on the drain-to-source voltage for four IRF devices most likely to be used in off-line conversion. Figure 8 shows superimposed plots of Figs. 5 and 7. It can be observed that for devices with relatively high output capacitance (such as IRF 620 and IRF 720) it is necessary to have a higher minimum primary

z,=JL/'Lc

The first equation (Eq. (6.a)) defines conditions for zero-voltage switching, while the other two define the characteristic impedance and the resonant frequency, respectively.

25

0

100

300

200

400

500

vos [ V I

0

100

300

200

400

500

Output capacitance CO,, of four high-voltage IRF devices as a function of drain-to-source voltage V,,

Fig. 7. vs [ V I

Fig. 5.

Maximum resonant capacitance , ,C , for HB ZVS-QRC as a function of input voltage V, for four primary currents lo/N and constant resonant frequency f, = 5 MHz

I,

-

5MHZ

7 0

200

100

300

v,

Fig. 8.

400

500

[VI

Superimposed plots of output capacitance Cess (Fig. 7) and maximum resonant capacitance CmaX(Fig. 5) for f, = 5 MHz

C. Design Procedure Fig. 6.

Minimum primary current /(;‘“/I%’ can be kept at a desired level either by increasing /(;In and/or by decreasing the turns ratio, N. However, increasing /Fin results in a reduced load range, whereas reducing N increases the conduction loss of the switches. Moreover, from the dc voltage-conversion characteristics in Fig. 4, a low turns ratio also decreases the load range. Therefore, it is recommended that the turns ratio of the transformer be maximized.

Minimum resonant inductance L,,, for HB ZVS-QRC as a function of input voltage V, for four primary currents /,/N and constant resonant frequency f,=5 MHz

current to accomplish zero-voltage-switching (z 0.65 A for IRF 720 and Y 1 A for IRF 620 for V!Jax=200 V). For the low-capacitance devices, such as IRF 610 and IRF 710, a smaller minimum primary current is required (for example, about 0.25 A for IRF 710 at ,pax = 400 V). If the resonant frequency is chosen at 2 MHz. the minimum primary current is 0.1 A for a 400-V operation using IRF 710. If the resonant frequency is chosen at 10 MHz, at least 0.5 A of the primary current is required for the same operating condition.

The maximum turns ratio of the transformer is determined by “ax

where D,,, 0.7 to 0.9.

26

= T$”/(T,,+

= Dmin-

VY’ 2Vn

(8)

Tp;”) is the minimum duty cycle, typically

I

1

vco Fig. 9.

S T E E R I N G LOGIC

ITaX ppnm ax- N

=V y x

Following the design procedure outlined in the preceding section, a 75W HB ZVS-QRC operating with a 300+50 V input, 5 V output, and with the minimum conversion frequency of I MHz was implemented. The power stage, shown in Fig. I , consists of the following components: Q1,Q2 -IRF 710 (International Rectifier); D,, D2 -internal body diode of IRF 710; C,,C, -junction capacitance of IRF 710, C;?,= 50 pF @ 25 V; -0.1 pF/400 V metalized polyester; C, -core: TDK LP 32/13 (material H,,,) TR primary: 16 turns of 60140 Litz wire (equiv. AWG # 22). secondary: 1 turn 135/35 Litz wire (equiv. AWG # 15), center-tapped L -leakage inductance of the transformer N 16 pH; D,,,DR2 -60CNQ045 (International Rectifier); L, --IpH @ 15 A, Magnetics MPP core 55125 with 6 turns of magnet wire AWG # 18;

(10)

To obtain the widest possible load range it is necessary to select MOSFETs with a current and voltage rating according to Eqs. (9) and (IO) and the smallest possible output capacitance, C,,=C'. occurs at low line and full load,

= 2"-

I

D. Experimental Results

Since the voltage across the nonconducting MOSFET switch is clamped at the supply voltage, the maximum drain-to-source voltage is

M =,,M ,

STRGE 5

For low output voltages the above design equations should include the effect of the voltage drop on the rectifiers (VDR) by replacing Vo with V', = Vo t, V , .

(9)

~

Minimum conversion frequency i.e., for

OUTPUT

Circuit diagram of the two-channel isolated gate drive

Once the turns ratio N' is chosen (* denotes a design value), the maximum primary current is

?;v

I

VO Vyln

and

C,

-3 3 p F x 3, Z5U multilayer chip capacitors.

Also, to reduce ringings across the rectifiers at turn-off, an R-C snubber is used (R,= I O @ C, = 1.5 nF). For IRF 710 the calculated C;?, at Vpax/2 (the converter enters the resonant stage when vcl becomes Vs/2) is approximately 20 pF. However, to account for stray capacitance between the drain of the lower switch and ground, it is assumed that the design value is C*=30 pF. The estimated resonant frequency is f0=5.3 MHz.

Substituting Eqs. (11) and (12) into Eq. (3) and solving the resulting transcendent equation the value of resonant inductor L' can be obtained. The maximum value of the normalized load resistance at which zero-voltage is achieved is given by

The power stage was driven using a two-channel, isolated gate drive, shown in Fig. 9. The drive consists of the voltage-controlled oscillator (VCO), steering logic and output stages. Control voltage Vc sets the frequency of the VCO [7] which generates constant offtime pulses distributed to the two output stages by the steering logic. A small inductor in series with the collector of each driver's output transistor improves the turn-on speed. The isolation transformers are wound bifilarly to minimize the leakage inductance and their outputs are directly soldered to the gate and source terminals of the MOSFETs with minimum lead length. When driving IRF 710, the drive can operate up to 12 MHz, dissipating around 3 W and having voltage rise and fall slopes of approximately 0.5 V/ns and 1 V/ns, respectively

Thus, the minimum regulated output current, determined by rmax, is

and occurs at the maximum conversion frequency

27

20

35

50

65

80

Po [WI

Fig. I O . Measured efficiency of the HB ZVS-QRC power stage

as a function of the output power

Fig. 12. Gate drive VGs2, prlmary current Ipnm, switch voltage VDs2, and rectifier voltage VDR2 waveforms of the U6 ZVS-QRC at full power (5 VI15 A). lnput voltag? V, =300 V, conversion freauencv 6-..=2 MHz.

W,

= 250W

the rectifiers and the resonant inductor. As shown in Fig. 12, when the primary switches conduct, the primary current (Iprim ) is oscillatory instead of being constant ( l o p ) . At higher frequencies ( ~ 4 M h ' z )the primary switches can be turned off at an instantaneous current below the average value of lop." This accounts for a, loss of zero-voltage switching at higher output currents than predkted.

0

20

35 Po I W l

Finally, it should be pointed out that the transformer's size is larger than necessary. The main reason for selecting a relatively large core is that for zero-voltage switching a large leakage inductance is required which calls for a significant separation between the primary and secondary windings. At heavy loads the major portion of the transformer loss occurs in the secondary windings, whereas the core loss is dominant at light loads (higher frequencies).

Flg. 11. Measured conversion frequency of the U B ZVS-QRC power stage as a function of the output power Figures 10 and 11 show the measured efficiency and conversion frequency of the breadboarded converter as functions of the output power. It can be seen that an efficiency greater than 80% was achieved at low line, At high line the efficiency drops slightly below 80% due to an increased core loss of the transformer, and turn-off losses in the rectifiers and power switches. From Fig. 10 it can be also seen that the load range is rather limited. For high line the converter operates with zero-voltage-switching from full load down to 70% of full load (10.5 A), whereas, at low line the load range extends to 40% (6 A). It is possible to operate the converter at lighter loads. However, the converter will operate without zerovoltage-switching and, consequently, with lower efficiency.

111. HALF-BRIDGE ZERO-VOLTAGE-SWITCHED MULTI-RESONANT CONVERTER All practical ZVS-QRCs suffer from the undesired parasitic oscillations between the resonant inductor and junction capacitance of the rectifier [ i l l . These oscillations not only limit the converter's load range but also adversely affect the dc voltage-conversion-ratio characteristics in such a way that the conversion ratio exhibits positive slopes in certain regions (only negative slopes are desirable). These positive-slope characteristics can result in loop instability. To assure stable operation it is necessary to suppress the parasitic oscillations. This oRen is achieved by using dissipative snubbers across the rectifiers. This solution can result in a significant reduction of efficiency, especially at high-frequency operation.

According to Eq. (14), the predicted minimum load current of the converter is around 40% (6 A) of full load. The discrepancy between the prediction (6 A) and the experimental result (10.5 A) is primarily due to the parasitic oscillation between the junction capacitance of

28

"GS2

"c 1 vc

I1 I . _ _ '

I

I

1

8

'

' $ :

,

!

Fig. 13. Half-bridge zero-voltage-switched converter (HB ZYS-MRC)

m

1

I I

,

I 1 I

I I

I

I

I

1

h

,

I

i

1

t

multi-resonant

1

I

bl

I)

r

I

"2

I

COP,

Fig. 14. Equivalent circuit of the H E ZVS-MRC in four topological stages: a) switch-resonant stage [70, T , ] 5 ) rectifier-capacitor-discharging stage [TI. 721 c) inductor-discharging stage [T2, T3] d) rectifier-resonant stage [T3, TJ

A novel, multi-resonant-switch concept [8] was proposed recently to alleviate the aforementioned difficulties The proposed technique allows the rectifier's junction capacitance to resonate in a controlled fashion with the resonant inductor. To obtain desired resonant frequency, an external capacitance can be added in parallel with the rectifier if the diode junction capacitance is not sufficiently large.

Fig. 15. Circuit waveforms of the H B ZVS-MRC Switch-resonant stage [To, TJ, Fig.14.a. and inductance L resoWhen transistor Q1 is on, capacitance C, nate. At t = To, transistor Ql is turned off. Since rectifier D,, is still reverse biased, the equivalent circuit of the converter is as shown in Fig. 14.a. During this stage, capacitance Cl is being charged in a resonant manner toward the supply voltage, whereas C, is being discharged. The stage terminates a i ! = T , when voltage vc2 becomes zero. Subsequently. transistor Q 2 should be switched on to achieve a lossless turn-on.

The circuit diagram of a half-bridge zero-voltage-switched multiresonant converter (HB ZVS-MRC) is shown in Fig. 13. It differs from the diagram of the HB ZVS-QRC only by showing the capacitors across the rectifiers. These capacitors represent the junction capacitance of the rectifiers and any externally added capacitance. A. Princiole o f ODeration

Rectifier-capacitor discharging stage [TI,

There are several possible modes of operation of the HB ZVS-MRC [12]. The mode of operation which occurs under the most input and load conditions is described below. For ease Of explanation, the same assumptions made in Section 11 are employed. Figure 14 shows the equivalent circuit of the HB ZVS-MRC in the four topological stages, whereas Fig. 15. shows typical waveforms.

T,], Fig. 14.b.

In this stage, C, continues i o resonate with L. Due to a negative voltage across L, the primary current decreases and C,, continues to discharge, The stage terminates at t = T 2 when the capacitor voltage across C, becomes zero and diode D,, becomes forward biased.

29

M=

1

0

I

0

2.5

,I

5

1 7.5

1u

XC

Fig. 17. Normalized primary peak current of the HB ZVS-MRC as a function of X ,

Rectifier-resonant stage IT3,

Td, Fig. 14.d.

At t = T3, C , starts resonating with inductance L. This stage ends when switch Q2 is turned off and a new conversion cycle is initiated. If switch QP stays on for a longer time, the rectifier voltage may oscillate for several cycles. In this particular mode of operation the dc voltage-conversion ratio shows undesired positive-slope characteristics. To avoid this mode of operation it is necessary to limit the on-time duration (i.e., minimum switching frequency) to approximately one half of the resonant period of the rectifier voltage. Figure 16 shows the dc voltage-conversion ratio as a function of the conversion frequency. These characteristics must be plotted with two parameters specified: lo,,, = PZ,Io/NVS - the normalized output - the ratio of the capacitance across current, and X , = 2C,,/(N2C) the rectifiers reflected into the primary (CDR/(N/2)2)and the resonant capacitance of the primary (2C). It should be pointed out that for ZVS-MRCs it is difficult to plot the dc voltage-conversion ratio with the normalized output resistance (r=N2RL/Z,) as a running parameter. 0 '4

1:2

08

1.6

Examining Fig. 16, it is found that the conversion frequency must be higher than a given frequency to ensure that the operatirg point of the converter does not go into the positive-slope region This limits the allowed operating region to the right of the dashed line in Fig 16

Icon

C (b)

B. Design Guidelines Fig. 16. DC voltage-conversion ratio of the HB ZVS-MRC as a function of the normalized conversion frequency: a) X , = 5, b) X , = 10. Normalized output current ION = 2Z,IO/NVs and X , = 2CD,/N2C are parameters. Note that X , represents the ratio of the capacitance across the rectifiers reflected into the primary (C,,/(N/2)2 and the resonant capacitance o f t h e primary (2C).

It is not possible to obtain explicit closed-form solutions of the equations describing the operation of the ZVS-MRCs. Therefore, the design of the HB ZVS-MRC is mainly based on the numerically calculated dc voltage-conversion-ratio characteristics shown in Fig. 16. The design guidelines generally follow those of HB ZVS-QRC. In fact, the guidelines for selecting the transformer turns ratio and the resonant capacitance are identical. To determine the values of resonant inductor L and capacitance CDF, it is necessary to use the dc voltage-conversion ratio characteristics plotted for various X,. Capacitance C*,, is determined by selecting X,, whereas inductance L" is determined by selecting ION at low line and full load, i.e., 2Z,/gaX/N'Vy1n , Finally, the primary switches are selected according to the voltage and current ratings, and the output capacitance. While the voltage across the nonconducting switch in the HB ZVS-MRC is the same as in the HE ZVS-QRC. the peak current in the HB ZVS-MRC (Fig. 15) is somewhat higher than that in the HB ZVS-QRC (Fig. 3). Figure 17 shows the normalized peak primary current in a HB ZVS-MRC as a function of X,. The maximum peak current occurs for /MX = 2Zn/MX/N'V~1n.

/w=

Inductor-discharging stage [T2,TJ, Fig. 14.c. During this stage, both rectifiers conduct so that the primary voltage is zero and a negative voltage is applied to L. As a result, the primary current decreases with a constant rate. The stage terminates at t = T , when the primary current becomes -l0/N and rectifier D,, ceases to conduct.

30

0

3

Fig. 19. Measured converslon frequency of the H 6 ZVS-MRC power stage as a function of the output power

Fig. 18. Measured efficiency of the H 6 ZVS-MRC power stage as a function of the output power

Fig. 21. Gate drive VGS2,primary current,,,,,/ switch voltage VDS2,and rectifier voltage V, waveforms of the H 6 ZVS-MRC at no load (5 VI0 A). lnput voltage V s = 3 0 0 V, conversion frequency fc0,=8 MHz. scale: V,, - 2OVldiv; V,, - 5OVldiv; l,,,, - O.5Aldiv; V,, - 5Vldiv.

Fig. 20. Gate drive VGS2,primary current lprrm, switch voltage V,,, and rectifier voltage VDR2 waveforms of the H 6 ZVS-MRC at full power (5 V l f 5 A). lnput voltage V,=300 V, conversion frequency f&=2 MHz. scale: V,, - 20Vldiv; V,, - 50Vldiv; Ipnm - 1Aldiv; V,, - 10VldiV.

31

A HB ZVS-MRC is designed with the same specifications as the previous breadboarded HB ZVS-QRC (Po=75 W, Vo=5 V, Vs =300 V+50 V, fcon >I MHz). Therefore, the turns ratio of the transformer and the resonant capacitance for the HB ZVS-MRC are assumed the same as for the HB ZVS-QRC (N*=16, C'=30 pF) Using the available plot of the dc voltage-conversion-ratio for X , = 5 , it follows that CDR=20 nF. Also, selecting =5, the resonant inductor value is 25 pH. From Fig. 17, for X,=5 and =5. l F ~ $ / ( l ~ a x / N ' ) ~ 1 . is 4 4obtained. Since 1,44*(15A)/16= 1.35A the IRF 710s are selected for the primary switches. Estimated resonant frequency of the converter is f0y4 MHz. From Fig. 16.a the minimum conversion frequency (which occurs for /mX=55) is around 2 MHz

lm"

lFJA=

The HB ZVS-MRC has a potential to operate at yet higher frequencies (over 10 MHz) Practically, the main obstacle in achieving this is the relatively high output capacitance of today's available MOSFET devices and a lack of adequate core materials for very high-frequency power transformers.

loN=lmx

REFERENCES

[l]

K. Liu. R Oruganti. F. C. Lee, "Quasi-Resonant Converters - Topologies and Characteristics," IEEE Trans. Power Electronics, vol. PE-2, No. 1. pp. 62-74, January 1987.

[2]

P. Vinciarelli, "Forward Converter Switching at Zero Current." U.S. Pat. 4,415,959, 1983.

[3]

A. Heyman, "Low-Profile High-Frequency Off-Line Quasi-Rescnant Converter,'' / E € € Applied Power Electronics Conference Proceedings, pp.157-165, 1987.

B. Experimental Results The power stage of the HB ZVS-MRC. Fig. 13, consists of the same components as that of the experimental HB ZVS-QRC except that a 20 nF ( 3 ~ 6 . 8nF) NPO ceramic chip capacitor is added in parallel to each rectifier, and the transformer is rewound to increase the leakage inductance to ~ 2 pH. 5 The measured efficiency and conversion frequency are shown in Figs. 18 and 19. Compared to the HB ZVS-QRC, the efficiency of the HB ZVS-MRC is slightly lower. This can be attributed to a higher rms value of the primary and secondary currents, loss in the capacitors across the rectifiers, and loss due to an increased transformer leakage. As can be seen, the converter operates with zero-voltage switching in the load range from 10% to 100% The conversion frequency varies from 1.5 MHz to slightly above 8 MHz. Figure 20 shows typical oscillograms of the converter at full load It is also possible to operate the converter with no load, as shown in Fig. 21. Even though zero-voltage switching is lost. the switches are turned on with a relatively low voltage.

[4] D. C Hopkins, M M. Jovanovic, F. C Lee, F. W. Stf.phenson, "Two-Megahertz Off-Line Hybridized Quasi-Resorwit Converter,'' / E € € Applied Power Electronics Conference Proceedings, pp, 105-114, 1987.

[SI

M M. Jovanovic, D. C. Hopkins, F. C. Lee, "Design Aspects for High-Frequency Off-Line Quasi-Resonant Converters," High Frequency Power Conversion Conference Proceedings, pp. 83-97, 1987.

[6]

K H. Liu. F. C. Lee, "Zero-Voltage Switching Technique In DC!DC Converters, IEEE Power Electronics Specialists Conference Record. pp, 58-70, 1986.

IV. CONCLUSIONS The zero-voltage-switching technique is implemented with the half-bridge topology for high-frequency off-line applications. Two zero-voltage-switching-circuit techniques are discussed in this paper on? employs the quasi-resonant technique, the other employs a novei multi-resonant technique. In ZVS-QRCs. the power switches are operated under zero-voltage switching. Nonetheless, the rectifier diodes are switched with an abrupt change in voltage which induces high-frequency ringings and power dissipation The ZVS-QRCs also exhibit limited load range. The dc characteristics of a half-bridge ZVS-QRC and a ZVS-MRC are analyzed, the performances of the two converters are compared, and design procedures are outlined.

"

171

W. A. Tabisz, P. Gradzki, F.C. Lee, "Zero-Voltage-Switched Quasi-Resonant Duck an2 Flyback Converters - Experimental Results at IOMHz," lEEE Power Electronics Specialists Conference Record, pp, 404-413, 1987.

[a]

W. A. Tabisz, F.C Lee,

"Application of a Novel, Multi-Resonant Sw/tch in H g h Frequency DCIDC Converters," VPEC Power Electronics Seminar Proceedings. Virginia P olytechnic lnstitufe and State University, Blacks6urg, Virginia, pp. 65-71, 1987.

A breadboarded HB ZVS-QRC is presented which operates from a 300k50 V input with maximum output power of 75 W (5 V/15 A) ana an efficiency of 83.5% at low line and full load and 73.2% at high line and full load The converter operates with zero-voltage switching only in a relatively limited load range, from full load to about 55% of full load at nominal line voltage. The conversion frequency necessary to regulate the output in the above input voltage and load range varies from 1 MHz to 4.2 MHz

191

W.A Tabisz, F. C. Lee,

"Multi-Resonant Switches - A Novel Approach t o lmprove Performances of High-Frequency Quasi-Resonant Converters, to b e published a t the 19th Power Electronics Specialists Conference, A p r i l 1988, Kyoto, Japan. "

In ZVS-MRCs, all semiconductor devices are operated with no abrupt changes of the voltage across the devices. This technique permits utilization of junction capacitances of all semiconductor devices and the transformer leakage inductance to form a multiple-resonant-tank network t o implement zero-voltage switching for all semiconductor devices. Consequently, ZVS-MRCs can operate with a high conversion frequency and a wide load range.

1101 International Rectifier, Hexfet Data Book, HDB-3, 19fl5. [ll]

Employing this technique, a HB ZVS-MRC is breadboarded with the same specifications as the HB ZVS-QRC. The efficiency of the HB ZVS-MRC is slightly lower than that of the HB ZVS-QRC, 81 7% at full load and low line and 78.5% at full load and high line. However, the converter can be operated from full load down to 10% of full load with a conversion frequency from 1.5 MHz to 8 MHz.

L Casey, M . Schlecht, " A High Frequency, Low Volume. Point-of-Load Power Supply for Distributed Power Svsfems." / E € € Power Electronics Specialists Conference Record, pp. 438-450, 1987.

1121 M.M. Jovanovic, "High-Frequency Off-Line Power Conversion Us/ng Quas/Resonant and Multi-Resonant Techniques," Ph. D. Dissertation, Virginia Polytechnic lnstitute and State University, Blacksburg, Virginia, 1988 (in preparationj.

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