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1997 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN

EXTRACTION, SIMULATION AND IDDQ TEST GENERATION FOR EFFICIENT BRIDGING FAULT DETECTION IN DIGITAL VLSI CIRCUITS Tzuhao Chen

Ibrahim N. Hajj

Department of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois, Urbana, IL 61801, USA [email protected]

Abstract | In this paper we give an overview of recent work in extraction, simulation, and IDDQ test generation for bridging faults (BFs) in digital VLSI circuits. We then show how these techniques can be applied in a hybrid (logic+IDDQ) testing strategy for ecient BF detection in sequential circuits. In this strategy, logic and IDDQ tests are performed in that order. Realistic BFs are rst extracted from circuit layouts. Then a voltage-based BF simulation is performed on the extracted BFs to lter out those BFs that can be detected by logic testing. IDDQ test generation is then performed targeting the remaining BFs. This hybrid testing strategy shows superior fault coverage with very short IDDQ test sets. In addition, the test generation time for this approach is signi cantly shorter than that a recently proposed approach.

enough in the design layout. A BF extractor therefore can extract the potential BFs with their occurrence likelihood values based on the defect radius and defect distribution statistics. Existing work on BF extraction will be described in Section II. The BF simulators are tools used in determining the faulty circuit behavior under the presence of BFs. The inputs to these simulators are the circuit descriptions in gate- or transistor-level together with input (test) vectors. By BF simulation one can determine the detection state of each BF as well as the fault coverage for a given test set. Five types (gate-level, switchlevel, electrical-level, mixed-level, and table-based) of BF simulators will be described in Section III. The task of test generation for BFs is to nd the proper test vectors to activate the faulty circuit behavior under the presence of BFs so that a faulty circuit can be distinguished from a fault-free one during testing. In IDDQ testing, the quiescent power supply current is sensed. Therefore, the task of IDDQ test generation is to nd proper test vectors that cause conductive paths between power supply and ground that pass through the BFs. Existing work on IDDQ test generation will be described in Section IV.

I. INTRODUCTION Due to the high integration density of VLSI circuits, bridging faults (a physical defect that form a faulty resistive short between two conducting nets in the layout), have become one of the most frequently occurring physical faults. To ensure high quality in manufactured VLSI chips, testing for BFs with high fault coverage is essential and critical. ?
A complete (all-pair) BF set of size N2 covers all node pairs in a circuit; where N is the number of nodes in the transistor netlist. For large circuits, a complete BF set could be extremely large. Therefore test generation targeting such a complete BF set could be very computationally expensive. However, [1] showed that by analyzing the physical design layout using an Inductive Fault Analysis(IFA) technique, a realistic BF set of size O(N) can be extracted. The IFA technique is based on the reasoning that two conducting nets can only be bridged together by a defect if they are close

Fault Extraction from Circuit Layout

PHASE 1

Extracted Fault Set Voltage-Based Bridging Fault Simulation Using Stuck-at Fault Test Set

PHASE 2

Reduced Fault Set I DDQ Test Generation

PHASE 3

I DDQ Test Vectors

Figure 1: Our IDDQ TG strategy.

Following the review of existing BF extraction, simulation, and IDDQ test generation techniques, we present a hybrid (logic+IDDQ ) testing strategy that achieves

This research was supported by the Semiconductor Research Corporation under Contract SRC 96-DP-109.

1

high fault coverage with very short IDDQ test set for digital sequential circuits. In the proposed testing strategy, logic testing is followed by IDDQ testing. The BFs that can be detected in the logic testing phase are dropped from the fault lists in IDDQ test generation. The reduction is fault set sizes leads to shorter IDDQ test sets which are desirable because of the low IDDQ sensing speed. The test generation ow of our approach is shown in Figure 1[2]. In phase 1, BF extraction is done on given circuit layouts to generate the extracted BF sets (EFSs). In phase 2, voltage-based BF simulation is done on the EFSs using the single stuck-at (SSA) test sets to lter out the BFs that can be detected by the logic testing. The remaining undetected BFs form the reduced BF sets (RFSs). In phase 3, IDDQ test generation targeting the RFSs is done to generate very short IDDQ test sets. Experimental results and discussions are given in Section V.

II. BRIDGING FAULT EXTRACTION Defects such as dust particles, oxide pinholes, or underetched metal interconnects that may occur during the IC manufacturing process, can cause faulty resistive bridges between two conducting nets in a circuit layout [3], as shown in Figure 2. These BFs may cause faulty logic operations or increased delays in a circuit. 000 111 111 000 000 111 000 111 000 111 000 111 000 111 000000000000000000000 111111111111111111111 000 111 000000000000000000000 111111111111111111111 000000000000000000000 111111111111111111111 000000000000000000000 111111111111111111111 111111111111 Resistive Defect 000000000000 00000000000000000 11111111111111111 Defect Radius 00000000000000000 11111111111111111 00000000000000000 11111111111111111 000 111 000 111 00000000000000000 11111111111111111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 Net 2 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 000 111 Net 1

Figure 2: BF formation due to a dust particle.

In cell-based designs, BFs can be grouped into three classes[4], depending on their physical connectivities, as shown in Figure 3. A routing BF is a BF which involves two nodes external to cells. An adjacency BF is an inter-cell BF which involves at least one internal node. An intra-cell BF involves two nodes which belong to the same cell. Routing

Routing Channel

Adjacency Intra-cell Cell A

Cell B

Figure 3: Bridging fault types.

Cell Row

Adjacency

In the past few years, several BF extractors have been developed. FXT[1], a pioneer IFA work, deter-

mines the eect of spot defects by simulating eects of the defects on various layers (e.g conducting, insulating, and semi-conducting) using statistical defect information. A BF list which contains the transistor-level BFs with their occurrence likelihood values are then generated. FANTESTIC[5] uses a similar simulation approach to extract the technology dependent topology defects from layouts using defect statistics; it then converts the topology defects to one of four primary faults (hard-short, resistive short, break, and new transistor). These primary faults are then converted to transistorlevel BFs through a topology to logic mapping. CARAFE[6], a general purpose BF extractor, is able to extract intra- and cross-layer BFs in its bridge extraction mode. For intra-layer BF extraction, CARAFE takes each region of material and checks for other regions of the same material that are close enough to the original region to form a BF. For cross-layer BF extraction, CARAFE looks for all overlaps in the two desired layers to determine the BFs. All the above tools are designed for at extraction; that is, a layout has to be attened before the extraction can be done. The

attened methods are able to extract all three classes (routing, adjacency, and intra-cell) of BFs. However, they may be slow and memory inecient. As an accuracy-cost trade o, some routing BF extractors were developed to extract on only the routing channels to save CPU time and memory. In HEMLOCK[7], a library which characterizes the ports of each cell in a standard cell library is used to maintain the connectivity of routing BFs among dierent channels. [8] is a similar work which employs a dierent method of calculating the critical area in determines the occurrence likelihood value for each BF. LIFT[9, 4], a two-level BF extractor, performs a routing channel extraction to obtain the routing BFs and a table lookup for each cell instance to obtain the intra-cell BFs. The table contains the bridging likelihood values for all node pairs inside each individual cell and is obtained through a topological scan. Although faster than the at scheme, LIFT is not capable of extracting adjacency BFs. FAULTAN[10], a fully hierarchical BF extractor developed by the authors, follows the design hierarchy while performing BF extraction. In a cell-based design with interleaving routing-channels and cell-rows, FAULTAN rst performs a topological scan on a routing channel. It then performs a table lookup to extract all the intra-cell and adjacency BFs that may occur in the cell-row. A boundary topological scan is then performed to extract all the adjacency BFs that may occur in between a routing-channel and its neighboring cell-row. A cell fault library (CFL) containing bridging

likelihood values for all potential intra-cell BFs within a cell and all adjacency BFs in between two neighboring cells is used in FAULTAN. The CFL is obtained through a pre-con guration process using topological scans on all individual-cell and cell-pair layouts. This hierarchical BF extraction scheme allows the accurate extraction of all three classes of BFs (routing, adjacency, and intra-cell) at very low CPU time and memory costs as compared with the at approach, such as CARAFE.

III. BRIDGING FAULT SIMULATION Existing work on BF simulation can be divided into the following ve types: gate-level, switch-level, electricallevel, mixed-level, and table-based. Gate-level approaches ([11, 12], to mention a few) employ either wired-and or wired-or logic to model the bridged gates so that the BF simulation can be done eciently at gate level. However, [13, 14] pointed out the inadequacy of using the wired-logic models and suggested the use of Primitive Bridge Functions (PBFs) as better models to BFs. The PBFs are new gate primitives created by bridging the outputs of two gates. For each BF a PBF need to be placed into the circuit, therefore altering the circuit structure. For large circuits with huge numbers of BFs, this approach may not be applicable. In general, gate-level approaches cannot properly handle the \Byzantine General's Problem" where an intermediate cell output voltage can be interpreted dierently (as logic 1 or 0) by dierent fanout cells[15, 16]. In addition, they can only simulate routing BFs since no information internal to the gate cells is available to the simulator. Switch-level simulators[17, 18, 19] model a BF as a permanent conducting transistor. They are applicable if the BFs can be modeled as transistors with allowable strength levels. Although the switch-level approaches are more accurate than the gate-level ones and can be used to simulate the general (routing,adjacency, and intra-cell) BFs, they may be pessimistic because of the unknown states often caused by conducting paths from VDD to GND. Furthermore, the switch-level approach are slower than the gate-level approaches since the circuits are represented at the transistor-level. Electrical-level simulators such as SPICE[20] or PSPICE[21] are accurate, but extremely expensive. These simulators calculate the voltage and current for every node and path in a circuit. This may be a waste of computational resource since much less information is required for BF simulation. Moreover, most of the signal nodes in a circuit assume voltage values close enough to be interpreted as logic 1 or 0. Therefore logic simulation is adequate at those nodes. Practi-

cally, electrical-level BF simulation is only applicable to small circuits due to the extremely long computation time. Mixed-level BF simulation methods [22, 23] were developed to simulate BFs more eciently while maintaining the accuracy of electrical-level simulators. In these methods, switch- or gate-level simulation is rst performed starting with the primary inputs, then electrical-level simulation is performed only at the bridged gates and their fanout cones for a few levels before the simulation switches back to switch- or gate-level. In [22], a constant number of gate levels for electrical-level simulation is used; all unresolved intermediate voltage values are then mapped to logic values. In [23], electrical-level simulation remains as long as the gate outputs cannot be interpreted as de nite logic 1 or 0. In the mixed-level approaches, numerical convergence problems may cause false unknowns. In addition, repeated electrical-level DC analysis are often done on the same circuit cluster unnecessarily. Furthermore, feedback BFs are not handled, since electricallevel DC analysis may be required for large circuit clusters, which complicates and slows down the simulation. The speed of mixed-level simulationis only practical for medium-sized circuits because of the frequent calls to the time consuming DC analysis subroutines. Since mixed-level simulators may still be too slow for simulating large circuits, table-based simulators[16, 24] were proposed as a time-accuracy trade-o to the mixed-level ones. In the table-based simulators, output voltages of the bridged cells for each possible bridge in a cell library are pre-computed with electrical-level simulators such as SPICE. The BF simulation thus can be done at the gate-level everywhere except at the bridged gates, where the input logic values for the bridged gates are applied to a look-up table to obtain the analog gate output voltage values. These analog voltages are then compared to the pre-computed switching threshold voltages for each fanout pin to determine their logic interpretations. In these approaches the \Byzantine General's Problem" is properly taken care of since threshold voltages at every input pin for all gate cells in a library are tabulated and used in determining the gate output states. These simulators are much faster than the mixed-level ones since gate-level simulation and table look-up are both fast. However, inaccuracies may arise when more than one input voltage values of a cell are intermediate since the switching threshold may have been changed. Also, these simulators only handle non-feedback routing BFs which could amount to less than 50% of all the realistic BFs. Our BF simulator GOLDENGATE[25] is designed for both combinational and sequential circuits using a table-based simulation scheme for best eciency. The

advantages of GOLDENGATE compared to existing table-based BF simulators are as follows: 1. It handles general (routing, adjacency, and intra-cell) realistic BFs. 2. It simulates both feedback and non-feedback BFs using a cycling event-driven technique. 3. It supports a hybrid (logic+IDDQ ) testing scheme where alternating logic and IDDQ sensings are allowed in a vector-by-vector basis. GOLDENGATE can switch dynamically between voltage and IDDQ simulation modes to determine the composite BF coverage eciently under such a hybrid testing environment.

IV. IDDQ TEST GENERATION There are many published results on IDDQ test generation. In [26], boolean functions NiVDD (NiGND ) representing input patterns that create conducting paths from node i to VDD (GND) is rst found. Then for each BF in the fault list which connects node X and Y, a test function Tn is found using the relation: Tn = NiVDD  NjGND +NjVDD  NiGND : A BF is detected when its corresponding test function is true. When the test functions are obtained, a minimum test vector set is found through a set-covering algorithm. This work is limited to combinational circuits, and its complexity depends on the boolean functions that have to be formulated and solved. Since IDDQ sensing is very slow, [27] proposed a test subset selection heuristic to reduce the number of IDDQ sensings starting with functional test sets; the selected test subset maintains the same fault coverage as the full test set. This work targets the leakage faults which are equivalent to intra-cell BF de ned above. BF detection is determined via a fast gate-level simulation and table lookups. Later [28] extended the subset selection from combinational to sequential circuits for general two-line BFs starting with SSA test sets. In [29], both all-pair and extracted routing BFs are targeted for combinational circuits. It shows that IDDQ test generation targeting all-pair BF sets is only practical for circuits with less than 10,000 gates. It also nds that targeting smaller BF sets leads to shorter test sets. In addition, they demonstrate that test sets for logic testing are much longer than that for the IDDQ testing, while suering from poor fault coverage. [30] uses the ordered binary decision diagram (OBDD) to identify equivalent BFs thereby collapsing them. After BF collapsing, a stuck-at test generator is used to generate IDDQ test sets on structurally modi ed circuits. The circuit is modi ed such that for each BF, an XOR gate is inserted with the two bridged wires as the inputs to this XOR gate. The output of this XOR gate is a primary output so that a BF is detected when the two input wires assume opposite logic values.

This work shows good fault coverage with very short test patterns; however it can be overly optimistic and is limited to routing BFs and combinational circuits. In [31], a hierarchical circuit model containing gatelevel and switch-level representations is used to facilitate the test generation for general BFs for combinational circuits. A BF is sensitized if there is a conducting path from VDD to GND containing nodes X and Y . Therefore a path tracing is required in justifying the sensitization condition for a BF. In this work a depth rst search is used in an implicit enumeration algorithm to eciently explore the search space. [32] is an incremental test generator. In this work a set of random vectors is generated initially. Simulation is done on the BF set to calculate the number of detected BFs. The test set is then augmented by random vectors one at a time to improve the fault coverage. The improvements are calculated using incremental simulation for better eciency. The program stops when no or too little improvement has been made for the last few augmented vectors. In [33], sequential circuit test generation targeting switch-level all-pair BFs is made possible through an ef cient Genetic Algorithm (GA) engine and a compactfault-list data structure. In this test generator a number of chromosomes (test sequences) are kept in a pool to form a generation. Associated with each chromosome is a tness value that is equal to the number of detected BFs. For each chromosome a switch-level simulation is performed using the good circuit to obtain the tness value. A BF between a node of state \1" and another node of state \0" is detected. A new generation of chromosomes is produced through selection, crossover, and mutation operations on the current chromosome population. The program terminates when there is no improvement made over a number of generations. In this work, general BFs are handled and all-pair BF sets are used. Despite its ability to handle sequential circuits, the runtime and test set lengths are long because of its switch-level simulation engine and large number of all-pair BFs targeted. In [34], BF collapsing is rst performed to reduce the number of BFs to about 20% of an all-pair BF set. Random test sets are then applied and BFs detected. Following the random test generation, deterministic test generation is done on structurally altered circuits using a novel adder block to target the remaining undetected BFs. Finally a reduced order simulation is performed to compact the test sets. This four-step approach generates in general short test sets for combinational circuits. [35] is another four-step (BF collapsing, GA-based test generation, deterministic test generation, and subset selection) test generation approach for combina-

tional circuits. The GA test generation scheme used is similar to [33] but for combinational circuits only. After the GA step, a technique similar to [30] is used to target the remaining BFs undetected thus far. The GA+deterministic test sets are then made compact by subset selection[28]. In comparison to [32] and [34], this approach shows in general higher fault coverage at the cost of longer test sets. We developed our test generator using the GA approach since it often out-performs deterministic approaches in producing short test sets. In our test generator, some basic GA operations are derived from [33] with a new linear fault list data structure and other improvements. Unlike other test generators that use build-in gate- or switch-level simulators for BF detection, we use a table-based simulation approach simpli ed from [25] for the accuracy of electrical-level simulation at the speed of gate-level simulation. The loaded table contains the IDDQ detection states for each BF possible and under each input pattern. It is accurate because it is derived using an electrical-level simulator. It doesn't use much computer memory since each detection state entry in the table uses only one bit. The experiments show that this approach is very ecient in producing short test sets with high fault coverage.

V. A HYBRID TEST STRATEGY Our motivation in developing a hybrid (logic+ IDDQ ) testing strategy is to reduce test cost by deriving very short IDDQ test sets at minimum extra testing and test generation cost. In our proposed hybrid testing scheme, logic testing and IDDQ testing are performed in that order. Since logic testing is almost always done at production testing, this hybrid scheme does not impose any extra testing cost for the logic testing part. Both [2] and [31] point out that targeting smaller BF sets results in shorter test sets. Therefore we choose to start by targeting the realistic BF sets (EFS) extracted from circuit layout. Our hierarchical BF extractor FAULTAN[10] described in Section 2 is used for this task. For logic testing, we choose to apply stuck-at test sets since most logic test vectors are derived using the SSA fault model. The SSA test sets are generated by a deterministic SSA test generator HITEC[36]. Until recently the logic and IDDQ tests have been done separately[37, 38] in the sense that both tests target the same BF sets. However, when IDDQ testing is performed following logic testing, a BF need not be targeted by both testing stages. Therefore, we lter out the BFs that can be detected by logic testing and target the remaining undetected BFs in the IDDQ test generation stage. This ltering can be done through

a voltage-based BF simulation using the SSA test sets for logic testing on the EFS. For this task we use our BF simulator GOLDENGATE[25] described in Section 3. After the simulation, those BFs that remain undetected by the logic testing are assigned to the reduced BF sets (RFSs). Finally, IDDQ test generation is carried out targeting the RFSs only. For this task we use our ecient GAbased IDDQ test generator described in Section 4. In our experiments, layouts for part of ISCAS89 benchmark circuit set were generated using Mentor Graphics Design Tools. A CMOS standard-cell library of feature size 1m was designed and used. All experiments were done on a SUN SPARCstation 5 with 70MHz CPU and 32Mb of RAM. In the BF extraction stage, a defect diameter of 10m was used to obtain the EFSs; the results are shown in Table 1. Table 1: BF extraction results. Ckt Gate N APS EFS T(s) s298 119 292 42,486 350 0.7 s344 160 324 52,326 542 0.9 s832 287 916 419,070 1,285 3.4 s1238 508 1,288 828,828 3,803 7.8 In Table 1, The \Gate" column contains numbers of cell instances in the circuit layouts. Column \N" contains numbers of nodes in the circuit layouts. Column \APS" contains the all-pair BF set sizes. Column \EFS" contains the extracted BF set sizes. Column \T" contains the execution CPU time in seconds. One can observe from Table 1 that the fault extraction has very eciently reduced the BF set sizes from O(N 2) to O(N). Table 2: Simulation-based BF ltering results. Ckt Vtr EFS FC(%) RFS T(s) s298 259 350 92.6 26 4.1 s344 108 542 92.3 42 3.8 s832 967 1,285 91.7 107 163 s1238 478 3,803 97.8 84 35 The simulation-based BF ltering results are shown in Table 2. Column \Vtr" contains the sizes of SSA test sets generated by HITEC. Column \EFS", which contains the sizes of the extracted BF sets targeted by the voltage-based simulator, is copied from Table 1. Column \FC" contains the BF coverage for logic testing. Column \RFS" contains the numbers of BFs that are left undetected by the logic testing. Column \T" contains the execution CPU time in seconds. One can observe from Table 2 that the BF ltering has further reduced the BF set sizes eciently. The IDDQ test generation results are shown in Table 3. Column \RFS", which contains the sizes of

Table 3: IDDQ TG results.

Ckt RFS Vtr Det Undet FC(%) T(s) s298 26 14 25 1 96.2 1.3 s344 42 5 40 2 95.2 1.6 s832 107 18 106 1 99.1 8.9 s1238 85 14 84 1 98.8 9.5

the reduced BF sets targeted by the IDDQ test generator, is copied from Table 2. Column \Vtr" contains the sizes of the IDDQ test sets generated. Column \Det(Undet)" contains the numbers of BFs that are detected(undetected) by the IDDQ testing. The numbers in column \Undet" are also the numbers of BFs undetected by the hybrid scheme. Column \FC" contains the fault coverage for the RFSs in the IDDQ testing. Column \T" contains the excecution CPU time in seconds. One can observe from Table 3 that by targeting the very small RFSs in IDDQ test generation, very compact test sets are derived. Table 4: Performance comparison. s298 s344 s832 s1238 99.63 99.92 99.97 FC(%) This[33]work 99.71 99.71 99.63 98.91 99.97 This work 14 5 18 14 TL [33] 60 90 240 370 6 175 52 T(s) This[33]work 546 64 1420 2400 The overall performance of the hybrid testing strategy is compared with that of [33] in Table 4. In [33], all-pair BF sets of sizes O(N 2 )are targeted using a GAbased test generator for sequential circuits. Row \FC" contains the realistic fault coverage. Row \TL" contains the IDDQ test lengths. Row \T"contains the excecution CPU time in seconds. We can observe from Table 4 that the IDDQ test sets generated by this new approach is much shorter than that of [33], while the fault coverage is the same or better. Also, the test generation time is much shorter. For larger circuits, the TG run-time saving may be even larger since we target the RFSs of sizes O(N).

VI. CONCLUSION In this paper, we gave an overview of existing work in extraction, simulation, and IDDQ test generation for BFs. We then described a new hybrid (logic+IDDQ ) testing strategy which achieved high fault coverage with very short IDDQ test sets.

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