Fast Smith-Waterman hardware implementation H. Ekin S¨umb¨ul Electronic Engineering Program Sabancı University Turkey
[email protected]
Zubair Nawaz, Koen Bertels Computer Engineering Lab Delft University of Technology, The Netherlands {z.nawaz, k.l.m.bertels}@tudelft.nl
Abstract—The Smith-Waterman (SW) algorithm is one of the widely used algorithms for sequence alignment in computational biology. With the growing size of the sequence database, there is always a need for even faster implementation of SW. In this paper, we have implemented two Recursive Variable Expansion (RVE) based techniques, which are proved to give better speedup than any best dataflow approach at the cost of extra area. Compared to dataflow approach, our HW implementation is 2.29 times faster at the expense of 2.82 times more area. Keywords-computational biology; sequence alignment; hardware acceleration; RVE
I. I NTRODUCTION Smith-Waterman (SW) algorithm is one of the widely used algorithms for sequence alignment in computational biology. With the growing size of the sequence database, there is always a need for even faster implementation of SW. The main contributions of this paper1 is the actual implementation of RVENP and RVEP for different versions of SW and blocking factor for RVE as described in our earlier work [1], [2]. Furthermore, we have implemented conventional linear systolic array dataflow implementation of a single element for SW for comparison. The results shows that RVEP give 129% more speedup at the cost of 182% more area than the dataflow approach. FPGAs are a good choice to accelerate the sequence alignment as they provide a lot of parallelism. A linear systolic implementation of the dataflow approach is widely used for it. Some of the solutions based on FPGAs using the dataflow are given in [3], [4], [5]. Recently Jiang [6] modified the SW formula by introducing a new variable and thereby reducing the critical path to compute a single cell. Implementations similar to our are presented in [7], [8]. Both of them are mere implementation of RVENP technique [1] and model only SW with linear gap penalty. In [7], the hardware implementation was done based on the rectangular systolic array implementation, whereas in [8], the linear systolic array implementation is done. [8] is more close to our current implementation. We have not only implemented
T
HE
1 This
work is sponsored by the hArtes (IST-035143), the MORPHEUS (IST-027342) and RCOSY (DES-6392) projects.
T C C A T G
0 0 0 0 0 0 0
G 0 0 0 0 0 0 2
T 0 2 0 0 0 2 0
C 0 0 4 2 0 0 1
G 0 0 2 3 1 0 2
C 0 0 2 4 2 0 0
A 0 0 0 2 6 4 2
A 0 0 0 0 4 5 3
C 0 0 2 2 2 3 4
Figure 1. Matrix for an example of SW algorithm, when a = −2 and x(i, j) = +2 when S[i]=T[j] otherwise −1. Elements in the trace back are shown in bold.
RVENP but also RVEP using the linear systolic array for SW with linear and affine gap penalities. [8] also takes lot more time (19900 ns) than our equivalent RVENP implementation (690 ns) for the table of size 50 × 50. The rest of the paper is organized as follows. In section II, we briefly describe the Smith Waterman Algorithm and how it is implemented on a uniprocessor. Section III describes the way the RVE technique is applied to SW and also shows the mapping to actual circuits. Section IV discusses the experimental setup and obtained results showing the time and hardware results for different versions SW with different blocking factor of RVE. Finally, we conclude the paper in Section V. II. T HE S MITH -WATERMAN ALGORITHM Let S[1..m] and T[1..n] be two sequences of length m and n for sequence alignment. The optimal alignment score F [i, j] for two sub-sequences S[1..i] and T[1..j] is given by the following recurrence equation. ⎧ ⎪ ⎪D[i, j] ⎪ ⎨F [i − 1, j − 1] + x[i, j] (1) F [i, j] = max ⎪ E[i, j] ⎪ ⎪ ⎩ 0 and D[i, j] = max E[i, j] = max
F [i, j − 1] + a D[i, j − 1] + b
F [i − 1, j] + a E[i − 1, j] + b
1
1
