FPGA Implementation of Optimal and Approximate ... - Semantic Scholar

2012 IEEE International Conference on Control Applications (CCA) Part of 2012 IEEE Multi-Conference on Systems and Control October 3-5, 2012. Dubrovnik, Croatia

FPGA Implementation of Optimal and Approximate Model Predictive Control for a Buck-Boost DC-DC converter Veaceslav Spinu1 , Alberto Oliveri2 , Mircea Lazar1 and Marco Storace2 Abstract— This paper proposes a method for FPGA implementation of explicit, piecewise affine (PWA) model predictive control (MPC) laws for non-inverting buck-boost DC-DC converters. A novel approach to obtain a PWA model of the power converter is proposed and two explicit MPC laws are derived, i.e., one based on the standard approach to synthesis of explicit MPC and one based on a simplicial PWA approximation of the resulting MPC law, which permits a more efficient implementation. An FPGA circuit is designed for both the original and the approximating MPC control law. Two hardware architectures with different FPGA footprint and computation latency are developed for each control law. Extensive real-time experiments demonstrate the performance of the two MPC controllers and their computational characteristics.

I. INTRODUCTION There is a number of challenges in controller design for power converters. First of all, the very high sampling rate heavily restricts the controller choice, i.e., only low complexity control strategies are feasible. In the Pulse Width Modulation (PWM) controlled converters, hard bounds are imposed on the duty-cycle ratios. Furthermore, the continuously increasing demand for converters with higher powerdensity, leads to tight constraints on voltages and currents through converter components, and therefore on the system states. Classical control techniques applied to power converters, e.g., controllers designed for small-signal linearized models, feedback linearization, or passivity based control, do not take into account neither state nor input constraints, and thus violations of component specifications regularly occur in practice. In this work we employ the Model Predictive Control (MPC) methodology to include the state and input constraints into the design of the control law and optimize the performance of the closed loop system at the same time. Online MPC is known to be difficult if not impossible to implement for sampling rates above 10kHz. The explicit MPC proved to be a viable alternative for the control of power converters. Successful implementation of a highly simplified explicit MPC law for a buck converter was reported in [1]. The partition of the control law consists of 9 polytopes in 2D and sampling rates up to 2.5MHz are 1 A.

of

Oliveri and M. Storace Genoa, Via Opera Pia 11a,

are with DITEN, University 16145, Genoa, Italy. E-mails:

{alberto.oliveri,marco.storace}@unige.it 2 V. Spinu and M. Lazar are with the Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands. E-mails: {[email protected],

[email protected]}@tue.nl. This work was partially supported by the EC project MOBY-DIC “Modelbased synthesis of digital electronic circuits for embedded control” (FP7INFSO-ICT-248858), and the Dutch Ministry of Economic Affairs under the project “Ultra High-Precision Power Amplifier” (IOP-EMVT-II: 08201).

978-1-4673-4504-0/12/$31.00 ©2012 IEEE

achievable through extensive pipelining of the FPGA control system implementation. In this paper, control of a more complex power converter, i.e., a non-inverting buck-boost converter, is considered. This type of converter has bilinear averaged dynamics which makes the synthesis of predictive controllers difficult. As far as online MPC is concerned, one-step predictive solutions were proposed to control this type of converters [2]. However, a successful implementation of control systems with sampling rates in the order of 200kHz, which is the target for this case study, was not reported so far. To make the explicit MPC applicable, an approximation of the non-linear model, e.g., with a piecewise affine (PWA) model [4], should be carried out. This approach was illustrated in [3], where three explicit MPC solutions were compared for the buckboost converter. The main difference between the solutions comes from the employed control models for the converter, i.e., linearization at the equilibrium state, approximation with a PWA system and a so-called adaptive linear model. The reported size of the controller partitions are 233, 521 and 153 polytopic regions in 6, 6 and 9 dimensions for the linearized, PWA and adaptive linear model, respectively. The comparison in [3] is based only on simulations, and therefore no particular implementation details are available. The control design part of this paper focuses on very lowcomplexity control laws, suitable for practical deployment in low cost FPGA or ASIC devices, and yet preserves good performances and constraint handling, which are the main advantages of MPC. The approach is to assume the dutycycle ratio of the boost stage as a piecewise-constant function of the supply voltage. In this way, the model of the converter implicitly becomes PWA, without performing any approximation of the bilinear model, and the predictive control law can be synthesized by the explicit MPC framework directly. Furthermore, the state reference can be efficiently embedded into the problem formulation, which leads to a reduction in the required number of parameters and number of regions in the resulting explicit MPC controller. Apart from the optimal explicit MPC law, a low-complexity approximation [9] on a non-uniform simplicial partition is also constructed. Along with the complete design procedure for the explicit MPC and approximate MPC solutions, this paper reports the successful automated synthesis of the hardware description for the control law computation. The VHDL description of the controller is generated with the toolbox under development within the EU-FP7 MOBY-DIC project [5]. Further, it is implemented in the FPGA device and the full experimental results are reported. The practical synthesis results suggest

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that the proposed version of the control system [1] of the explicit MPC can be executed with about 2MHz sampling rate even on a low-cost Spartan 3 FPGA. Further improvements can be attained with the approximate MPC control law. The rest of this paper is organized as follows. Section II presents the model of the buck-boost converter that is used for control design. The explicit MPC schemes along with a dedicated tuning procedure are presented in Section III. The hardware implementation is presented in Section IV and experimental results are provided in Section V. Conclusions are summarized in Section VI. II. BUCK-BOOST DC-DC CONVERTER MODEL The non-inverting buck-boost converter is essentially made up of one buck and one boost converter connected in series. This type of converter can produce lower as well as higher output voltages than the supplied one. The converter topology employed in this paper has a separate control input for each stage. The control signal is a PWM waveform with a constant frequency and controlled duty-cycle ratio. The schematic representation of the buck-boost converter is shown in Fig. 1. The PWM waveform generation is illustrated in Figure 2.

sampling period. The effects of dead-time and non-linearities of the circuit components are neglected. The ON resistance of the power transistors is lumped with the inductor resistance into RL . For more general information on the subject of modeling power converters, see, for example, reference [6]. The resulting continuous-time, nonlinear1 model is described by d2 iL − iload dvC = dt C (1) diL d1 vs − iL RL − d2 vC = dt L Naturally, duty-cycle ratios are restricted to [dmin , dmax ] ⊆ [0, 1]. High reliability of the power converter is achieved by respecting tight bounds on system states, i.e., currents through and voltages across converter components should stay within appropriate bounds. The converter parameters, bounds on external disturbances and constraints on average system states and inputs considered in this paper are summarized in Table I. The required output voltage of the converter is denoted by Vref . Name RL C L dmax dmin max vC min vC

Value 0.2Ω 22µF 220µH 1 0 22V 0V

Name Vref imax load imin load vsmax vsmin imax L imin L

Value 20V 1A 0.02A 30V 10V 3A 0A

TABLE I S UMMARY OF CONVERTER PARAMETERS AND CONSTRAINTS . Fig. 1. A schematic representation of the non-inverting buck-boost converter.

The control signal di is the duty-cycle ratio of the high-side switch in the buck (i = 1) and boost (i = 2) stages. The resulting signal si is then supplied to the gate driver of the high-side transistor of the stage i and its inverse to the lowside transistor. The period of the PWM signal in the converter used in this paper is Tpwm = 10µs. Further, a switch-on delay (dead-time) of 100ns is inserted to prevent cross-conduction in the series-connected switches.

1

di si

PWM carrier

The converter model (1) is in continuous time. However, it represents the average system behavior, which is measurable only at specific sampling instants. In Figure 2 these instants are denoted by kTs , for k = 1, 2, 3, where Ts = 0.5Tpwm is the sampling time. Then, a discrete-time version of model (1) will be employed in the controller design procedure. III. CONTROLLER DESIGN The goal of the power converter is to maintain the output voltage at predefined level Vref regardless of disturbances. It is also required to keep system states and inputs within the specified bounds. To satisfy these requirements an explicit MPC strategy is proposed, along with a dedicated tuning procedure. A. MPC controller

t 0

Ts

2Ts

3Ts

Fig. 2. Symmetric PWM waveform (dashed line – duty-cycle ratio, dotted line – control signal to the gate driver, solid line - internal triangular wave of the PWM signal generator).

For the control design, a simplified model of the system is derived. This model is obtained through averaging over the

As already mentioned in Section II, a sampling time of only 5µs is employed in the prototype converter. Such a small sampling time, generally prevents the use of on-line optimization solutions. Hence, an explicit MPC solution is adopted. Explicit MPC solutions are available only for PWA systems. Obviously, model (1) does not fall into this category. Furthermore, it should be discretized in order to be employed

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1 i.e.,

nonlinear with respect to {vc , il , d1 , d2 , iload , vs }.

for the computation of the MPC control law. Typically, model (1) would be discretized by the Euler forward method, which leads to a bilinear discrete-time model [7], [3]. In [3], this model was further approximated by PWA or adaptive linear models to make explicit MPC solution applicable. As observed also in [3], the PWA approximation approach leads to very large and complex controller partitions of the MPC solutions which are not likely to be implementable in practice and may result in rather a large steady-state offset. The adaptive linear model leads to explicit MPC solutions with large number of parameters, which is also not desired for practical applications. 1) Control model: Here we start with the observation that the main difficulty in the controller design for the buck-boost converter comes from the bilinear terms involving d2 . In this paper, we propose to restrict the values of d2 to a set with a finite number of elements D2 ∈ [dmin , dmax ]. Furthermore, d2 = ci remains constant for a given range of vs ∈ Vi , i ∈ {i, . . . , nv }. At a first glance, keeping d2 piecewise-constant may seem a very restrictive assumption. However, it will be shown in Section V that good disturbance rejection and fast startup of the converter can be achieved despite this  v restriction. Let us define u := vs d1 and x := iLC . The model (1) can be recast as follows     1  ci 0 0 −C C x+ 1 u+ iload , (2) x˙ = 0 − cLi − RLL L

thus d2 remains constant and the model (2) is affine for the entire sampling period. As such, the continuous-time model (2) can be discretized for each affine subsystem to obtain the following discrete-time PWA representation x(k + 1) =Ai x(k) + Bi u(k) + f iload (k),

xeq (vs , iload , d1 ) :=

vs ci d1 −RL iload c2i iload ci

, if vs ∈ Vi .

(5)

2) Controller design: In this paper, we aim at finding the duty-cycle ratios d1 and d2 as a function of [xT , vs , iload ] in such a way that the error between the predicted h Vref i converter states and a reference xref (vs , iload ) = iload is minici mized. The duty cycle ratio d2 can be computed in a trivial way, by finding an i ∈ {1, . . . , nv } such that vs ∈ Vi and taking d2 = ci . The computation of d1 = u/vs can be performed by minimizing the following cost function:

if vs ∈ Vi .

Given the partition of the supply voltage range, the task is to design constants ci for each Vi . Obviously, the highest efficiency of the power converter is achieved for the highest sustainable d2 . However, a large d2 implies slow ramping of the inductor current in the boost mode, which leads to poor disturbance rejection. To make a trade-off between the disturbance rejection in boost mode and the overall efficiency, a parameter β is introduced:   inf(Vi ) ci = min dmax , β . (3) Vref

(4)

if vs (k) ∈ Vi ,   h i Ts c i 1 0 C where Ai = , Bi = Ts and f = Ts ci −Ts RL +L L − L L h T i − Cs . The v and i s load values are considered constant 0 during each sampling period. Observe that for a certain vs , iload , and d1 the converter model (2) has a unique equilibrium state2 # "

J(x(k), vs (k), iload (k)) = N X j=1

kQ(x(k + j|k) − xref (vs (k), iload (k)))k∞ ,

(6)

where x(k + j|k) denotes the prediction of the state at time k + j based on the information available at time k, N is the prediction horizon, and Q is a constant weighting matrix. The predicted values of supply voltage and load current are assumed to be constant after time k. Then, the control problem can be formulated as follows: min J(x(k), vs (k), iload (k)) (7)  min   max  vC vC s.t. min ≤ x(k + j|k) ≤ max , ∀j ∈ {1, ..., N }, iL iL u(0),...,u(N −1)

High values of β lead to high efficiency of the converter, conversely, low values can improve disturbance rejection. The bounds on β are implicitly defined by

x(k + j + 1|k) = Ai x(k + j|k) + Bi u(j) + f iload (k),

imax imax load load RL , ∀i ∈ {1, . . . , nv }. ≤ ci ≤ max iL Vref − inf(Vi )dmax

if vs (k) ∈ Vi ,

u(j) = u(N − 1), ∀j ≥ Nc .

u(j) ∈ [vs (k)dmin , vs (k)dmax ], ∀j ∈ {1, ..., N }

V [dmax ref β

Observe from (3) that for any Vj ⊆ , vsmax ] the associated cj = dmax . Therefore, it is reasonable V max to define Vnv := [dmax ref ]. Further, the interval β , vs Vref min [vs , dmax β ] is split into non-overlapping subintervals Vi , i ∈ {1, . . . , nv − 1}. In our case the supply voltage range is split into Vi := [8 + 2i, 10 + 2i] for i ∈ {1, . . . , 4}, V5 := [18, 21] and V6 := [21, 30]. Given the splitting of the supply-voltage range {Vi } and the parameter β, one can compute the coefficients ci . Note that the decision on changing ci is made at sampling instants,

Above, Nc denotes the control horizon. Observe that the optimization problem (7) can be efficiently cast as a multiparametric mixed-integer linear program with only 4 parameters [x> (k), vs (k), iload (k)]. In our case, the following controller parameters   were 1 0 chosen: N = 2, Nc = 2, β = 0.95, and Q = 0 1 . 2 Since v is fixed, it can be shown that the model (2) admits the same s equilibrium state as (4).

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The parametric solution to (7) was computed with the Multi Parametric Toolbox [8] and is a PWA function u(vC , iL , vs , iload ) defined over 153 generic polytopic regions in 4 dimensions. The resulting PWA function will be referred to as PWAG throughout the remainder of the paper. A plot of the polytopic partition for fixed parameters vs and iload is shown in Figure 3.

Fig. 3. Two-dimensional section of polytopic partition along vs = 15 V and iload = 0.2 A.

B. Approximate MPC controller The evaluation of optimal MPC controller can be in some cases computationally heavy, due to the complexity of the control function. This issue limits the application of MPC to systems requiring low sampling times. This problem can be solved by employing approximations that simplify the control function, allowing to achieve a faster circuit computation and therefore lower sampling times. On the other hand, closed-loop system stability must be preserved and constraints fulfilled. Some techniques have been developed in the recent years for the approximation of explicit MPC [9], [10]. In this paper the optimal controller is approximated with the method described in [9]. Based on this technique, the PWAG control function is approximated with another PWA function, which is defined over a simplicial partition of the domain of operation (this PWA function will be referred to as PWAS in the remainder of the paper). The approximation is obtained by minimizing a cost function, representing the norm (L1 , L2 or L∞ ) of the difference between the PWAG controller and the PWAS one; in addition, constraints are imposed on the PWAS function in order to guarantee that the system states and inputs satisfy the design specifications. A stability analysis is performed a posteriori. The domain of the PWAS function has been chosen as DP W AS = {[vC , iL , vs iload ]0 : 0V ≤ vC ≤ 22V, 0A ≤ iL ≤ 3.5A, 10V ≤ vs ≤ 30V, 0.02A ≤ iload ≤ 1A}, whereas the simplicial

partition has been generated by subdividing vs and iload in 3 segments of the same length, iL in 7 segments of the same length and vC in 7 non-uniform segments as shown in figure 4.

Fig. 4.

Domain partition along vC [V ].

The reason for the concentration of points around vC = 20 is that the value 20 is the reference voltage to which

the system must be regulated; therefore a higher precision around this point is required to ensure stability. The resulting simplicial partition is made up of 1024 vertices and 24576 simplices. The L2 norm of the difference between the PWAG control law and the PWAS one is minimized. IV. CIRCUIT DESIGN The details on the FPGA implementations of PWAG and PWAS functions are given in the following subsections. A. PWAG controller A circuit architecture has been designed by the authors recently [11] for the computation of PWA functions defined over a generic polytopic partition of the domain. This architecture is therefore suitable for the implementation of MPC controllers. Successful implementation results can be found in [12]. Here we use an improved and optimized version of the circuit proposed in [11] (referred to as pwag ser) and a new solution (pwag par). The pwag par architecture has a parallel computing unit in which a Multiply and Accumulate block from pwag ser has been replaced by a bank of adders and multipliers, in order to reduce computation latency. The PWAG function is defined over a collection of polytopes {P1 . . . , Pnr }. An affine control law Fi y + Gi is defined within each polytope Pi . The computation of the PWAG function in a point y is performed by (i) locating the polytope Pi such that y ∈ Pi and (ii) evaluating the associated affine function. The first step, known as the point location problem, is solved by means of a binary search tree, computed offline, whose non-leaf nodes correspond to polytope edges and leaf nodes correspond to polytopes [13]. B. PWAS controller The evaluation of a PWAS function with a digital circuit can be performed in a very efficient way, due to the regularity of the simplicial partition. Two circuit architectures have been proposed in [14] for the evaluation of this kind of functions. The point location problem is solved here in just one clock cycle by using comparators, while the evaluation of the PWAS function in a point y is performed by linear interpolation of the value of the function at the vertices of the simplex containing y. A further generalization was proposed in [15] to handle non-uniform simplicial partitions: a PWA mapping is applied to each input component, before the computation of the PWAS function. This allows for mapping of the non-uniform partition into a uniform one. One major upgrade has been applied to the solutions available in the literature (called pwas ser and pwas par), i.e., the mapping of the non-uniform partition into the uniform one is performed with multipliers instead of shifters; this allows to choose an arbitrary partition, and not necessarily a partition in which the length of the subdivision is a negative power of 2. Note that the number of multipliers can vary for the implementation of the PWAS function because it can happen that the partition is uniform along one or more domain dimensions; in this case some multipliers can be saved.

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C. Circuit performance The parameters chosen for this application for both PWAG and PWAS architectures and the related circuit specifications after “place and route” process are reported in Table II.

N. bits inputs N. bits outputs Clock (MHz) Latency (ns) Multipliers Memory size (B) occupied slices (%)

pwag ser 16 34 80 788 1 880 14

pwag par 16 34 40 600 4 880 10

pwas ser 12 21 40 250 2 1536 17

MS vC

+ vC

vs

i+ L

iload iL

x1 x2

SC2 ×

PWAG

x3 Pred.

x4

PWAS Sinc

pwas par 12 21 40 125 6 7680 38

1 vs

PWM Buffer

C. d2

z −1 z −1

TABLE II PARAMETERS AND CIRCUIT PERFORMANCES OF THE PWAG AND PWAS ARCHITECTURES .

SC1

DATA ARE RELATED TO A S PARTAN 3AN FPGA ( XC 3 S 700 AN ).

Fig. 5.

Note that both pwag and pwas architectures can be easily implemented on small and low-cost FPGAs (such as a Spartan 3) and are able to perform the computation of the control law in a time which is an order of magnitude lower than the sampling time of the system. The better performances of the pwas circuits in terms of latency, with respect to the pwag ones, are payed with a larger area and memory occupation. An increase in the number of multipliers, moreover, allows a further improvement of the circuit speed with the parallel architectures. For further information on the circuit implementation of PWAG and PWAS functions the interested reader is referred to the Moby-Dic toolbox documentation [5] and references therein. V. EXPERIMENTAL SETUP AND RESULTS The power stage of the converter is controlled by a PWM signal with a 100kHz switching frequency. Symmetric PWM generation allows to achieve a sampling rate of the control law of 200kHz. The PWAG and PWAS functions describe the behavior of u, which should be further post processed to derive d1 = vus . Since the division operation is highly time consuming, especially on FPGAs, it was preferred to compute v1s in parallel with the evaluation of the control function and then to use a one-cycle multiplication to obtain d1 . Neither the PWAG nor the PWAS function return d2 , which should be computed separately by finding the supply voltage region Vi , such that vs ∈ Vi . In our case, the number of regions is very limited and a linear search was employed. In more time-critical applications, a binary search tree can be used to locate the region vs belongs to. Next, d2 is computed by (3). We point out that that Vref is constant here, thus the division is substituted with the multiplication by a constant 1 Vref . Note that the control action cannot be applied in the same time with sampling instant due to delays in the measurements and MOS-FET drivers. Hence, the control action is computed based on a one-step prediction of the system states, and is applied at the next PWM cycle.

Data flow diagram of the control system.

The conceptual data flow diagram of the control system implementation is shown in Figure 5. “MS” denotes the measurements subsystem, “Pred.” block stands for predictor, “SC1” adapts the representation of the controller variables [x> (k + 1) vs (k) iload (k)] to the internal representation in the implementation of PWAG or PWAS functions, “C. d2 ” is the block that computes d2 . When the computation of d1 (k+1) and d2 (k+1) is complete, their values are stored in the “PWM Buffer” until the sampling synchronization signal becomes active. Then the duty-cycle ratios of the power stage are updated and the control loop is repeated. The VHDL files describing the hardware implementation of PWAG and PWAS functions were generated with the toolbox under development within the MOBY-DIC project [5]. Further, these files are included as an external IP node into the LabView FPGA module and synthesized on the NI-PXI-7852R multifunction acquisition board featuring the Virtex-5-LX50 FPGA device. The pwag ser architecture was synthesized using a 80MHz clock frequency (40MHz for pwag par). The maximum clock frequencies reported by the synthesis tool after the “place and route” step were 98MHz for the serial and 53MHz for the parallel architecture. As such, given the estimated state, the control action can be computed in less than 1µs for both architectures. The measurement and observer computation take less than 2µs. The total computation time is lower than 3µs, which is well within the 5µs required by the application. The measurement results for serial and parallel PWAG architectures are equivalent. Hence, only results for the parallel architecture are presented in what follows. The startup of the converter with the supply voltage at lowest bound is shown in Fig. 6 (blue line). For the sake of comparison, the startup of the same converter in closed loop with the lowcomplexity affine state feedback control law designed in [7] is shown in green. The controller in [7] was designed for the converter with resistive load of 100Ω. Thus, the experiment was performed with the same load, even if the predictive controller designed in this paper can handle arbitrary loads. Figure 6 evidences that no constraints violation occur during

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20 voltage(V)

20

vC

15 10

19 18 17 16

5 0

−1.5

0

0.5

1

−1

−0.5

0

0.5 time(s)

1

0.5 time(s)

1

1.5

2 −3

x 10

1.5

time (ms)

1.5

current(A)

3 iL

2

1 0.5

1 0

−1.5

0

0.5

1

−1

−0.5

1.5

0

1.5

−3

time (ms)

Fig. 6. Startup comparison of the developed PWAG predictive controller compared to an affine state-feedback control law (blue - predictive controller, green - affine control law).

2 x 10

Fig. 8. Illustration of the disturbance rejection in the load current of the PWAG controller (green - output voltage/inductor current, red - input voltage/load current).

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experiment. Further, the considerably faster rising time of the converter in closed loop with the predictive controller serves as a motivation for using this type of controller in practical applications. To illustrate the disturbance rejection of the developed controller, the buck-boost converter was subject to several tests. First test takes the supply voltage trough all Vi , i.e., vs is a sinusoidal waveform with variation within 10.5V and 24.5V. A resistive load of 100Ω is considered here. The input and output voltage profiles are shown in Figure 7.

vC

15 10 5 0 −0.2

0

0.2

0.4 0.6 time (ms)

0.8

1

0

0.2

0.4 0.6 time (ms)

0.8

1

3 iL

2 1 0 −0.2

voltage(V)

25 20

Fig. 9.

15

−0.08 −0.06 −0.04 −0.02

0 0.02 time(s)

0.04

0.06

0.08

0.1

Fig. 7. 0.8Illustration of the disturbance rejection in the input voltage of the PWAG controller (green - output voltage, red - input voltage). current(A)

Startup of the converter with PWAS control law.

0.6

0.4 Second test consists of application of fast step variation in the0.2load current from 0.2A to 0.9A and back. The supply voltage is −0.08 fixed−0.06 to 17.5V in this0 experiment. The 0.08 current −0.04 −0.02 0.02 0.04 0.06 0.1 and voltage waveforms are showntime(s) in Figure 8. The converter in closed loop with the approximate control law was subject to similar tests. Both serial and parallel PWAS architectures with 12 bit resolution of the input were implemented. The architectures were synthesized with a 40MHz clock frequency, whereas the maximum clock frequency reported by the synthesis tool was 45MHz. The measured waveforms at startup are shown3 in Fig. 9. It can be

3 The measures refer to parallel architecture, the same results have been obtained with the serial one.

seen in Figure 10 that the approximate controller copes well with the variations in the supply voltage. However slightly higher offset in the output voltage can be observed. Note that the proposed control scheme does not include any integral action, and hence, steady state offset can appear when there is a mismatch between the model of the converter and the actual plant. An integral action can be added by augmenting the state of the system with the integral of the output voltage error. As in the case of rejection of the power supply voltage variations, the effects of the approximation of the controller can be noticed in the case of sudden variations of the load current. Lower damping of oscillations in the LC circuit can be observed for high load steps. This effect is illustrated in Fig. 11. This is an expected result as the approximated controller puts more effort in satisfying constraints rather than achieving good performances, when close to the boundary of the domain of operation.

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were performed, which demonstrated the effectiveness of the proposed solutions.

voltage(V)

25 20

ACKNOWLEDGMENTS

15

The authors acknowledge helpful discussions with W.P.M.H. Heemels. −0.08 −0.06 −0.04 −0.02

0 0.02 time(s)

0.04

0.06

0.08

0.1

R EFERENCES

0.8

voltage(V)

current(A)

Fig. 10. Illustration of the disturbance rejection in the input voltage of the PWAS 0.6 controller (green - output voltage, red - input voltage). 0.4 0.2 20 0 19

−0.08 −0.06 −0.04 −0.02

0 0.02 time(s)

0.04

0.5 time(s)

1

0.5 time(s)

1

0.06

0.08

0.1

18 17 −1.5

−1

−0.5

0

1.5

2 −3

x 10

current(A)

1.5 1 0.5 −1.5

−1

−0.5

0

1.5

2 −3

x 10

Fig. 11. Illustration of the disturbance rejection in the load current of the PWAS controller (green - output voltage/inductor current, red - input voltage/load current).

The accuracy of the steady-state output voltage is summarized in Table III. It was observed that the accuracy of the output voltage is within ±1% except for the PWAS controller when the supply voltage is close to the boundary of the domain of operation. PWAG [19.9, 20.2]V [19.95, 20.05]V

PWAS [19.7, 20.1]V [19.9, 20.05]V

conditions vs ∈ [10, 30]V, iload = 0.5A vs = 17V, iload ∈ [0.1, 1]A

TABLE III C IRCUIT SPECIFICATIONS OF THE ARCHITECTURES FOR THE COMPUTATION OF PWAG FUNCTIONS .

VI. CONCLUSIONS A new explicit MPC controller for a non-inverting buckboost DC-DC converter has been designed, which allows for efficient circuit implementation. Two digital controllers have been implemented on FPGA: one implementing the optimal MPC controller defined over a generic polytopic partition of the domain and one implementing a low-complexity approximation of this controller defined over a simplicial partition. Serial and parallel architectures have been exploited for both circuits and extensive real-time experiments

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