2015 Online International Conference on Green Engineering and Technologies (IC-GET)
FPGA Implementation of Universal Asynchronous Transmitter and Receiver Jayesh More, Rushank Suryavanshi, Gaurav Dasarwar, Sivanantham S* and Sivasankaran K School of Electronics Engineering VIT University Vellore - 632014, India. E-mail:
[email protected]
three main components i.e. transmitter, receiver and the baud rate generator. As we are using the state machines for transmitter and receiver due to which our design become less complex and the proposed UART becomes more stable, reliable and compact for serial data communication[3]. Due to which, the consumption of LUTs, flip flops or in short the area consumption of the chip becomes less. We have also tested our design for the errors which a rises during transmission of data to analyze that our output of the receiver is free from the errors or not.
Abstract—The proposed work in this paper describes the implementation of universal asynchronous transmitter and receiver, that is UART. The UART is a type of a serial communication protocol which serves the purpose of full duplex communication over a serial link. The UART here in is described by hardware description language that is Verilog HDL. The Verilog HDL code has been simulated in the ModelSim 10.1d and implemented on Altera DE1 board. Keywords—Serial Communication, asynchronous transmitter, full duplex communication.
II. UART I.
INTRODUCTION
The block diagram for UART is as shown in the figure.1 below. It comprises mainly of clock, transmitter and receiver. The function of the transmitter module is to convert the 8 bit serial data into the single bit data. In this module, when our load signal is high the data in is stored into the holding register. The data in the holding register is shifted to the intermediate register with the start bit of zero and this intermediate register is of 9 bits. Once the shift signal is high the least significant bit of the intermediate register i.e. the start bit comes at the output of the transmitter and served as the input to the receiver. When the entire data has been sent, the transmitter provides a parity bit which is served as the input to the receiver.
The main motivation behind the implementation of UART on FPGA is: UART is directly available in microcontroller for serial communication but this is not available in case of FPGA. This proves to be helpful for providing the interface between the FPGA and some communicating module or devices like GSM module, etc. The UART [1] is basically used in between the slow and the fast peripheral devices for example: computer and printer or in between the controller and LCD. Due to this reason, UART is used mostly for the short distance, low speed and is of low cost. The main blocks for the design of UART are clock generator, transmitter, and the receiver. The transmitter and the receiver block diagrams are implemented using finite state machines. The universal asynchronous receiver/transmitter is abbreviated as UART. The UART is basically used in between the slow and the fast peripheral devices for example: computer and printer or in between the controller and LCD. Due to this reason, UART is used mostly for the short distance, low speed and is of low cost. This paper uses the Verilog description language to implement the core functions of UART and integrate them into a FPGA chip [2]. Singh et.al proposed a novel low power UART [6] which is implemented on Altera Vertex FPGA. The UART plays a vital role in modern complex control systems [7], motion control IC design [8], Reliable High Speed Data Acquisition System [9], AES algorithm [10] to communicate quickly and effectively. It has
978-1-4673-8625-8
A. Transmitter Module The function of the transmitter module is to convert the 8 bit serial data into the single bit data. In this module, when our load signal is high the data_in is stored into the holding register. The data in the holding register is shifted to the intermediate register with the start bit of zero and this intermediate register is of 9 bits. Once the shift signal is high the least significant bit of the intermediate register i.e. the start bit comes at the output of the transmitter and served as the input to the receiver. When the entire data has been sent, the transmitter provides a parity bit which is served as the input to the receiver. To check the CRC error, we have to provide the divisor as the user input and once the entire data has been sent,
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2015 Online International Conference on Green Engineering and Technologies (IC-GET) the transmitter generates the remainder which is given as the input to the receiver and receiver provide us the crc_out. For interfacing other devices such as GSM module with FPGA [4] [5] we require the UART. B. Receiver Module The function of the receiver module is that it will store the tx_out i.e. the output of the transmitter which is of single bit into the intermediate register with the start bit as the least significant bit and collectively provides the serial data of 8 bit. When the load signal is high it will get the start bit from the transmitter which assures that the original data is now being send by the transmitter. Once the shift signal is becomes high with no load signal, the data coming from the transmitter gets shifted into the intermediate register of the receiver and provides the 8 bit serial data which we have given as an input to the transmitter. Once the entire data has been sent the parity error and the CRC errors has been checked out and are served as the input to the transmitter. If parity error and CRC errors occur or are at logic 1, it means that our transmission is having some errors. The Baud rate generator is nothing but the frequency divider. In this UART we will apply the synchronized clock signal to both transmitter and the receiver. The clock signal applied to the receiver is 16 times to that of the transmitter.
Fig. 2. Transmitter State Diagram
Fig. 3. Receiver State Diagram
Fig.2 shows the state diagram of transmitter module. The state diagram explains the functionality of the transmitter that how the data has been transmitted. Fig.3 shows the state diagram of receiver module. The state diagram explains the functionality of the receiver that how the data has been received through transmitter D. Baud-rate Generator The processor clock generator receives a signal from an external clock source and produces a UART input clock with a programmed frequency. The UART contains a programmable baud generator that takes an input clock and divides it by a divisor in the range between 1and (216 - 1) to produce a baud clock. The baud rate frequency element can be calculated using given clock frequency (oscillator clock) and the required baud rate. The figured baud rate frequency element is utilized as the divider variable. In this outline, the frequency clock delivered by the baud rate generator is not the baud rate clock, in any case, 16 times the baud rate clock. The reason for existing is to definitely test the serial information at the recipient. At the point when the UART gets serial information, it is extremely basic to figure out where to test the information data. The perfect time for inspecting is at the center purpose of every serial information bit. In this configuration, the get clock frequency is intended to be 16 times the baud rate, in this manner, every data width got by UART is 16 times the get clock cycle.
Fig. 1. Block Diagram of UART
When the load signal is high it will get the start bit from the transmitter which assures that the original data is now being send by the transmitter. Once the shift signal is becomes high with no load signal, the data coming from the transmitter gets shifted into the intermediate register of the receiver and provides the 8 bit serial data which we have given as an input to the transmitter. C. State Diagram When the load signal is high it will get the start bit from the transmitter which assures that the original data is now being send by the transmitter. Once the shift signal is becomes high with no load signal, the data coming from the transmitter gets shifted into the intermediate register of the receiver and provides the 8 bit serial data which we have given as an input to the transmitter.
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2015 Online International Conference on Green Engineering and Technologies (IC-GET) REFERENCES
III. ALGORITHM • •
• •
Three different modules are made for baud rate generator, transmitter and receiver. Baud rate generator is generated using formula and by changing value of the variable we can change the baud rate. Some control signals are defined which will control the transmission and reception. The 8-bit data is given serially and can be seen on the LEDs assigned
[1]
[2]
[3]
IV. RESULTS [4]
The simulation results are consists of successful transmission of data from transmitter. The UART has been simulated and implemented on Altera FPGA. The simulation waveform in the Modelsim software is shown below
[5]
[6]
[7]
[8]
Fig. 4. Transmitter Output
[9]
[10]
Fig. 5. Receiver Output
V. CONCLUSION This paper describes the architecture of UART. The working principle of UART is explained and proved that communication is fast and effective between transmitter and receiver which are implemented on Cyclone II board.
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