Functional test compaction by statistical modelling of ...

Functional test compaction by statistical modelling of analogue circuits N. Akkouche, A. Bounceur, S. Mir and E. Simeu TIMA laboratory 46, AV. Felix Viallet 38031 Grenoble Cedex, France Email: [email protected]

Abstract— In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the circuit under test. The statistical model is obtained using data from a Monte-Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test compaction method is based on the minimization of the defect level, again at the design stage, that is calculated from the estimated PDF and the actual specifications of the circuit performances. The suitability of the actual reduced functional test set for production test must next be evaluated in terms of its capability of detecting catastrophic and parametric faults.

I. I NTRODUCTION The increasingly important part played by the test on the cost of analogue and mixed-signal integrated circuits imposes a step of optimisation of the test methods to reduce production test costs. Traditionally, analogue circuits are tested by explicit functional tests that measure directly the set of the circuit performances and compare them with their specifications, defined by the designer. Thus, the circuit is classified as functional if all the specifications are satisfied. Otherwise, it is faulty. This process is very expensive in terms of test time and equipment. Test time being a major factor, it is obvious that the test of all the circuit performances is very often not economically viable during production. Thus, it is necessary to resort to a reduced number of performances, which will be carried out in a reasonable time, while accepting a minimum test risk. This is typically the case of analogue and RF circuits. Several functional test compaction techniques have been proposed to date. In [1], a fault-driven approach is followed. The set of non-redundant functional tests is built cumulatively by adding at each step the test for which the yield of the currently excluded tests is maximized. The algorithm terminates when a desired fault coverage is reached. A weighted version of this greedy compaction approach is solved in [2] wherein the test cost of test configurations is taken into account. In [3], regression models are built to map a set of explicitly tested performances to the values of the rest (untested) performances, and test limits are assigned such that they guarantee the compliance of the untested performances to the specifications with the desired confidence levels. A modified multidimensional scaling method called isomap is

studied in [4] for fast exploration of the functional test space to determine redundancy in functional tests. Another technique is presented by [5] where test compaction is based on the calculation of a redundancy matrix obtained from the correlation matrix. Recently, the use of machine learning has been explored to learn the intricate mappings between a subset of functional tests and a direct pass/fail decision [6], [7], [8]. In this article we propose a new approach for the compaction of functional tests, based on the minimisation of the defect level (proportion of faulty circuits that pass the test) at the design stage. The suitability of the reduced test set for detecting catastrophic and parametric faults is next evaluated by fault simulation. It must be noticed that since only functional test sets are considered, the reduced test set has no yield loss. The statistical modelling of the circuit under test and the evaluation of the defect level is carried out as described in [9]. The performances of the circuit under test follow a multi-normal distribution for the case-study considered. The rest of the paper is organized as follows. Section II describes the principle of the method. Section III studies the validation of the Gaussian assumption. In Section IV, the method is applied on a fully differential amplifier and results are analysed in the following Section. Finally, Section VI gives some conclusions and directions for future work is described. II. P RINCIPLE OF THE TECHNIQUE The test compaction method is based on evaluating the defect level obtained when circuit performances are eliminated at the design stage, that is, when only process deviations are considered. At each stage, the method evaluates the defect level that results from the elimination of a single performance. The performance whose suppression results in a minimal defect level, is then eliminated. This process is repeated until the set of the performances is reduced to only one performance. At the end, we obtain a ranking of performance tests in terms of the estimated defect level. It must be noted that this heuristic used for performance elimination seems to lead to the optimal result, in particular for the case-study considered, and thus there is no need to study all possible combinations of performances. The principal stages of the method are summarized in the flow chart of Figure 1. In order to estimate the defect level, we use the technique presented in [9]. This technique supposes that the joint PDF of

the performances is multi-normal. The PDF is estimated from data obtained via Monte-Carlo simulation. The parameters of the multi-normal distribution include the vector of average values and covariance matrix of the performances. The estimation of test metrics with ppm (parts per million) precision is made possible by considering the multi-normal behaviour. A simple program in R [10], implements the method of simulation of a large circuit population (>1 million circuits) from the multinormal distribution. Start Generation of 1 million instances of the circuit under test with NP performances i=1

yes NP = 1

yes

Eliminate the performance generating the minimum defect level NP = NP - 1

because: E(U ) = 0 (1) E(U U ′ ) = P ′ E((X − M )(X − M )′ )P = P ′ SP = P ′ P DP ′ P = D

(2)

Where E(.) is the mathematical expectation. To check the normality of the marginal variables, we use the Normal Quantile Plots. This method makes possible to quickly read the mean and the standard deviation of such a distribution. Its principle is to trace the quantiles of the performance to be tested according to the theoretical quantiles of a reduced centered normal distribution. If the variable is Gaussian, the points are aligned. IV. C ASE - STUDY CIRCUIT

no

i > NP

no

- Eliminate the performance i - Evaluate and safeguard the defect level i=i+1

The application of the method is carried out on a differential amplifier, designed with technology 0.18µm CMOS of STMicroelectronics. The amplifier consists of four main blocks: a bias circuit, a start-up circuit, a common-mode control circuit and a differential amplifier circuit. The circuit is illustrated in Figure 2. Monte-Carlo simulations (1000 iterations) of the circuit are carried out in order to find the adjusted Gaussian distributions of each performance. The complete set of the performances considered is indicated in Table I, where a1 and a2 represent the bounds of each specification.

Display the results of various eliminations Stop

Fig. 1.

TABLE I G AUSSIAN PARAMETERS AND SPECIFICATIONS OF THE PERFORMANCES

Flow chart of the method of reduction of performances.

III. M ULTI - NORMAL HYPOTHESIS An extensive literature exists regarding the test of multivariate normality [11]. Unfortunately, there is no known uniformly most powerful test. In our study, we assume that the circuit population generated by Monte-Carlo simulation follows a multi-normal distribution. We validate this assumption by testing the normality of a marginal variables in the corresponding independent space of the performances after projection. Let us suppose that Monte-Carlo simulations (X) follow a multi-normal distribution with mean vector M and covariance matrix S. This matrix can be decomposed in the form S = P DP ′ , where D : a diagonal matrix whose coefficients are eigenvalues; P : a matrix whose columns are eigenvectors. If the performances X follow a multi-normal distribution N (M, S) then U = P ′ (X − M ) follow a normal distribution N (0, D). Thus the test of the Gaussian assumption is equivalent to the only test of the marginal normality of the vector U (independence is ensured by the fact that D is diagonal)

Performance 1. AD 2. GBW D 3. P hase M argin 4. CM RR 5. P SRR (GN D ) 6. P SRR (VDD ) 7. T HD 8. IDD 9. Intermodulation 10. SR+ 11. SR− 12. N oise

µ 76.60dB 330MHz 63.33 -42.76dB -29.99dB -28.21dB 66.19dB 2.48mA 67.57dB 73.14V/µB 73.14V/µB 39.22µV

σ 0.493dB 18.14MHz 0.45 1.02dB 3.65dB 3.75dB 2.38dB 0.21mA 1.09dB 5.55V/µB 5.55V/µB 0.5µV

Specification a1 a2 74.49dB 78.71dB 252.36MHz 407.64MHz 61.40 65.26 -47.13dB -38.39dB -45.61dB -14.37dB -44.26dB -12.16dB 56.00dB 76.38dB 1.58mA 3.38mA 62.90dB 72.24dB 49.38V/µB 96.88V/µB 49.38V/µB 96.88V/µB 37.08µV 41.36µV

The specifications of the amplifier are not known a priori, since the real application of the device is not considered in this work. Thus, to have a high design yield of Y = 99.99% when all the performances are considered, we have fixed each specification at µ ± 4.3σ, where k = 4.3 is the tolerance of specifications. The analysis of the correlations between the performances, shows that the performance SR+ has the same values as SR−, and thus the latter was eliminated. In the continuation of the study the number of performances of the circuit under test is reduced to 11 performances. Figure 3 shows an example of quantile plots of a marginal variable in the independent space.

VDD V biasp o V casp o V biasp o

o VZ

V casp o

V casp o o + V in

o V in-

V out o

+

V out o

V CM o

-

o V biasn

V2

V1 V REF

V REF

VZ V out o o + V out

V casn o

o V casn

V biasp

V biasp o

V biasp o

V biasp o

V biasp o

-

oV ana 0.9V

V CM o

V casn o

G ND

Start-Up Circuit

Bias Circui t

Fig. 2.

Fully differential amplifier used as case-study.

6

3

120

x 10

100

2

1

Defect level (ppm)

Quantiles of marginal variable

Common-Mode Control Circuit

Amplifier Circuit

0

-1

-2

80

60

40

20

-3

-4 -4

0

-3

-2

-1

0

1

2

3

4

Standard Normal Quantiles

Fig. 3.

Application of the Normal Quantile Plots on a marginal variable.

It is clear that the set of points are aligned. This proves that the corresponding marginal variable is Gaussian. Similar results was obtained for the 10 other marginal variables. This result shows that the assumption of multi-normality of the performances is not contradicted. V. R ESULTS The application of the test compaction method on the circuit of Figure 2 allows us to: • identify the performances to be eliminated from the test set for a certain value of the defect level. • to establish an order of elimination of the performances. • to evaluate the yield and the defect level for a reduced set of performances. A. Defect level Figure 4 presents 20 simulations of the test compaction method for a tolerance of specifications k = 4.3. An analysis of the graph of Figure 4 shows that it is possible to build a 95% confidence interval of the defect level for each number of performances to include in the test. For example for a value of the defect level varying between 4ppm and 17ppm (to accept an error of 17 faulty circuits which passes the test among 1 million circuits manufactured), the method indicates that it is possible to eliminate 4 performances from the test.

11

10

9

8

7

6

5

4

3

2

1

Number of performance

Fig. 4. The defect level according to the number of performances (20 simulations).

Thus only 7 performances need to be tested instead of the 11 initial performances. This result is important, because it makes possible to specify the number of performances to be applied to the circuit under test for a tolerated value of the defect level while ensuring that all functional circuits pass the test. Thus we can draw up the Table II which summarizes the number of performances to be tested for 95% confidence interval of the defect level with the tolerance of specifications k = 4.3. TABLE II N UMBERS OF PERFORMANCES REQUIRED FOR A 95% CONFIDENCE INTERVAL OF THE DEFECT LEVEL .

Defect level (ppm) [0 , 1.10001] [0 , 3.0004] [1.0001 , 9.0012] [4.0004 , 17.002] [12.001 , 27.0029] [19.0014 , 42.0039] [28.0018 , 58.0045] [42.0022 , 75.0046] [57.0021 , 92.004] [73.0015 , 113.0026]

Number of performances 10 9 8 7 6 5 4 3 2 1

TABLE IV O RDER OF ELIMINATION OF THE PERFORMANCES .

B. Order of elimination

Order of elimination 1 2 3 4 5 6 7 8 9 10 11

Performance SR+ P SRR (GN D ) T HD CM RR GBW D P SRR (VDD ) Intermodulation AD IDD N oise P hase M argin

1000 900 800

Defect level (ppm)

From the results obtained, it appears clear that the order of elimination is also related to the actual tolerance of specifications k, which determines the specifications of each performance. We have applied the method for various values of the tolerance of specifications (k = 1.8, 2.3, 2.8, 3.3, 3.8, 4.3) and for each value, we have made 20 simulations of the test compaction method. At each one of these simulations we count the number of times that each performance is eliminated, with the characteristic that a performance eliminated at the beginning will be counted within each stage of elimination but a performance eliminated at the end of the method will be counted only once. The results of the simulations are summarized in Table III. For example, for k = 1.8, the performance AD is eliminated 65 times out of 200 (20 simulations with 10 possible eliminations at each simulation), the performance GBW D 120 times, until the last performance N oise, which count 21 eliminations (second column of the Table III).

700

- SR+ - PSRR GND - THD - CMRR - GBWD - PSRR VDD

600 500 400 300 200 100

TABLE III

0

TABLE OF THE NUMBER OF TIMES THAT EACH PERFORMANCE WAS ELIMINATED ACCORDING TO THE TOLERANCE OF SPECIFICATIONS k.

95

96

97

98

99

100

101

Yield (%)

Fig. 5.

The defect level according to the yield for various eliminations.

k Performance AD GBW D P hase M argin CM RR GN D VDD T HD IDD Intermodulation SR+ N oise

1.8 65 120 27 140 180 18 160 95 74 200 21

2.3 31 120 15 140 180 100 160 14 80 200 60

2.8 45 120 25 140 181 89 160 35 62 199 44

3.3 62 120 19 140 190 55 160 64 68 190 32

3.8 63 119 39 137 174 71 157 55 56 192 37

4.3 78 117 51 111 162 105 139 78 52 157 50

Mean 57.33 119.33 29.33 134.67 177.83 73 156 56.83 65.33 189.67 40.67

The order of elimination of the performances is clarified in table IV. The comparison between this order and the order of elimination of each simulation for k = 1.8, 2.3, 2.8, 3.3, 3.8, 4.3, showed that this order is the same for all simulations until the 6th performance eliminated and for the two last order elimination orders (10th and 11th ). On the other hand the order of the 7th to the 9th elimination differs slightly according to the value of the tolerance of specifications k.

enables us to choose the performances to be eliminated from the test as trade-off between the yield and the defect level. This result is interesting because it allows to characterize a procedure of test according to two criteria which are the yield and the defect level. For example, the elimination of the performance SR+, will produce a variation of the yield between 95% and 100% and a variation of the defect level until 150ppm for a variation of k between 1.3 and 3.8. VI. C ONCLUSION We have presented a method of functional test compaction for analogue circuits, based on the minimisation of the defect level at the design stage. A statistical model of the circuit under test is considered. The application of the method is shown through a numerical example, where the principal assets of the method are: •

C. Yield To calculate the yield (proportion of the functional circuits), we impose to the test compaction method the order of elimination previously established (see Table IV) until the 6th eliminated performance. For each value of the tolerance of specifications k, we execute 20 simulations at each stage of elimination (elimination of the first performance then of the two first until the elimination of the six performances). The results of this procedure are summarized on the graph of the Figure 5. This graph gives us the defect level according to the yield for various values of the tolerance of specifications. This

• •

To identify the performances to eliminate from the test for each tolerated value of the defect level, while making sure that all the functional circuits pass the test. To establish an order of elimination of the performances. To develop a procedure of test, based on the elimination of the performances as trade-off between the yield and the defect level.

Current work is directed towards the validation of the reduced test set under the presence of faults (both catastrophic and parametric) and the evaluation of fault coverage. This should be available in the final version of the paper. Future work will aim at removing the Gaussian assumption in the circuit statistical model and at exploring other statistical methods for the elimination of the performances.

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