Integer Programming for Partitioning in Software Oriented Codesign Markus Weinhardt Universitat Karlsruhe, Fakultat fur Informatik D{76128 Karlsruhe, Germany email:
[email protected] Published in Field-Programmable Logic and Applications: 5th International Workshop, Aug./Sept. 1995, Springer LNCS 975, pp. 227{234
Abstract
This paper presents a new partitioning method for software oriented hardware/software codesign. It is applied to the use of eld{programmable accelerator boards. In the underlying model the dedicated hardware has no direct access to the host memory, and communication is slow. Therefore detailed data{ ow information is necessary to minimize the communication overhead between host and accelerator board. The partitioning problem is formulated as an integer (linear) program which simultaneously determines which code regions should be implemented in dedicated hardware and which data has to be communicated, so that well{known optimization algorithms can be applied.
1 Introduction The goal of software oriented hardware/software codesign is to improve system performance by moving time-critical parts of a program to hardware. This approach is attracting increasing interest since it uses simple speci cations in common programming languages and allows the use of automatically designed dedicated hardware|especially eld{programmable hardware|in applications beyond embedded systems. So FPGA{ boards available for PCs or engineering workstations can be used to accelerate common programs. Figure 1 shows the general design ow. A pro ler determines time critical regions of the input program and average sizes of data structures used by these regions. This information is then used to determine a feasible hardware/software partitioning which maximizes the estimated speedup. The code of the regions to be implemented in hardware is transformed to an HDL speci cation which guides the synthesis of the corresponding circuit. The software part is processed by a conventional compiler, and the interface determines the synchronization and communication between hardware and software. This work has been supported by the Deutsche Forschungsgemeinschaft (DFG) within the Graduiertenkolleg \Beherrschbarkeit komplexer Systeme".
1
Program Pro ling Partitioning HDL
Interface
Synthesis
Software Compilation
Netlist
Code
Figure 1: Design ow We assume as a model of computation a coprocessor board with FPGAs and local memory connected to a host computer via the system bus. Host and board can communicate through the bus, but the board cannot directly access the host memory, and communication is slow. Our goal is to select those regions of the program which yield the highest speedup if moved to hardware. The computation of this partitioning should be ecient and it should consider the overhead of the required communication between host and coprocessor board. The limited host memory access places some restrictions on the regions which can be implemented in hardware, and means that data used in the hardware regions must be explicitly copied to the board. (We allocate scalar variables to FPGA registers and arrays to the local memory.) On the other hand the absence of memory access con icts allows operating the host and coprocessor board concurrently. Some commercially available boards (e.g. [1]) implement this model of communication. The following sections present a new partitioning method suitable for this model. We derive a linear cost function and linear constraints which de ne the partitioning problem formally as an integer program. Hence we can use the simplex and branch{and{bound optimization algorithms to compute the partitioning.
2 Preprocessing 2.1 Candidate Selection One of the most important issues in hardware/software partitioning is the selection of adequate candidates which should be considered for hardware implementation. There is a trade{o between the granularity of the candidate and the feasibility of the optimization 2
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