Testing High Speed Memory Interface - Silicon Valley Test Workshop

OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLy nx V8.0 Comment: 650MHz at clk input, J10, fixture attached 3000.0

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Date: W ednesday Mar. 3, 2010 Time: 14:16:09

Testing High Speed Memory Interface: A case for FPGA based Test systems ? Mathieu Duprez MuTest [email protected]

Agenda







Customer requirement Characterizing memory controllers HSMI solution Project rollup, Conclusion

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Customer requirement
Large majority of processors and SOC devices are interfacing with DDR2/3 memories through 1 or multiple embedded memory controllers
DEFT is commonly used to check controller functionality, however, functionality and Physical layer verification still requires Source sync ATE and/or strobe alignment prior to testing


In order to characterize precisely a SOC product line using a DDR3 interface and monitor its process, a customer wants to perform statistics on High Speed Memory Interface and gather Key parameters. Silicon Valley Test Conference 2011

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Characterizing memory controllers Memory requirement and DUT model
Write cycles: DUT Memory Controller

DQ’s Memory

Tdss

DQ’s DM

Tdsh

Tdqsh DQS

DQS

Tdqss CLK

Tdqsl

Tdsh

CLK_P CLK_N

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Characterizing memory controllers Tdqsh evaluation using Tester Synchronous ATE
Clocks are typical generated from DUT internal PLL/DLL. Tco is unknown
Before performing any functional test, a timing search is performed to find out where the clock seats. DQS, DQ timing are then set accordingly.
2 timing search are necessary to get Tdqsh
System and device Jitter is such that getting Tdqsh precisely is almost impossible Silicon Valley Test Conference 2011

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Characterizing memory controllers Tdqsh evaluation using Source Synchronous ATE
Tco is still unknown, but not an issue anymore
Functional test can be performed on Dqs as long as Delay line are set properly


1 timing search is necessary to get Tdqsh

DUT

Source Synchronous

Memory Controller DQ’s dly DQS

Tdqsh

Reference Clock

dly CLK dly

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Characterizing memory controllers HSMI Solution
Tester Synchronous solution does meet the timing accuracy requirement
In addition to its costs, Source Synchronous tester requires too much time. Statistics on 1000 search requires in the order of 1000 x 100us x 30 steps = 3 s per parameters Dedicated solution is required

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HSMI Solution Technical implementation

Data storage (DIMMs)

Services (Bus, sync, clocks)

Timing Generator Ch 1

Sequencer, Capture, Data generation

DUT interfacing (Pin electronic, conectivity)

Timing Generator Ch 0


Start from existing instrument (HW/FW)
Remove timing generators
Implement new FW

Timing Generator Ch n FPGA Boundarie


SS capability
Automatic cycle type detection
Φ(clk, ctrl) capability
Φ(clk, dqs) capability
Φ(dqs, dq’s) capability


Dedicated search & statistics within FPGA Silicon Valley Test Conference 2011

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HSMI Solution Technical implementation

Services (Bus, sync, clocks)

Sequencer, Capture, Data generation

DUT interfacing (Pin electronic, conectivity)

Data storage (DIMMs)


Start from existing instrument (HW/FW)
Remove timing generators
Implement new FW

FPGA Boundarie


SS capability
Automatic cycle type detection
Φ(clk, ctrl) capability
Φ(clk, dqs) capability
Φ(dqs, dq’s) capability


Dedicated search & statistics within FPGA Silicon Valley Test Conference 2011

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HSMI Solution Technical implementation

Data storage (DIMMs)

DQS

dly dly

CTRL

dly

CLK

dly

Services (Bus, sync, clocks)

dly

Sequencer, Capture, Data generation

dly Protocol analyser

DUT interfacing (Pin electronic, conectivity)

DQ’s


Start from existing instrument (HW/FW)
Remove timing generators
Implement new FW

DLL

FPGA Boundarie


SS capability
Automatic cycle type detection
Φ(clk, ctrl) capability
Φ(clk, dqs) capability
Φ(dqs, dq’s) capability


Dedicated search & statistics within FPGA Silicon Valley Test Conference 2011

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HSMI Solution Technical implementation

Data storage (DIMMs)

DQS

dly dly

CTRL

dly

CLK

dly

Services (Bus, sync, clocks)

dly

Sequencer, Capture, Data generation

dly Protocol analyser

DUT interfacing (Pin electronic, conectivity)

DQ’s


Start from existing instrument (HW/FW)
Remove timing generators
Implement new FW

DLL

FPGA Boundarie


SS capability
Automatic cycle type detection
Φ(clk, ctrl) capability
Φ(clk, dqs) capability
Φ(dqs, dq’s) capability


Dedicated search & statistics within FPGA Silicon Valley Test Conference 2011

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HSMI Solution Key features
Measure, characterize HSMI physical layer key parameters in less than 100ms








TDQSS, TDSS/H, TDSS, TDQSH, TDQSL, TDS, TDH, TDQSCK, TDQSQ …

Test time

Instrumentation (Oscilloscope)

1000 S.Sync ATE

100 10

Tester Sync ATE

HSMI

1

Accuracy 1

10

100

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HSMI Solution Key features
Engineering/debug environment providing help for analysis.

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HSMI Solution key project comparison FPGA Based instrument

Dedicated new instrument

From requirement to proven solution - Duration - Effort

4 months 8 pers. months

~ 15 months 24 to 50+ pers. month

$80K $20K

$250K to $3 000K >> $100K $20K

2 systems

10 systems

Development cost - Labor - prototyping - Validation tooling

Return On Investment

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Project Roll up - Conclusion
Density and functionalities embedded in modern FPGA enable building of wide variety of ATE instruments, from production to characterization systems
Furthermore, re configurability, development cost and cycle time make them perfect candidate to answer the increasing needs for dedicated solutions. Silicon Valley Test Conference 2011

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Thanks for your attention

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