Modeling of Crosstalk Delay and Noise in Single-walled ... - IEEE Xplore

2013 Annual IEEE India Conference (INDICON)

Modeling of Crosstalk Delay and Noise in Single-walled Carbon Nanotube Bundle Interconnects Manodipan Sahoo

Hafizur Rahaman

Department of Information Technology Bengal Engineering & Science University Shibpur, Howrah-711103, India Email: [email protected]

Department of Information Technology Bengal Engineering & Science University Shibpur, Howrah-711103, India Email: rahaman [email protected]

Abstract—In the proposed work, crosstalk effects are investigated in two identically coupled SWCNT bundle interconnects at 21 nm and 15 nm technology nodes for intermediate and global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse and dense SWCNT bundle interconnect system. The simulation results show that the proposed model is not only ∼100% accurate but also almost 6 times faster than SPICE. The worst case crosstalk induced delay and peak crosstalk noise voltages for SWCNT bundle interconnects are compared to those of conventional copper (Cu) interconnects at the intermediate as well as global level interconnects. Simulation results also confirm that dense SWCNTs are always ahead of sparse SWCNTs with respect to performance advantage numbers over copper for every levels of interconnects and irrespective of technology nodes. As far as the worst case peak crosstalk noise is concerned, there is a critical length after which the performance of the dense SWCNT bundles is better than that of its sparse counterpart. Simulation results also prove that dense SWCNT bundled interconnect is a potential alternative to Copper interconnects in future nanoscale integrated circuits with respect to performance as well as signal integrity issues. Keywords—Single-walled Carbon Nanotube (SWCNT) ; Interconnects ; Nanoscale ; Integrated circuit ; Intermediate ; Global ; Crosstalk ; ABCD parameter; Delay ; Noise ; SPICE.

which does’nt correctly model the intermediate and global interconnects of the nanometer regime. Crosstalk effects have been analysed for SWCNT bundle interconnect systems using SPICE like circuit simulators in [6], [7]. Multiequivalent single conductor (MESC) approach is used to analyse the crosstalk induced effects in SWCNT bundle interconnects in the frequency domain in [8]. In this work, we have used the concept of ABCD parameter matrix to accurately model the crosstalk delay and noise of two identically coupled SWCNT bundle interconnects at the intermediate and global level for the IC technology nodes of 21 nm and 15 nm [2], [9]-[11]. The rest of the paper is organized as follows. Section II briefly describes the equivalent RLC parameters of SWCNT bundle nanointerconnects. Section III discusses the proposed delay and crosstalk model. Section IV describes the crosstalk analysis results using our proposed model for various technology nodes and levels of interconnects. Finally the conclusions are drawn in section V. E QUIVALENT ELECTRICAL PARAMETERS OF SWCNT

II.

BUNDLE INTERCONNECT

I.

I NTRODUCTION

Process technology scaling has led to longer interconnects, faster edge rate signals, increase in the clock frequency and decrease in the separation between adjacent interconnects. Aggressive interconnect scaling also leads to significant coupling capacitance among adjacent interconnects. Add to this, due to the lower resistivity copper interconnects and higher operational frequencies, inductive impedance of the on-chip wires become comparable to or larger than the resistive impedance. Due to these reasons on chip capacitive and inductive effects play a major role in determining the signal integrity and performance of today’s copper based nano-interconnects [1]. So, traditional approaches of lumped or distributed RC model of interconnects are not adequate for delay and crosstalk prediction especially in intermediate and global wires in the nanometer regime. In [2], the investigation on a single distributed RLC line has been done without any consideration of coupling capacitances. Time domain expressions for output of capacitively coupled interconnects have been developed using the transmission line theory in [4]. However, the delay and crosstalk noise expressions ignore the effect of capacitive loading at the receiver end. Delay and crosstalk have been modeled in [3] for loosely coupled interconnects. In [5], the lumped parameter approximation is considered for crosstalk delay and noise estimation, This work is partially supported by the grant from DIT, Government of West Bengal, India under VLSI Design Project.

VIN

Equivalent RC circuit of the Inverting Buffer Distributed Line of length L Lumped Resistance Rf Rf Rs r.dx l.dx Vout Cout

C q .dx C e .dx

C

L

dx : infinitesimal section length Inverting Buffer

Fig. 1: Electrical equivalent model of a typical SWCNT bundle interconnect system.

A typical SWCNT bundle interconnect system is shown in Fig. 1. In Fig. 1, L is the interconnect length, 𝑅𝑓 is the lumped resistance (i.e., consists of nanotube-electrode contact resistance and quantum resistance), r is per unit length (p.u.l) resistance, l is p.u.l self inductance, 𝐶𝑞 is p.u.l quantum capacitance, 𝐶𝑒 is p.u.l electrostatic ground capacitance. The driver is implemented using inverting buffers and load is capacitive, denoted by 𝐶𝐿 . The buffers can be modeled as an equivalent RC circuit with a high degree of accuracy [2]. The parameters of the buffers are 𝑅𝑠 and 𝐶𝑜𝑢𝑡 . 𝑅𝑠 and 𝐶𝑜𝑢𝑡 are the equivalent switching resistance and the equivalent diffusion capacitance of

978-1-4799-2275-8/13/$31.00 ©2013 IEEE

a minimum sized inverter buffer. RC parameters of the driver and load inverting buffer are estimated using the device parameters from ITRS2011 roadmap [12]. The estimated parameters are shown in Table I. The technology parameters for various levels of copper interconnects are obtained from ITRS-2011 roadmap [12]. The analytical equations from [13] are used to calculate the distributed RLC parameters of copper interconnects. The analytical equations used to calculate the RLC parameters of SWCNT bundle interconnects are taken from [14][16].

and, matrix P is shown in (4). ⎡

1 0 ⎢ 𝑃 =⎣ 𝑠𝐶𝑞 (1 − 𝑔)𝑑𝑥 −𝑠𝐶𝑞 .𝑓.𝑑𝑥

0 1 −𝑠𝐶𝑞 .𝑓.𝑑𝑥 𝑠𝐶𝑞 (1 − 𝑔)𝑑𝑥

 node Technology  Parameters   𝑅𝑠 (in KΩ) 𝐶𝑜𝑢𝑡 (in fF)

21 nm

15 nm

34.45 0.049

47.4 0.03

Vi1

I

I

r.dx

i1

o1

⎡

−1 ⎢ 1 𝑉 =⎣ −𝑍

1

⎡ (1 + 𝜃1 𝑑𝑥) 0 ⎢ 𝑊 =⎣ 0 0

Vo1

l.dx C q .dx

C c .dx

net2 I

r.dx

i2

l.dx

I

Vo2 o2

C q .dx

1 1 𝑍2 𝑍2

⎤ 1 1 ⎥ −𝑍2 ⎦ −𝑍2

(5)

0 (1 − 𝜃1 𝑑𝑥) 0 0

0 0 (1 + 𝜃2 𝑑𝑥) 0

⎤ 0 0 ⎥ ⎦ 0 (1 − 𝜃2 𝑑𝑥)

𝑛

Φ𝑖 = 𝑃𝑑𝑟 𝑃𝑑𝑐 𝑃𝑅𝑓 𝑃 𝑃𝑅𝑓 𝑃𝑙𝑜𝑎𝑑 Φ𝑜

C e .dx

(6)

(10)

where, 𝑃𝑑𝑟 and 𝑃𝑑𝑐 are the ABCD matrices corresponding to 𝑅𝑠 and 𝐶𝑜𝑢𝑡 element of the driving buffer respectively, 𝑃𝑅𝑓 is the ABCD matrix of the lumped resistance 𝑅𝑓 , and 𝑃𝑙𝑜𝑎𝑑 is that of the capacitive load. By solving (10), the final output voltages 𝑉𝑜1 (s) and 𝑉𝑜2 (s) can be represented in terms of the inputs 𝑉𝑖1 (s) and 𝑉𝑖2 (s) in matrix form as shown in (11).

Fig. 2: Schematic diagram of an infinitesimal section of an identically coupled SWCNT bundle interconnect system.

[

III.

−1 1 𝑍1 −𝑍1

Here, 𝜃1 and 𝜃2 are the propagation constants of the decoupled interconnects and, 𝑍1 and 𝑍2 are the characteristic impedances of the decoupled interconnects. These parameters are defined as√follows: √ √ (𝑟+𝑠𝑙) 𝜃1 = 𝑠(𝛼.𝐶𝑞 )(𝑟 + 𝑠𝑙) , 𝜃2 = 𝑠(𝛽.𝐶𝑞 )(𝑟 + 𝑠𝑙), 𝑍1 = 𝑠(𝛼.𝐶𝑞 ) √ (𝑟+𝑠𝑙) and 𝑍2 = 𝑠(𝛽.𝐶𝑞 ) . Here, 𝑑𝑥 = 𝐿/𝑛 where, n is the number of infinitesimal sections. Other parameters are defined as, 𝛼 = (1 + 𝑓 − 𝑔) 𝐶𝑐 𝑎 𝑏 and 𝛽 = (1 − 𝑓 − 𝑔) where, 𝑓 = (𝑏2 −𝑎 2 ) and 𝑔 = (𝑏2 −𝑎2 ) with 𝑎 = 𝐶𝑞 𝐶𝑒 +𝐶𝑞 +𝐶𝑐 𝑛 −1 𝑛 𝑛 −1 and 𝑏 = . Using, 𝑃 = (𝑉 𝑊 𝑉 ) = (𝑉 𝑊 𝑉 ) and 𝐶𝑞 the identity, lim𝑛→+∞ (1 + 𝑛𝑥 )𝑛 → 𝑒𝑥 , 𝑃 𝑛 can be written as shown in (7), where, 𝑡𝑎 = cosh(𝐿𝜃1 ) , 𝑡𝑏 = cosh(𝐿𝜃2 ) , 𝑡𝑐 = sinh(𝐿𝜃1 ) and 𝑡𝑑 = sinh(𝐿𝜃2 ) . The final Kirchoff equation for the coupled interconnects can be written as,

C e .dx Vi2

(4)

and, W is a diagonal matrix shown in (6).

Infinitesimal section of a distributed line

net1

⎤ 0 (𝑟 + 𝑠𝑙)𝑑𝑥⎥ ⎦ 0 1

The matrix P can be diagonalized as 𝑃 = 𝑉 𝑊 𝑉 −1 , where,

𝑍1

TABLE I: RC parameters of the minimum sized buffer

(𝑟 + 𝑠𝑙)𝑑𝑥 0 1 0

P ROPOSED M ODEL FOR ANALYSIS OF CROSSTALK EFFECTS

] [1 (𝐻1 (𝑠) + 𝐻2 (𝑠)) 𝑉𝑜1 (𝑠) = 12 𝑉𝑜2 (𝑠) 2 (𝐻1 (𝑠) − 𝐻2 (𝑠))

1 2 (𝐻1 (𝑠) 1 2 (𝐻1 (𝑠)

][ ] − 𝐻2 (𝑠)) 𝑉𝑖1 (𝑠) + 𝐻2 (𝑠)) 𝑉𝑖2 (𝑠)

(11)

In this work, an efficient computational model for crosstalk analysis in identically coupled SWCNT bundle interconnect systems is presented. The model is also compared with SPICE. In our proposed methodology first, we develop an analytical expression for the crosstalk delay and noise in laplace domain. Then we adopt the inverse laplace transform to find out the time-domain response of the crosstalk delay and noise. Our methodology of crosstalk estimation is as accurate as SPICE but computationally much faster. The proposed methodology is illustrated as follows.

The exact expressions of 𝐻1 (s) and 𝐻2 (s) in (11) are shown in (8)and (9) respectively. Where, 𝐴 = (1+𝑠𝑅𝑠 𝐶𝑜𝑢𝑡 ) and 𝐵 = (𝑅𝑠 +𝐴𝑅𝑓 ) . 𝐻1 (s) and 𝐻2 (s) are the transfer functions of the decoupled interconnects. The transfer function for the crosstalk delay or noise evaluation in the victim net will be denoted as H(s) throughout the paper. H(s) can be derived from (11) for different evaluation conditions (i.e., crosstalk delay and noise). We consider a seventh-order Pad´ 𝑒 expansion for approximating hyperbolic functions in (8)and (9) with high degree of accuracy [2]. So the transfer function H(s) will be of the form given in (12) after the Pad´ 𝑒 expansion:

ABCD parameter based approach:

𝐻(𝑠) =

An infinitesimal lumped RLC section of an identically coupled SWCNT bundle interconnect system is shown in Fig.2. The Kirchhoff equation for an infinitesimally small segment of these two identically coupled interconnects is given by the following equation [10], 𝜙 𝑖 = 𝑃 𝜙𝑜

(1)

1 1 + 𝑠𝑏1 + 𝑠2 𝑏2 + 𝑠3 𝑏3 + 𝑠4 𝑏4 + 𝑠5 𝑏5 + 𝑠5 𝑏5 + 𝑠6 𝑏6 + 𝑠7 𝑏7 (12) where, the coefficients are shown below, 𝑏1 =

𝐿2 𝑟𝐶 + 𝑅𝑠 (𝐶𝑜𝑢𝑡 + 𝐶𝐿 ) + 2𝑅𝑓 𝐶𝐿 + (𝑅𝑠 + 𝑅𝑓 )𝐿𝐶 + 𝐿𝐶𝐿 𝑟 2

𝐿2 𝑙𝐶 𝐶 𝐿 𝐿3 𝑟 2 𝐶 𝐿4 𝑟 2 𝐶 2 + 𝐶𝐿 𝐿𝑙 + + 2 6 24 (𝑅𝑠 + 𝑅𝑓 )𝑟𝐿3 𝐶 2 𝐿2 𝑟𝐶(𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 2𝑅𝑓 𝐶𝐿 ) + + 2 6 𝐿𝑅𝑓 𝐶(𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 2𝑅𝑓 𝐶𝐿 ) + 𝐿𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 𝑟

(13)

𝑏2 = 2𝑅𝑓 𝑅𝑠 𝐶𝑜𝑢𝑡 𝐶𝐿 +

where, 𝜙𝑖

= [𝑉𝑖1 , 𝑉𝑖2 , 𝐼𝑖1 , 𝐼𝑖2 ]𝑇

(2)

𝜙𝑜

= [𝑉𝑜1 , 𝑉𝑜2 , 𝐼𝑜1 , 𝐼𝑜2 ]𝑇

(3)

(14)

⎡

𝑃

𝐻1 (𝑠) 𝐻2 (𝑠)

𝑛

= =

( 𝑡𝑎 2 ⎢ ( 𝑡𝑎 ⎢ = ⎣ 𝑡𝑐2 ( 2𝑍1 𝑡𝑐 ( 2𝑍1

+ − + −

𝑡𝑏 2 ) 𝑡𝑏 2 ) 𝑡𝑑 2𝑍2 ) 𝑡𝑑 2𝑍2 )

( 𝑡𝑎 2 − ( 𝑡𝑎 2 + 𝑡𝑐 ( 2𝑍1 − 𝑡𝑐 ( 2𝑍1 +

𝑡𝑏 2 ) 𝑡𝑏 2 ) 𝑡𝑑 2𝑍2 ) 𝑡𝑑 2𝑍2 )

( 𝑡𝑐.𝑍1 2 ( 𝑡𝑐.𝑍1 2 ( 𝑡𝑎 2 ( 𝑡𝑎 2

+ − + −

𝑡𝑑.𝑍2 ) 2 𝑡𝑑.𝑍2 ) 2 𝑡𝑏 2 ) 𝑡𝑏 2 )

( 𝑡𝑐.𝑍1 2 ( 𝑡𝑐.𝑍1 2 ( 𝑡𝑎 2 ( 𝑡𝑎 2

− + − +

⎤

𝑡𝑑.𝑍2 ) 2 𝑡𝑑.𝑍2 ⎥ )⎥ 2 𝑡𝑏 ⎦ 2 ) 𝑡𝑏 ) 2

1 (𝐴(1 + 𝑠𝐶𝐿 𝑅𝑓 ) + 𝑠𝐶𝐿 𝐵) cosh(𝜃1 𝐿) + ( 𝑍𝐵 (1 + 𝑠𝐶𝐿 𝑅𝑓 ) + 𝐴𝑠𝐶𝐿 𝑍1 ) sinh(𝜃1 𝐿) 1

(7)

(8)

1

(𝐴(1 + 𝑠𝐶𝐿 𝑅𝑓 ) + 𝑠𝐶𝐿 𝐵) cosh(𝜃2 𝐿) + ( 𝑍𝐵 (1 + 𝑠𝐶𝐿 𝑅𝑓 ) + 𝐴𝑠𝐶𝐿 𝑍2 ) sinh(𝜃2 𝐿)

(9)

2

IV.

TABLE II: Crosstalk delay comparison in intermediate level interconnects in 21 𝑛𝑚 node.

The proposed analytical model is implemented using MATLAB 7.1 under standard desktop environment on Intel Core 2 Duo Chip running at 3.0 GHz with 4.0 GB of physical memory. The simulation is performed in various technology nodes namely 21 nm and 15 nm and various interconnect levels. We have chosen the inverter buffer size to be 100 times the minimum sized buffer for global and 50 times the minimum sized buffer for intermediate interconnects. The capacitive load is considered to be 100 fF for all the simulations. SWCNT bundles are considered to be consisting of 1 nm fixed diameter sparse SWCNTs (with metallic fraction=1/3) and metallic electrode-nanotube contact resistance (𝑅𝑐 ) of 100 KΩ [16].

𝑇 1𝑃 𝐿𝐻 (ns) 𝑇 2𝑃 𝐿𝐻 (ns) SPICE Model % diff SPICE Model % diff 10 𝜇m 0.104 0.103 0.96 0.104 0.103 0.96 50 𝜇m 0.129 0.128 0.77 0.131 0.13 0.76 100 𝜇m 0.16 0.159 0.625 0.165 0.164 0.6 500 𝜇m 0.428 0.426 0.47 0.48 0.478 0.42 1 mm 0.81 0.807 0.37 0.984 0.978 0.61 Average simulation time in SPICE is ∼61 sec and our model takes ∼11.5 sec. So our model is in average ∼5.3 times faster than SPICE. Length

𝐿2 𝑙𝐶(𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 2𝑅𝑓 𝐶𝐿 ) 2 + 𝐶𝑟𝐿 𝑅𝑠 𝑅𝑓 𝐶𝑜𝑢𝑡 𝐶𝐿 + 2 𝐶 2 𝑟 2 𝐿4 (𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 2𝑅𝑓 𝐶𝐿 ) 𝐶 2 𝑟𝑙𝐿4 + 𝑙𝐿𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 12 24 𝐶 2 𝑟𝐿3 𝑅𝑓 (𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 𝑅𝑓 𝐶𝐿 ) 2 + 𝐶𝐿𝐶𝐿 𝑅𝑓 𝑅𝑠 𝐶𝑜𝑢𝑡 + + 6 𝐶𝑟𝑙𝐶𝐿 𝐿3 𝐶𝑙𝐿3 𝐶 2 𝑟 2 𝐿5 𝐶𝑟 2 𝐿3 𝑅𝑓 𝐶𝐿 𝐶𝑜𝑢𝑡 + +( + ) 6 6 6 120 (𝐶(𝑅𝑠 + 𝑅𝑓 ) + 𝑟𝐶𝐿 )

R ESULTS AND D ISCUSSIONS

𝑏3 =

A. SPICE Simulation procedure (15)

We have chosen the Spectre simulator version IC 6.1.4.500 of Cadence and found out the noise and delay values. Simulations are run in the same environment where MATLAB simulations are run. RC parameters of the driver/load inverting buffer are taken from Table(I). Because of the distributed nature of the interconnects, we implement that by cascading 200 infinitesimal lumped RLC sections [17]. B. Results of Crosstalk delay analysis

𝐶 2 𝑙 2 𝐿4 𝐶 2 𝑟 2 𝐿4 (𝑅𝑠 𝐶𝑜𝑢𝑡 𝑅𝑓 𝐶𝐿 ) + + 24 12 𝐶𝑟𝑙𝐶𝐿 𝐿3 𝑅𝑠 𝐶𝑜𝑢𝑡 𝐶 2 𝑟𝑙𝐿4 (𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 2𝑅𝑓 𝐶𝐿 ) + + 12 6 𝐶 2 𝑟𝐶𝐿 𝐿3 (𝑅𝑠 𝐶𝑜𝑢𝑡 𝑅𝑓2 ) 𝐶 2 𝑟𝑙𝐿5 + (𝐶(𝑅𝑠 + 𝑅𝑓 ) + 𝑟𝐶𝐿 )+ 6 60 𝐶𝑙𝐿3 𝐶 2 𝑟 2 𝐿5 ( + )(𝐶𝑅𝑓 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝐶𝑅𝑓 𝐶𝐿 (𝑅𝑠 + 𝑅𝑓 )+ 6 120 𝑟𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑙𝐶𝐿 )

(16)

𝐶 2 𝑙 2 𝐿4 𝐶𝑙𝐿3 (𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑅𝑠 𝐶𝐿 + 2𝑅𝑓 𝐶𝐿 ) + ( + 24 6 2 5 𝑟𝑙𝐿 𝐶 𝐶 2 𝑟 2 𝐿5 2 )(𝐶𝑅𝑓 𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑙𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 ) + + 120 60 𝐶 2 𝑟𝑙𝐿4 (𝑅𝑠 𝐶𝑜𝑢𝑡 𝑅𝑓 𝐶𝐿 ) (𝐶𝑅𝑓 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝐶𝑅𝑓 𝐶𝐿 (𝑅𝑠 + 𝑅𝑓 )+ 6 𝐶 2 𝑙 2 𝐿5 (𝐶(𝑅𝑠 + 𝑅𝑓 ) + 𝑟𝐶𝐿 ) 𝑟𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑙𝐶𝐿 ) + 120

(17)

𝐶 2 𝑙2 𝐿4 (𝑅𝑠 𝐶𝑜𝑢𝑡 𝑅𝑓 𝐶𝐿 ) 𝐶 2 𝑟𝑙𝐿5 2 + (𝐶𝑅𝑓 𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 12 60 𝐶 2 𝑙 2 𝐿5 𝑙𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 ) + (𝐶𝑅𝑓 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝐶𝑅𝑓 𝐶𝐿 (𝑅𝑠 + 𝑅𝑓 )+ 120 𝑟𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑙𝐶𝐿 )

(18)

2

𝑏4 = 𝐶𝑙𝐿 𝑅𝑠 𝑅𝑓 𝐶𝑜𝑢𝑡 𝐶𝐿 +

𝑏5 =

Table II, III, IV and V show the crosstalk delay values for various technology nodes and interconnect levels in two identical SWCNT bundle interconnect system. Our model is in an average 6 times faster as compared to SPICE with accuracy within ∼3.16% of SPICE. We have calculated the delay values due to the crosstalk for two cases : (a) 𝑇 1𝑃 𝐿𝐻 : when aggressor and victim nets switch in the same direction, from low to high, and (b) 𝑇 2𝑃 𝐿𝐻 : when aggressor and victim nets switch in the opposite direction, victim net switches from low to high and aggressor nets switch from high to low. Fig. 3(a) shows crosstalk delay waveforms as obtained by SPICE simulations and proposed model when the nets switch in opposite direction. The difference of the waveforms are shown in Fig. 3(b). C. Results of Crosstalk noise analysis Table VI, VII, VIII and IX show the crosstalk noise values for various technology nodes and level of interconnects in two identically

𝑏6 =

𝑏7 =

𝐶 2 𝑙 2 𝐿5 2 (𝐶𝑅𝑓 𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 + 𝑙𝐶𝐿 𝑅𝑠 𝐶𝑜𝑢𝑡 ) 120

TABLE III: Crosstalk delay comparison in intermediate level interconnects in 15 𝑛𝑚 node. (19)

Similarly, 𝐻2 (s) can be represented in a form as given in (12). The parameter C in the coefficients 𝑏1 to 𝑏7 varies according to the transfer function of the decoupled interconnect and it is represented as 𝛼𝐶𝑞 and 𝛽𝐶𝑞 in 𝐻1 (𝑠) and 𝐻2 (𝑠) respectively. The other parameters are basically the distributed parameters of the copper interconnect, length of the interconnect, driver and load RC parameters.

𝑇 1𝑃 𝐿𝐻 (ns) 𝑇 2𝑃 𝐿𝐻 (ns) SPICE Model % diff SPICE Model % diff 10 𝜇m 0.171 0.17 0.58 0.172 0.171 0.58 50 𝜇m 0.217 0.216 0.46 0.22 0.219 1.36 100 𝜇m 0.275 0.274 0.36 0.283 0.282 0.35 500 𝜇m 0.775 0.774 0.13 0.866 0.862 0.46 1 mm 1.48 1.48 0 1.79 1.78 0.56 Average simulation time in SPICE is ∼60.8 sec and our model takes ∼10 sec. So our model is in average ∼6 times faster than SPICE. Length

1

0.3515 Vin2 Vo2 using SPICE Vo2 using Model

0.9

0.351

0.7

Voltage(V) −−−>

Voltage(V) −−−>

0.8

0.6 0.5 0.4 0.3

Vo2 using SPICE Vo2 using Model

Zoomed in portion

0.3505

0.35

0.3495

0.2 0.1 0 0

0.349 5

10 Time(ns ) −−−>

15

20

0.89

0.895

(a)

0.9 0.905 Time(ns ) −−−>

0.91

0.915

(b)

Fig. 3: Crosstalk delay waveform for 2 mm long sparse SWCNT bundle interconnect in 15 nm technology node. (a)Crosstalk delay waveform as obtained from SPICE and proposed model when aggressor and victim nets switch in opposite direction. (b)Zoomed crosstalk delay waveform.

0.04

0.0375 Vo2 using SPICE Vo2 using Model

0.035

Vo2 using SPICE Vo2 using Model 0.037

0.025

Zoomed in portion

Voltage(V) −−−>

Voltage(V) −−−>

0.03

0.02 0.015 0.01

0.0365

0.036

0.0355

0.005 0.035 0 0

5

10 Time(ns ) −−−>

15

20

0.55

(a)

0.6

0.65

0.7 0.75 Time(ns ) −−−>

0.8

0.85

0.9

(b)

Fig. 4: Crosstalk noise waveform for 2 mm long sparse SWCNT bundle interconnect in 15 nm technology node. (a)Crosstalk noise waveform as obtained from SPICE and proposed model when victim net remains quiet at ground and aggressor nets switch. (b)Zoomed crosstalk noise waveform.

TABLE IV: Crosstalk delay comparison in global level interconnects in 21 𝑛𝑚 node. Length 100 𝜇m 500 𝜇m 1 mm 1.5 mm 2 mm

SPICE 0.0475 0.103 0.182 0.272 0.373

𝑇 1𝑃 𝐿𝐻 (ns) Model 0.046 0.102 0.18 0.27 0.37

% diff 3.16 0.97 1.1 0.74 0.8

SPICE 0.0488 0.114 0.216 0.34 0.486

𝑇 2𝑃 𝐿𝐻 (ns) Model 0.048 0.113 0.214 0.337 0.482

% diff 1.64 0.88 0.93 0.88 0.82

Average simulation time in SPICE is ∼59.9 sec and our model takes ∼13 sec. So our model is in average ∼ 4.6 times faster than SPICE.

coupled SWCNT bundle interconnect system. Our model has accuracy within ∼1.38% of SPICE and in an average 6 times faster than SPICE. We have calculated various noise parameters to characterize the crosstalk induced noise. These parameters include Noise peak amplitude(NP), Noise width(NW) and Noise Area(NA). NA is calculated as, 𝑁 𝐴 = 12 𝑁 𝑃 × 𝑁 𝑊 . In all these simulations, the victim net remains at low and aggressor nets switch from low to high, thus inducing a noise in the victim net. Fig. 4(a) shows crosstalk noise

TABLE V: Crosstalk delay comparison in global level interconnects in 15 𝑛𝑚 node. 𝑇 1𝑃 𝐿𝐻 (ns) 𝑇 2𝑃 𝐿𝐻 (ns) SPICE Model % diff SPICE Model % diff 100 𝜇m 0.0775 0.077 0.65 0.0795 0.079 0.63 500 𝜇m 0.183 0.182 0.55 0.202 0.201 0.5 1 mm 0.334 0.332 0.6 0.393 0.391 0.51 1.5 mm 0.504 0.501 0.6 0.626 0.621 0.8 2 mm 0.694 0.69 0.58 0.899 0.892 0.78 Average simulation time in SPICE is ∼58.8 sec and our model takes ∼9 sec. So our model is in average ∼6.5 times faster than SPICE. Length

waveforms as obtained by SPICE simulations and proposed model. It can be observed that the waveforms obtained using SPICE and the proposed model is nearly the same. The difference of the waveforms is better shown in the Fig. 4(b). D. Worst case Crosstalk delay analysis Performance improvement using SWCNT bundles is evident in both Fig.5 and Fig.6. At the smaller interconnect length, the worst case crosstalk delay ratio (i.e., ratio of copper wire delay to SWCNT

TABLE VI: Crosstalk noise comparison in intermediate level interconnects in 21 𝑛𝑚 node. NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 10 𝜇m 0.466 0.466 0.803 0.809 0.187 0.188 -0.54 50 𝜇m 2.225 2.22 0.982 0.987 1.09 1.09 0 100 𝜇m 4.248 4.23 1.21 1.22 2.57 2.57 0 500 𝜇m 17.33 17.2 3.25 3.24 28.1 27.9 0.71 1 mm 30.19 29.9 6.26 6.23 94.6 93.3 1.37 Average simulation time in SPICE is ∼58 sec and our model takes ∼11.5 sec. So our model is in average ∼5 times faster than SPICE. Length

TABLE VII: Crosstalk noise comparison in intermediate level interconnects in 15 𝑛𝑚 node. Length 10 𝜇m 50 𝜇m 100 𝜇m 500 𝜇m 1 mm Average

NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 0.38 0.38 1.3 1.31 0.248 0.249 -0.4 1.81 1.81 1.63 1.64 1.48 1.49 -0.68 3.482 3.47 2.07 2.07 3.6 3.59 0.28 14.38 14.2 5.87 5.86 42.2 41.8 0.95 25.34 25.1 11.5 11.4 145 143 1.38 simulation time in SPICE is ∼58.75 sec and our model takes ∼10 sec. So our model is in average ∼6 times faster than SPICE.

Worst case Crosstalk delay ratio: Delay(Cu)/Delay(SWCNT)−−−>

bundle delay) is small due to the effect of lumped resistance component 𝑅𝑓 dominating the delay. However the worst case crosstalk delay ratio attains a maximum value of ∼22 and ∼29 in 21 nm and 15 nm technology node respectively for both the intermediate and global level dense SWCNT bundle interconnects. Whereas, the maximum worst case crosstalk delay ratios are ∼9 and ∼11 in 21 nm and 15 nm technology node respectively for the intermediate and global level sparse SWCNT bundle interconnects. The ratios are smaller for sparse SWCNT bundles due to higher resistivity of it compared to its dense counterpart. Performance advantages of both sparse and dense SWCNT bundles are achieved due to its lesser per unit length resistance than copper. 40 35 30

21 nm: SWCNT(Pm=0.33) 21 nm: SWCNT(Pm=1.0) 15 nm: SWCNT(Pm=0.33) 15 nm: SWCNT(Pm=1.0)

25 20 15 10 5 0 0

200

400

600

800

1000

Length of interconnect(in um )−−>

Fig. 5: Crosstalk Delay comparison in intermediate level interconnects E. Worst case Crosstalk noise analysis From Fig.7 and Fig.8, it is observed that the worst case peak crosstalk noise voltage is lesser in case of SWCNT bundles compared to copper in all cases. For 1 mm long intermediate level dense SWCNT bundle interconnects, the worst case peak crosstalk noise voltage ratio (i.e., ratio of peak noise of copper and SWCNT bundles)

TABLE VIII: Crosstalk noise comparison in global level interconnects in 21 𝑛𝑚 node. Length 100 𝜇m 500 𝜇m 1 mm 1.5 mm 2 mm Average

NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 3.917 3.9 0.372 0.373 0.729 0.727 0.27 15.713 15.6 0.784 0.784 6.16 6.12 0.65 26.83 26.6 1.39 1.38 18.6 18.4 1.08 35.77 35.6 2.09 2.08 37.4 37 1.07 43.25 43.1 2.89 2.87 62.6 61.8 1.28 simulation time in SPICE is ∼59.5 sec and our model takes ∼13 sec. So our model is in average ∼ 4.6 times faster than SPICE.

TABLE IX: Crosstalk noise comparison in global level interconnects in 15 𝑛𝑚 node. NP(mV) NW(ns) NA(V-ps) SPICE Model SPICE Model SPICE Model % diff 100 𝜇m 3.16 3.15 0.6 0.603 0.947 0.949 -0.21 500 𝜇m 12.81 12.7 1.39 1.39 8.93 8.85 0.9 1 mm 22.187 22 2.55 2.54 28.3 28 1.06 1.5 mm 29.94 29.7 3.89 3.86 58.2 57.4 1.38 2 mm 36.53 36.4 5.4 5.35 98.6 97.3 1.32 Average simulation time in SPICE is ∼61 sec and our model takes ∼9 sec. So our model is in average ∼ 6.8 times faster than SPICE. Length

is 2.8 for both the 21 nm and 15 nm technology nodes. For 2 mm long dense global interconnects, the ratios are 3.6 and 3.5 respectively for 21 nm and 15 nm nodes. For the smaller intermediate and global level interconnects at both the technology nodes, the peak crosstalk noise voltage ratios are higher for sparse bundles whereas the dense bundles show higher ratios at larger intermediate and global level interconnects. There is a certain critical length after which the dense SWCNT bundles start showing higher crosstalk noise voltage ratios (i.e., lesser noise contribution from SWCNT bundles) than its sparse counterpart. At smaller interconnect lengths, the Coupling Ratio (i.e., 𝑐 .𝑙 ) for both dense and sparse SWCNT bundles C.R.= 𝐶𝐿 +𝐶𝐶 𝑜𝑢𝑡 +𝐶𝑒𝑞 .𝑙 are almost the same due to the dominance of the capacitive load, 𝐶𝐿 compared to all other capacitive components, whereas they have different time constants (i.e., 𝜏 = (𝑅𝑠 + 𝑅𝑓 + 𝑟.𝑙)(𝐶𝐿 + 𝐶𝑜𝑢𝑡 + 𝐶𝑒𝑞 .𝑙). Here, equivalent electrostatic ground capacitance (𝐶𝑒𝑞 ) of the 𝐶 .𝐶 SWCNT bundle is expressed as, 𝐶𝑒𝑞 = (𝐶𝑞𝑞+𝐶𝑒𝑒 ) . It is well known that faster systems introduce more crosstalk noise than slower ones if the coupling ratio remains the same [18]. As dense bundles are slightly faster than sparse ones at smaller lengths, they introduce more noise leading to smaller peak crosstalk noise voltage ratio. For long interconnects however coupling ratio differs and the ratio is smaller for dense ones than its sparse counterpart. Though the dense bundles are faster than sparse ones, the crosstalk noise contribution at the far end of long interconnects however is entirely decided by the coupling ratio [18], thus leading to smaller worst case crosstalk noise for dense bundles. So dense SWCNT bundles can be used as a potential alternative interconnect fabric as a replacement for long intermediate and global Cu interconnects. V.

C ONCLUSIONS

In this work, an analytical model for crosstalk induced delay and noise has been presented for two identically coupled SWCNT bundle interconnect systems for various technology nodes in the nanometer era. The result shows that our proposed model is almost 100% accurate and in an average ∼6 times faster than SPICE. It has been shown that the crosstalk noise peak reduces as we move towards scaled technology nodes but noise width increases with scaling. It has

21 nm: SWCNT(Pm=0.33) 21 nm: SWCNT(Pm=1.0) 15 nm: SWCNT(Pm=0.33) 15 nm: SWCNT(Pm=1.0)

30 25 20 15 10 5 0 0

500

1000

1500

2000

Length of interconnect(in um )−−>

Peak Crosstalk noise voltage ratio: NP(Cu)/NP(SWCNT)−−−>

Fig. 6: Crosstalk Delay comparison in global level interconnects

3.4

21 nm: SWCNT(Pm=0.33) 21 nm: SWCNT(Pm=1.0) 15 nm: SWCNT(Pm=0.33) 15 nm: SWCNT(Pm=1.0)

3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 0

200

400

600

800

1000

Length of interconnect(in um )−−>

Fig. 7: Crosstalk noise peak voltage comparison in intermediate level interconnects

also been observed that the noise area increases with scaling which is a concern for the overall signal integrity in nanometer technology nodes. All the noise parameters increase with the length of the interconnect. It is also been observed that the crosstalk delay increases monotonically with the interconnect length and technology scaling. The worst case crosstalk induced delay and peak crosstalk noise voltages for SWCNT bundle interconnects are also compared to those of traditional copper interconnects. It is observed that dense SWCNT bundles have better performance advantage numbers than sparse SWCNT bundles at all levels of interconnects and technology nodes. As far as the worst case peak crosstalk noise voltage is concerned, there is a critical length after which dense SWCNT bundles perform better than its sparse counterpart. So from the performance and signal integrity point of view, dense SWCNT bundle is a potential alternative to copper interconnects for future Integrated Circuit technology nodes. R EFERENCES [1] E. E. Davidson, B. D. McCredie, and W. V. Vilkelis, “Long lossy lines (𝐿3 ) and their impact upon large chip performance,” IEEE Trans. Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, vol. 20, pp. 361-375, Nov. 1998. [2] Kaustav Banerjee and Amit Mehrotra, “Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects”, IEEE TCAD, vol. 21(8), pp. 904-915, 2002. [3] K. T. Tang and E. G. Friedman, “Peak Crosstalk Noise Estimation in CMOS VLSI Circuits”, IEEE ICECS, pp. 1539-1542, September 1999.

Peak Crosstalk noise voltage ratio: NP(Cu)/NP(SWCNT)−−−>

Worst case Crosstalk delay ratio: Delay(Cu)/Delay(SWCNT)−−−>

35

4

21 nm: SWCNT(Pm=0.33) 21 nm: SWCNT(Pm=1.0) 15 nm: SWCNT(Pm=0.33) 15 nm: SWCNT(Pm=1.0)

3.8

3.6

3.4

3.2

3 0

500

1000

1500

2000

Length of interconnect(in um )−−>

Fig. 8: Crosstalk noise peak voltage comparison in global level interconnects

[4] J. A. Davis and James D. Meindl, “Compact distributed RLC interconnect models-Part II. Coupled line transient expressions and peak crosstalk in multilevel networks,” IEEE Trans. Electron. Devices, vol. 47, pp. 20782087, Nov. 2000. [5] Debaprasad Das and Hafizur Rahaman, “Unified Model for Analyzing Timing Delay and Crosstalk Effects in Carbon Nanotube Interconnects”, IEEE ASQED, pp. 100-109, 2012. [6] Kailiang Zhang, Bo Tian, Xiaosong Zhu, Fang Wang and Jun Wei, “Crosstalk analysis of carbon nanotube bundle interconnects”, Springer Nanoscale Research Letters, 2012, 7:138. [7] S. N. Pu, W. Y. Yin, J. F. Mao and Q. H. Liu, “Crosstalk prediction of single- and double-walled carbon-nanotube (SWCNT/DWCNT) bundle interconnects,” IEEE Trans. Electron Devices, vol. 56, no. 4, pp. 560-568, Apr. 2009. [8] M. D´′ Amore, M. S. Sarto and A. Tamburrano, “Fast transient analysis of next-generation interconnects based on carbon nanotubes,” IEEE Trans. Electromagn. Compat, vol. 52, no. 2, pp. 496-503, May 2010. [9] A.K.Palit, V.Meyer, W.Anheier, J.chloeffel, “ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips”, IEEE 18th International Conference on VLSI Design, 2005. [10] Junmou Zhang and Eby G. Friedman, “Decoupling Technique and Crosstalk Analysis for Coupled RLC Interconnects”, IEEE ISCAS, pp. 521-524, 2004. [11] Sourajeet Roy and Anestis Dounavis, “Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1481-1492, Oct. 2009. [12] International Technology Roadmap for Semiconductors (ITRS-2011) Reports, [Online]. Available: http://www.itrs.net/reports.html. [13] Predictive Technology Model [Online]. Available: http://ptm.asu.edu/. [14] P. J. Burke, “Luttinger Liquid Theory as a Model of the Gigahertz Electrical Properties of Carbon Nanotubes”, IEEE Trans. Nanotechnology, Vol. 1, No. 3, pp. 129-144, 2002. [15] A. Raychowdhury and K. Roy, “Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies,” IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 25, no. 1, pp. 5865, Jan. 2006. [16] N. Srivastava and K. Banerjee, “Performance analysis of carbon nanotube interconnects for VLSI applications”, Proc. IEEE/ACM ICCAD, Nov. 2005, pp. 383-390. [17] T. Sakurai, “Approximation of Wiring Delay in MOSFET LSI,” IEEE JSSC, Vol. SC-18, No. 4, Aug. 1983. [18] O. Milter and A. Kolodny, “Crosstalk Noise Reduction in Synthesized Digital Logic Circuits,” IEEE Trans. on VLSI Systems, Vol. 11, No. 6, Dec. 2003.