Modified space vector modulation for fault-tolerant ... - IEEE Xplore

www.ietdl.org Published in IET Power Electronics Received on 29th September 2012 Revised on 15th January 2013 Accepted on 23rd January 2013 doi: 10.1049/iet-pel.2012.0543

ISSN 1755-4535

Modified space vector modulation for fault-tolerant operation of multilevel cascaded H-bridge inverters Mohsen Aleenejad, Hossein Iman-Eini, Shahrokh Farhangi School of Electrical and Computer Engineering, College of Engineering, University of Tehran, P.O. Box 14395-515, North Kargar Street, Tehran, Iran E-mail: [email protected]

Abstract: In this study, fault-tolerant operation of multilevel cascaded H-bridge (CHB) inverters is presented and a novel switching strategy based on space vector modulation is proposed. A faulty power switch in high power converters can lead to expensive downtime, loss of productivity and increased costs. Various power switch faults and their influence on space vector diagram of CHB inverters are investigated. In the event of a fault, the output voltage of inverter is reduced and redundant switching states are used to generate balanced line-to-line voltages. By adding some devices to the basic structure, CHB inverter will operate with maximum achievable output voltage. Simulation and experimental results are shown for a five-level CHB inverter to validate the proposed modulation technique.

1

Introduction

Utilisation of multilevel inverters is increasing in high power and medium voltage applications because of their inherent characteristics such as higher efficiency, lower total harmonic distortion (THD) and lower switching stress and electromagnetic interface (EMI) as compared with conventional two-level inverters [1–3]. However, as the number of voltage levels increases, the number of components in these inverters increases and leads to two main disadvantages; increment in total cost and reduction in the reliability of the inverter. Moreover, the high power converters should supply their loads in commercial and industrial applications without unintentional interruptions [4, 5]. Therefore the study of fault-tolerant methods is so important in these inverters. The three main multilevel converter topologies are the diode clamped converter [6, 7], flying capacitor converter [8, 9] and the cascaded H-bridge (CHB) converter [10, 11]. As of modularity feature and high reliability, CHB inverters are able to operate under faulty conditions [12]. Among all various switching algorithms which can be applied to multilevel inverters, space vector modulation (SVM) seems a promising technique because it is well suited for digital implementation. In addition, SVM is appropriate for reduction of switching losses, total harmonic distortion, as well as better usage of DC-link voltages [13, 14]. To generate balanced load voltages in a multilevel inverter with one or more faulty phases, some techniques use additional power devices and change the hardware topology after switch failure [15]. Moreover, the CHB inverters use their modularity characteristics to continue operation under faulty conditions. In these situations, the redundancy of H-bridge cells is used instead of redundancy of components [16]. 742 & The Institution of Engineering and Technology 2013

Besides the hardware-based fault tolerance methods, some techniques just modify the software, especially the modulation technique. In [17, 18] some fault-tolerant methods have been used to guaranty appropriate operation of multilevel inverters under faulty conditions. In these papers, the phase shift between the voltage references is changed to modify the unbalanced voltage magnitude generated by the inverter phases, using the available cells. In [19], a control scheme based on neutral shift pulse-width modulation has been presented. In this paper, the optimum phase shift angles are calculated for all fault combinations and these angles are saved in a look-up table. When a fault occurs, the phase shift angle of carrier signals is changed to modify the inverter operation and generate balanced line-to-line voltages. However, less attention has been paid to fault-tolerant techniques which use SVM. In recent years, some researchers have proposed new fault-tolerant algorithms based on SVM; however, most of these techniques cannot be applied to three level inverters. In [14], a method based on SVM with fault-tolerant ability has been presented. In failure mode, the faulty cell is bypassed using silicon-controlled rectifier (SCR) switches and the redundant switching states are used to continue inverter operation; however the maximum achievable voltage reduces. Furthermore, this reference compares different control schemes for multilevel inverters with faulty cells. Evaluation of neutral shift method shows that this approach can produce a larger balanced voltage in theory, but it leads to higher harmonics at higher modulation indexes, which makes it undesirable. The problem of detecting a fault, finding the location and then taking appropriate action is the basis of fault-tolerant control. Fortunately, many fault detection methods have been proposed over the last few years [20–23]. So, the main challenge in this paper is limited to take appropriate action IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

www.ietdl.org after fault diagnosis; on the other hand, it is assumed that the type and location of the fault has been detected. In this paper, a new SVM-based fault-tolerant technique is presented that can be applied to three (or more) level inverters. In this method, it is first checked to insert or not insert an external DC offset to the faulty phases according to the fault scenario. Then, the appropriate switching states from the space vector diagram are selected and applied to the multilevel inverter. To support different fault scenarios, a circuit consisting of a DC voltage source, a fuse and an electromechanical relay (for each phase) is used to compensate the DC offset caused by some types of faults in the phase voltages. This technique increases maximum achievable voltage after fault occurrence as compared to former techniqueswhen there is more than one fault. The reminder of this paper is organised as follows: a brief background is presented on five-level inverter and SVM in Sections 2 and 3. Then the methodology of new fault-tolerant algorithm is described in Section 4, followed by simulation and experimental results in Section 5. The paper ends in conclusions.

2

Five-level CHB inverter

The multilevel CHBs are commonly used in industrial applications because of their inherent properties such as

modular structure, simple physical layout and offering more redundant switching states than other topologies. Fig. 1a shows the power circuit topology of a five-level CHB inverter. Each phase consists of two H-bridge cells. Fig. 1b represents one of these H-bridge cells which contains a DC-link voltage and four IGBT switches S1–S4. The output AC terminal voltage can be equal to Vdc, 0 and –Vdc. To generate Vdc, positive voltage, the switches S1 and S4 should be on, to have zero voltage, the switches S1 and S2 or S3 and S4 should be on and to have negative voltage the switches S2 and S3 should be on [24]. It is worth noting that switches Si and Si + 2 (i = 1, 2) operate in a complementary mode in each leg. For example, if Si is ON, Si + 2 is OFF; otherwise Si is OFF and Si + 2 is ON. In general, the power switch failures can be classified into two category; short circuit failure and open circuit failure. When the open circuit failure occurs, the corresponding H-bridge cell fails to produce one of three levels. This kind of fault does not interrupt the operation of inverter; however it degrades the inverter performance. However, when a short circuit failure occurs, continuing the switching action in the faulty leg will cause the shoot through fault in that cell. To take a protective action, the complementary healthy switch in a faulty leg must be turned on in open circuit failure and turned off in short circuit failure. When a short circuit or open circuit failure occurs, according to the

Fig. 1 Basic topology of CHB inverter a Structure of a five-level CHB inverter b One H-bridge power cell IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

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www.ietdl.org situation of the failed switch, this fault can be classified into two types as follows [25]: 1. Failure type (F1): when devices S1 or S4 fails open circuit or devices S2 or S3 fails short circuit, the highest output level (+ Vdc) will be missed. 2. Failure type (F2): when devices S2 or S3 fails open circuit or devices S1 or S4 fails short circuit, the lowest output level (− Vdc) will be missed.

3

SVM principle

Multilevel inverters have a variety of switching vector states that can generate the desired reference. Also each of these switching vector states has some redundant states which increase the switching flexibility. The space vector diagram of a five-level inverter is illustrated in Fig. 2. Note that each of the dots in the figure shows a space vector that is defined by the equation below V = VaN + VbN ej2p/3 + VcN e−j2p/3

(1)

where VaN, VbN and VcN are the output voltages of the inverter where N is the neutral point of inverter. The following equations are used to transform the alpha– beta plane to the g–h plane (aka hexagonal coordinate plane). They reduce the angle between alpha and beta axis from 90° to 60° [26].

√ Vg = V cos u − V sin u/ 3)

√ Vh = V cos (p/3 − u) − V sin (p/3 − u)/ 3

(2)

where the demonstrated space vector in Fig. 2 recognised by amplitude V and phase angel θ. With the above equations, the basic space vectors of the inverter can be converted to the integer values. Thus, finding the coordinates of the three nearest vectors into a reference vector can be easily done. Already in [26], an efficient algorithm has been presented for detection of three nearest vectors and their relevant duty cycles. To find the four nearest vectors to reference voltage, the ‘floor’ and ‘ceiling’ commands can be applied to the Vrefg and Vrefh. The relation between these four nearest vectors

Fig. 3 Determination of three nearest vectors to the reference voltage

and reference voltage is shown in the following equations [26] ⎡ ⎡ ⎧ ⎤ ⎤ ⎪ V V ⎪ ⎪ ⎪ Vul = ⎣ ref g ⎦ Vlu = ⎣ ref g ⎦ ⎪ ⎪ ⎨ Vref h Vref h ⎡ ⎡ ⎤ ⎤ ⎪ ⎪ V V ⎪ ref g ref g ⎪ V =⎣ ⎪ ⎪ ⎦Vll = ⎣ ⎦ ⎩ uu Vref h Vref h

(3)

In (3), the symbols ⌈·⌉ and ⌊·⌋ represent the ceiling and floor operators, respectively. Vlu and Vul are the common space vectors between the upper and lower triangles which are shown in Fig. 3. The third space vector is selected by the equation below which determines the sign of S S = sign Vref g + Vref h − Vul g + Vul h

(4)

The third vector for positive and negative values of S is Vuu or Vll, respectively. So the value of output terminal voltage can be determined by (5) V=

dul Vul + dlu Vlu + dll Vll s , 0 dul Vul + dlu Vlu + duu Vuu s . 0

(5)

where dul, dlu and dll (or duu) are duty cycles which correspond to the three nearest vectors that are applied to the inverter and can be determined by the following equations If S < 0

Fig. 2 Space vector diagram of a five-level CHB inverter 744 & The Institution of Engineering and Technology 2013

⎧ ⎨ dul = Vref g − Vll g d = Vref h − Vll h ⎩ lu dll = 1 − dlu − dul

(6)

IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

www.ietdl.org Table 1 Possible switching states for a given space vector Possible switching states P1 P. 2 . Pn . − (α + β)

Va

Vb

Vc

α+β−m α + β −. m + 1 . m .

β−m . +1 β−m . m− . α

−m − m. + 1 . m − (α . + β)

Otherwise ⎧ ⎨ dul = Vuu h − Vref h d = Vuu g − Vref g ⎩ lu duu = 1 − dlu − dul

(7)

After calculating three nearest space vectors and their corresponding duty cycles, these space vectors must be transformed from g–h-plane to abc-plane. For a specific basic space vector (α, β), the number of switching states nsw can be determined by nsw = n − (a + b)

(8)

where n is the number of voltage levels in a multilevel inverter. It is obvious that most of the space vectors in g–h-plane have more than one switching state. Using Table 1, for the given space vector (α, β), all the possible switching states are calculated [14]. Where m is the number of H-bridge cells per phase and Pi (i = 1, ..., n − (α + β)) is the number of possible switching states. The alignment of switching sequence will be done according to the goal of switching strategy. This goal can be reduction of harmonic distortion, common mode voltage and switching losses. Depending on the desirable switching sequence, one switching state will be selected among the possible states in Table 1. In this paper, the generation of appropriate voltages in fault conditions is the goal of switching strategy.

4 4.1

Proposed fault-tolerant strategy Space vector diagram in faulty conditions

The focus of this paper is limited to take appropriate action after fault diagnosis. When a single fault occurs, depending to the fault type and location of faulty switch, faulty phase of inverter cannot produce a switching voltage level. Thus two phases operate with five voltage levels and faulty phase can continue its operation with four voltage levels.

For example, if switch S1 fails to open (or short circuit), the voltage level + 2Vdc (or − 2Vdc) cannot be produced according to the fault type. This unhealthy condition can lead to DC current offset in inverter phases, and then DC currents will generate unequal stress in the upper and lower switches and may lead to saturation of magnetic cores. Thus some of the space vectors and their corresponding switching states cannot be used according to the faulty phase as it is shown in Fig. 4. However, a limited balanced line-to-line voltage can be generated since there still does exist a large number of available space vectors. In normal operation, the maximum modulation index is related to the number of voltage levels (n) and can be calculated by Mmax =

√ 3 × (n − 1)/2

(9)

but, when a fault occurs, the number of voltage levels decreases and the maximum modulation index reduces as well. When the inverter operates with two or three faulty phases, depending on the fault types, different available space vectors are obtained. Fig. 5 shows space vector diagram of the inverter when these two or three faults are in the same type and Fig. 6 shows space vector diagram of the inverter when the type of faults is different. 4.2 Reconfiguration of the modulation technique and hardware topology To guarantee appropriate operation of the inverter in faulty conditions, the valid switching states must be selected. In fact, after a switch failure, the available switching vectors will reduce in the inverter space vector diagram. Hence, to generate balanced load voltages, the modulation strategy must be changed. The proposed fault-tolerant strategy in this paper consists of two steps. At the first step, it is checked to insert or not insert an external DC offset to the faulty phase for compensating the DC offsets caused by the switch failures. At the second step, the appropriate switching states of the space vector diagram are selected and applied to the multilevel inverter. 4.2.1 Step 1. Checking for adding a DC offset to the faulty phase: A comparison between Figs. 5 and 6 show that the number of healthy layers is lower when both of F1 and F2 faults do exist in the multilevel inverter; because, in this condition, the possible voltage levels which can be generated by one phase are different with two other phases. For example, in case of F1 fault in phase ‘a’ and F2 fault in

Fig. 4 Invalid space vectors with single fault a Phase a b Phase b c Phase c IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

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Fig. 5 Invalid space vectors with two or three faulty phases with the same type; for example, (F1 fault in phases ‘a’, ‘b’ and ‘c’) or (F2 fault in phases ‘a’ and ‘c’)

phases ‘b’ and ‘c’, phase ‘a’ generates − 2Vdc to + Vdc voltage levels and two other phases generate − Vdc to + 2Vdc. To increase the number of healthy layers, phase ‘a’ must generate output voltages between –Vdc to + 2Vdc. To achieve this goal, a DC voltage offset of + Vdc must be injected (in series) to phase ‘a’. With this solution, space vector diagram of faulty condition is changed from Figs. 6 to 5. Fig. 7 shows the proposed solution in this paper for injecting DC voltage offset to the faulty phase. In the proposed structure, three fast blowing fuses and three electromechanical relays (M1–M3) are added to the basic topology. In the previous example, Vdc is the DC voltage that must be added to phase ‘a’. In this case, relay M1 is commanded to be on, then blowing fuse ‘Fuse-I’ is blown and the appropriate voltage is injected to phase ‘a’. It is worth noting that, in the proposed circuit, the electromechanical relays and the fuses can be replaced by the semiconductor switches. However, replacing the fuse

Fig. 6 Invalid space vectors a F1 fault in phases ‘b’ and ‘c’ and F2 fault in phase ‘a’ b F1 fault in phase ‘a’ and F2 fault in phase ‘b’

Fig. 7 Structure of presented fault-tolerant solution 746 & The Institution of Engineering and Technology 2013


www.ietdl.org Table 2 Maximum achievable inverter outputs Fault scenario 1 2 3 4 5 6 7 8 9

Phase ‘a’

Phase ‘b’

Phase ‘c’

Vmax

F1 F2 F1 F2 *F1 *F1 F1 F2 F1

0 0 F1 F2 F2 F2 F1 F2 F2

0 0 0 0 0 F2 F1 F2 F1

√ 1.5 × √3 1.5 × √3 1.5 × √3 1.5 × √3 1.5 × √3 1.5 × √3 1.5 × √3 1.5 ×√3 1× 3

(or relay) by an electronic switch will cause higher conduction loss in the normal operation (or in the fault-tolerant operation) of the inverter. Moreover, complexity is increased as the gate driver circuits have to be isolated from power section. On the other hand, after a switch failure, there is enough time (almost one cycle) to turn on the relay and reconfigure the circuit without losing the system performance. So, using an electromechanical relay is preferred to the electronic switch with an additional isolated driver. Adding a DC voltage to one of the phases is not necessary in all faulty conditions; most of the time this solution is used for faulty conditions in which two different faults occur in two different phases, such as the previous example. In Table 2, the possibilities of different faults and the fault scenarios (fault scenarios #1–9) have been determined. The star sign in some cells of Table 2 indicates the inverter phase in which the DC voltage must be injected.

Fig. 8 Reference vector and space vectors in g–h coordinate system

After applying the DC voltage to the appropriate faulty phase, the switching algorithm is changed to generate balanced line-to-line voltages. The maximum achievable voltage that can be generated by the faulty condition is obviously less than healthy condition. For all combinations of fault types and faulty phases, maximum achievable inverter outputs are listed in Table 2. 4.2.2 Step 2. Selecting appropriate switching states in faulty conditions: For some space vectors in mentioned space diagram, none of the switching states are

Fig. 9 Operation of inverter in normal condition and fault-tolerant operation: inverter phase voltage, line-to-line voltage and load voltage An F1 fault happens at t = 0.02 s in phase ‘a’ IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

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www.ietdl.org valid because of the switch failure. For example, with a F1 fault in phase ‘a’, its output voltage has four voltage levels: − 2Vdc, − Vdc, 0 and + Vdc. Assume that the reference vector V is located within triangle of outer layers as shown in Fig. 8. Some selected space vectors such as (1, 3) and (2, 2) have just one switching state, for example, the switching states of (1, 3) and (2, 2) are [Va, Vb, Vc] = [2, 1, − 2] and [Va, Vb, Vc] = [2, 0, − 2], respectively. Since phase-a cannot generate + 2Vdc, these space vectors are unavailable, thus the reference vector must be limited to the V′. Now selected space vectors are (2, 1), (1, 2) and (1, 1). Space vectors (2, 1) and (1, 2) have two switching states: [Va, Vb, Vc] = [1, − 1, − 2], [2, 0, − 1] and [Va, Vb, Vc] = [1, 0, − 2], [2, 1, − 1], respectively. Also space vector (1, 1) has three switching states: [Va, Vb, Vc] = [0, − 1, − 2], [1, 0, − 1] and [2, 1, 0]. Among these switching states, [2, 1, 0], [2, 1, − 1] and [2, 0, − 1] are unavailable and cannot be used. To obtain three balanced line-to-line voltages of the inverter, valid switching states should be selected by an appropriate algorithm. When F1 faults occur, the possible switching states which are located at the first row of Table 1, that is, P1, are still available; however the switching state Pn − (α + β) is not longer valid. Thus in the event of F1 faults, the selection process for switching states should be done from the first row of Table 1. On the other hand, when F2 faults occur, the possible switching states are selected from the last row of Table 1 (Pn − (α + β)), although the switching state P1 is not longer valid. Thus in the event of F2 faults, the selection process should be from the last row of Table 1.

Using this algorithm for the above example, switching states [1, − 1, − 2], [1, 0, − 2] and [0, − 1, − 2] are selected for generating the space vectors (2, 1), (1, 2) and (1, 1), respectively. As a conclusion, all of the possible switching states are determined in this step and depending on the fault combination (or fault scenario) one of the possible switching states are selected.

5 5.1

Investigation of new fault-tolerant strategy Simulation results

Here, several simulations have been carried out on a three-phase five-level CHB inverter (as shown in Fig. 1a) by MATLAB/SIMULINK program to verify the proposed fault-tolerant method. The proposed fault-tolerant strategy has been applied to the inverter in different conditions, such as single fault and double fault (simultaneous fault) conditions. Fig. 9 shows output voltages of inverter in normal and faulty conditions, where an IGBT in phase ‘a’ fails to short circuit at t = 0.02 s and the faulty phase cannot produce + 2Vdc. This faulty condition has been defined at the first row of Table 2 (fault scenario #1). It is seen that by using the proposed switching state selection algorithm, all three phases continue operation with four √levels and the modulation index is reduced to 1.5 × 3 according to Table 2. In this case, the first step of fault-tolerant strategy is employed to check the necessity of adding an external DC voltage to the faulty phase. According to Table 2, the

Fig. 10 Operation of inverter in normal condition and fault-tolerant operation: inverter phase voltage, line-to-line voltage and load voltage An F1 fault happens in phase ‘a’ and simultaneously F2 fault in phases ‘b’ and ‘c’ at t = 0.02 s 748 & The Institution of Engineering and Technology 2013


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Fig. 11 Operation of inverter in normal condition and fault-tolerant operation: inverter phase voltage, line-to-line voltage and load voltage The F1 fault happen in phases ‘a’ and ‘c’ and simultaneously F2 fault in phase ‘b’ at t = 0.027 s

balanced output voltages could be generated without changing the hardware structure. So, by selecting the appropriate switching states in this faulty condition (through step 2), a DC offset is generated in each phases. Hence, the inverter generates asymmetrical phase voltages with negative DC offset, whereas three symmetrical balanced line-to-line voltages are obtained. In this condition, the load phase voltages are balanced and have 13 levels. The behaviour of fault-tolerant strategy for scenarios #3 and #7 would be same as scenario #1. In next simulation, it is assumed that phase ‘a’ cannot generate − 2Vdc (F2 fault). This faulty condition has been defined in the second row of Table 2 (scenario #2). According to Table 2, the reconfiguration of the hardware structure is not necessary. In this faulty condition each phase can generate voltage levels between –Vdc and + 2Vdc. Then, by selecting the appropriate switching states according to step 2, the inverter generates the phase voltages with identical DC offset which leads to symmetrical balanced line-to-line and the load voltages, as it can be seen in Fig. 10. The behaviour of fault-tolerant strategy for scenarios #4 and #8 would be same as scenario #2. In addition, Fig. 10 shows the behaviour of fault-tolerant strategy when the fault scenarios #5 or #6 happens. In scenario #6, for example, there are three faults in power switches, where phase ‘a’ cannot generate + 2Vdc (F1 fault) and phases ‘b’ and ‘c’ cannot generate − 2Vdc (F2 faults). In this condition, using the proposed solution in Fig. 7, a hardware reconfiguration is performed and the voltage IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

offset of + Vdc is added to phase ‘a’. This solution helps the inverter to generate phase voltages between –Vdc and + 2Vdc. Then, by selecting the appropriate switching states according to step 2, the inverter generates the phase voltages with identical DC offset which leads to symmetrical balanced line-to-line and the balanced load voltages. In the last simulation, it is assumed that there are three faults in power switches, where phase ‘b’ cannot generate − 2Vdc (F2 fault) and phases ‘a’ and ‘c’ cannot generate + 2Vdc (F1 faults). This faulty condition has been defined in the ninth row of Table 2 (scenario #9). It is seen that by using the proposed strategy, all three phases continue their operation with three levels and the voltage levels + 2Vdc and + Vdc are missed. This condition leads to a DC offset √ in each phase and the modulation index reduces to 1 × 3, according to Table 2. In this faulty condition, the hardware topology does not change and the proposed strategy employs step 2 of the fault-tolerant strategy to apply the appropriate switching states. As a result, the inverter generates asymmetrical phase voltages with negative DC offset while the symmetrical balanced line-to-line voltages are generated. In this condition, the balanced load voltages have nine levels as it can be seen in Fig. 11. 5.2

Experimental results

After simulations, the validity of the proposed modulation algorithm was verified experimentally on a five-level three-phase CHB inverter hardware prototype. In the 749


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Fig. 12 Operation of inverter in normal condition and fault-tolerant operation [experimental investigation]: inverter phase voltages (top) and line-to-line voltages (bottom)

Fig. 13 Operation of inverter in normal condition and fault-tolerant operation [experimental investigation]: inverter phase voltages (top) and line-to-line voltages (bottom)

F2 fault has happened in phase ‘a’

F1 fault has happened in phase ‘a’ and F2 fault in phases ‘b’ and ‘c’

investigation, the voltage of each DC link was set to 30 V and the corresponding phase load was a 50 Ω resistance. In addition, a TMS-28335 digital signal processor was employed to implement the proposed modulation algorithm. It is worth noting that the algorithm can be easily implemented in any other kind of microcontrollers. In first investigation, an F2 fault has happened in phase ‘a’ and Fig. 12 shows the output voltages of inverter in normal and faulty condition. Phase ‘a’ cannot generate − 2Vdc, therefore all three phases continue operation with four √ levels and the modulation index reduces to 1.5 × 3, according to Table 2. In this condition, the first step of fault-tolerant strategy shows that it is not necessary to change the hardware structure (or to insert the external DC offset). So, the inverter generates asymmetrical phase voltages with positive DC offset (by selecting the appropriate switching states) to produce the balanced line-to-line voltages, as it can be seen in Fig. 12. The obtained experimental results in this faulty condition are in good agreement with the simulation results in Fig. 10. In the second experiment, effect of an F1 fault in phase ‘a’ and F2 fault in phases ‘b’ and ‘c’ is illustrated in Fig. 13. According to the first step of fault-tolerant strategy, the external DC voltage must be added to the phase ‘a’. To achieve this goal, the electromechanical relay M1 is turned on less than one cycle after fault detection. During this transient time, conventional SVM algorithm is used. This switching algorithm bypasses the faulty power cell and eliminates two voltage levels of the corresponding phase. After this transient time, the switching algorithm is changed and the appropriate switching states are generated according 750 & The Institution of Engineering and Technology 2013

to step 2 of the fault-tolerant strategy. The obtained results in Fig. 13 confirm the correct operation of the inverter and are in good agreement with the simulation results in Fig. 10. Moreover, the transient time in Fig. 13 (almost one cycle after fault detection) is related to delay of activating the electromechanical relay, which is not seen in the simulation results.

6

Conclusions

In this paper, fault-tolerant operation of a three-phase five-level CHB inverter was investigated based on SVM algorithm. The focus of this paper is limited to take appropriate action after fault diagnosis, where it is assumed that the type and location of the fault has been detected. By using the proposed strategy, the inverter generates balanced line-to-line voltages in different fault conditions. All the simulation and experimental results confirmed the balanced operation of the inverter in normal and faulty conditions. Moreover, the maximum achievable line voltage reduces about 25% in most of faulty conditions while the decrement of maximum voltage is about 50% in the previous fault-tolerant strategies, when there is more than one fault in the converter. Therefore the proposed approach improves the maximum achievable fundamental voltage by reconfiguration of the modulation technique and the hardware topology. Using the proposed circuit, an additional DC offset is inserted to faulty phase in some faulty conditions. This reconfiguration makes the maximum voltage almost independent from fault type and fault location; thus the reliability of the CHB inverter increases IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 742–751 doi: 10.1049/iet-pel.2012.0543

www.ietdl.org and the inverter interruption is prevented in the event of different faults. This strategy can be easily extended and implemented for inverters with more voltage levels.

7

References

1 Rodriguez, J., Franquelo, L.G., Kouro, S., et al.: ‘Multilevel converters: an enabling technology for high-power applications’. Proc. IEEE, 2009, vol. 97, pp. 1786–1817 2 Rodriguez, J., Lai, J.S., Peng, F.Z.: ‘Multilevel inverters: a survey of topologies, controls, and applications’, IEEE Trans. Ind. Electron., 2002, 49, pp. 724–738 3 Kouro, S., Malinowski, M., Gopakumar, K.: ‘Recent advances and industrial applications of multilevel converters’, IEEE Trans. Ind. Electron., 2010, 57, pp. 2553–2580 4 Iman-Eini, H., Farhangi, S., Schanen, J.L., Khakbazan-Fard, M.: ‘A fault-tolerant control strategy for cascaded H-bridge multilevel rectifiers’, J. Power Electron., 2010, 10, pp. 34–42 5 Turpin, C., Baudesson, P., Richardeau, F., Forest, F., Meynard, T.A.: ‘Fault management of multicell converters’, IEEE Transactions on Industrial Electronics, 2002, 49, pp. 988–997 6 Nabae, A., Takahashi, I., Akagi, H.: ‘A new neutral-point-clamped PWM inverter’, IEEE Trans. Ind. Appl., 1981, IA-17, (5), pp. 518–523 7 Alepuz, S., Busquets-Monge, S., Bordonau, J., Gago, J., Gonzalez, D., Balcells, J.: ‘Interfacing renewable energy sources to the utility grid using a three-level inverter’, IEEE Trans. Ind. Electron., 2006, 53, (5), pp. 1504–1511 8 Meynard, T.A., Foch, H.: ‘Multilevel choppers for high voltage applications’. Proc. Power Electronics and Applications Conf., 1992, vol. 2, pp. 45–50 9 Lin, B.-R., Huang, C.-H.: ‘Implementation of a three-phase capacitor clamped active power filter under unbalanced condition’, IEEE Trans. Ind. Electron., 2006, 53, (5), pp. 1621–1630 10 Marchesoni, M., Mazzucchelli, M., Tenconi, S.: ‘A non conventional power converter for plasma stabilization’. Proc. Power Electronics Specialists Conf., 1988, pp. 122–129 11 Kou, X., Corzine, K., Wielebski, M.: ‘Overdistention operation of cascaded multilevel inverters’, IEEE Trans. Ind. Appl., 2006, 42, (3), pp. 817–824 12 Fazel, S.S., Bernet, S., Krug, D., Jalili, K.: ‘Design and comparison of 4-kV neutral-point-clamped, flying-capacitor, and series-connected H-bridge multilevel converters’, IEEE Trans. Ind. Appl., 2007, 43, (4), pp. 1032–1040


13 Correa, P., Pacas, M., Rodriquez, J.: ‘Modulation strategies for fault-tolerant operation of H-bridge multilevel inverters’. Industrial Electronics, 2006 IEEE Int. Symp., IEEE, 2007, pp. 1589–1594 14 Wei, S., Wu, B., Rizzo, S., Zargari, N.: ‘Comparison of control schemes for multilevel inverter with faulty cells’. Proc. 30th Annual Conf. on IEEE Industrial Electronics Society, Busan, Korea, November 2004, vol. 2, pp. 1817–1822 15 Li, S., Xu, L.: ‘Strategies of fault tolerant operation for three-level PWM inverters’, IEEE Trans. Power Electron., 2006, 21, (4), pp. 933–940 16 Song, W., Huang, A.Q.: ‘Control strategy for fault-tolerant cascaded multilevel converter based STATCOM’. Proc. 22nd IEEE Applied Power Electronics Conf., February 2007, pp. 1073–1076 17 Hammond, P.W.: ‘Multiphase power supply with series connected power cells with failed cell bypass’, U.S. Patent 6 222 284, 24 April 2001 18 Zang, Y., Wang, X., Xu, B., Liu, J.: ‘Control method for cascaded H-bridge multilevel inverter failures’. Proc. Intelligent Control and Automation, Dalian, June 2006, vol. 2, pp. 8462–8466 19 Rodriguez, J., Hammond, P.W., Pontt, J., Musalem, R., Lezana, P., Escobar, M.J.: ‘Operation of a medium-voltage drive under faulty conditions’, IEEE Trans. Ind. Electron., 2005, 52, (4), pp. 1080–1085 20 Da Silva, E.R., Lima, W.S., de Oliveira, A.S., Jacobina, C.B., Razik, H.: ‘Detection and compensation of switch faults in a three level inverter’. Proc. IEEE Power Electronics Specialists Conf., Jeju, Korea, June 2006, pp. 1309–1315 21 Rodriguez, M.A., Claudio, A., Theilliol, D., Vela, L.G.: ‘A new fault detection technique for IGBT based on gate voltage monitoring’. IEEE Power Electronics Specialists Conf., June 2007, pp. 1001–1005 22 Musumeci, S., Pagano, R., Raciti, A., Belverde, G., Guastella, C., Melito, M.: ‘A novel protection technique devoted to the improvement of the short circuit ruggedness of IGBTs’. IEEE Conf. on Industrial Electronics Society, November 2003, vol. 2, pp. 1733–1738 23 Fenton, W.G., McGinnity, T.M., Maguire, L.P.: ‘Fault diagnosis of electronic systems using intelligent techniques: a review’, IEEE Trans. Syst. Man Cybern., 2001, 31, (3), pp. 269–281 24 Iman-Eini, H., Schanen, J.L., Farhangi, S., Roudet, J.: ‘A modular strategy for control and voltage balancing of cascaded H-bridge rectifiers’, IEEE Trans. Power Electron., 2008, 23, (5), pp. 2428–2442 25 Mingyao, M., Lei, H., Alian, C., Xiangning, H.: ‘Reconfiguration of carrier-based modulation strategy for fault tolerant multilevel inverters’, IEEE Trans. Power Electron., 2007, 22, (5), pp. 2050–2060 26 Celanovic, N., Boroyevich, D.: ‘A fast space-vector modulation algorithm for multilevel three-phase converters’, IEEE Trans. Ind. Appl., 2001, 37, (2), pp. 637–641

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