On Device Architectures, Subthreshold Swing, and Power

Received 4 September, 2014; revised 20 February, 2015; accepted 24 February, 2015. Date of current version 22 April 2015. The review of this paper was arranged by Editor Y.-C. Yeo. Digital Object Identifier 10.1109/JEDS.2015.2409303

On Device Architectures, Subthreshold Swing, and Power Consumption of the Piezoelectric Field-Effect Transistor (π -FET) RAYMOND J. E. HUETING1 (Senior Member, IEEE), TOM VAN HEMERT1,3 , BUKET KALELI1,3 , ROB A. M. WOLTERS1,2 , AND JURRIAAN SCHMITZ1 (Senior Member, IEEE) 1

MESA+ Institute for Nanotechnology, University of Twente, Enschede 7500AE, The Netherlands 2 NXP Semiconductors, Eindhoven 5656 AA, The Netherlands 3 Now at ASML, Veldhoven 5504 DR, The Netherlands CORRESPONDING AUTHOR: R. J. E. HUETING (e-mail: [email protected])

This work was supported in part by the Dutch Technology Foundation Stichting Toegepaste Wetenschappen (STW), an Applied Science Division of Nederlandse organisatie voor Wetenschappelijk Onderzoek (NWO), and in part by NanoNextNL, a Micro and Nanotechnology Programme of the Dutch Ministry of Economic Affairs, Agriculture and Innovation (EL&I) and 130 partners.

ABSTRACT This paper describes the potential of tunable strain in field-effect transistors to boost per-

formance of digital logic. Voltage-controlled strain can be imposed on a semiconductor body by the integration of a piezoelectric material improving transistor performance. In this paper, we derive the relations governing the subthreshold swing in such devices to improve the understanding. Using these relations and considering the mechanical and technological boundary conditions, we discuss possible device architectures that employ this principle. Further, we review the recently published experimental and modeling results of this device, and give analytical estimates of the power consumption. INDEX TERMS Piezoelectric effect, MOSFET, CMOS, subthermal device, steep-subthreshold device.

I. INTRODUCTION

In recent years, the performance improvement of transistors from generation to generation has slowed down, as a result of lagging gate length scaling. So-called performance boosters have been introduced in Complementary Metal-Oxide-Semiconductor (CMOS) technology to further improve the circuit performance in new process generations [1]. These performance boosters include metal-gate-high-k stacks [2], [3], channel strain [4]–[6], and ultra-thin body configurations (e.g., ultra-thin body silicon-on-insulator substrates [7] and FinFETs [8], [9]). Both higher on-currents and lower off-currents are achieved through these measures. For the further advancement of CMOS, devices must exhibit a high on/off ratio at low power supply voltage. The key limiting factor in conventional MOS transistors is the subthreshold swing (SS), see also Fig. 1, defined as [10]: SS ≡

dVGS dVGS = · ln(10) = m · uT · ln(10), (1) d log(ID ) d ln(ID )

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where VGS is the gate-source voltage, ID is the drain current, uT is the thermal voltage, and m is the ideality factor. In a classical FET the subthreshold swing is limited by diffusion of charge carriers and is ≥60 mV/dec at room temperature whereas for future CMOS a lower, i.e., subthermal, SS, is required. Several device concepts aiming at a subthermal SS have been proposed and are currently under investigation; see [11]–[19] and the other articles of this Special Issue. In recent articles we proposed the addition of piezoelectric material to the FinFET as a further performance booster [20], [21]. In this device, dubbed π -FET, the converse piezoelectric effect is employed to achieve active modulation of the channel strain. Instead of permanent strain, we can now turn on the strain only in the on-state, leading to an advantageous on/off ratio, as visualized in Fig. 1. We earlier reported on experimental realizations of prototype devices following this principle [22]. In this work we further analyze the potential of the π -FET by technological and performance considerations. This article

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FIGURE 1. Illustration of the ID -VGS characteristics of a FET on semi-logarithmic scale. The characteristics are shown for a device with no strain (i.e., relaxed condition), constant strain, and strain formed by the converse piezoelectric effect (i.e., the π -FET). The subthreshold swing (SS) is also indicated.

describes the envisaged π -FET configurations, presents analytical relations of the SS, and estimates the power consumption based on analytical relations and roadmap projections [1]. This work is outlined as follows. In Section II we detail the principle of operation and derive the equations for the SS. In Section III we explain several device configurations. In Section IV we address the power consumption of the π -FET. Finally, in Section V the conclusions of this work are drawn.

relations for the SS applicable to most types of π -FETs for improving the basic understanding. For a classical Si transistor, when there is good electrostatic gate control over ID , SS equals 60 mV/dec at room temperature as illustrated in Fig. 1 (no strain). In CMOS technology so-called strain, i.e., mechanical deformation, is employed in Si to increase the mobility hence the performance. This type of strain is typically constant depending on the surrounding materials and leads to a relatively high Ioff and Ion provided all other process parameters are kept the same [5], [23], as illustrated in Fig. 1 (strained FET). Recently, we have proposed a new device called the PiezoFET (π -FET) [20], [21] in which a piezoelectric (π -) layer is incorporated in the device, see e.g., Fig. 2. The basic idea is that the strain in the semiconductor body can be tuned by the converse piezoelectric effect [24]. As a result, during device operation the body is relaxed in the off-state, resulting in a low Ioff , and it is strained in the on-state. As mentioned before the strain has an effect on the mobility, however, also on the band alignment. In particular the change in band alignment reduces the SS as predicted by [21], schematically illustrated in Fig. 1. However, [21] presented numerical calculations with a focus on ultrathin body (UTB) configurations. To grasp the basic principle it is important to derive closed form relations for the SS of the π -FET in bulk and UTB configurations. For determining the SS we need to study the electrostatics of a FET starting from: VGS = Vins + Vs ,

(2)

with Vins and Vs being the voltage drop across the gate insulator and semiconductor, respectively. Neglecting the mobile charge and nonidealities such as fixed charge in the gate dielectric, the following holds in subthreshold [10], [25]: VGS = −

FIGURE 2. Schematic cross section of several envisaged π -FET configurations. (a) Bulk π -FET in which the π -layer has been directly placed on the silicon (the gray region indicates the depletion region), and devices in which there is only a mechanical contact between the π -layer and the channel such as (b) bulk π -FET and ultrathin body (UTB) devices in (c) planar/double-gate π -FET configuration, and (d) π -FinFET configuration (perpendicular to the current flow direction). For the π -FinFET, the vertical dotted line indicates the axis of symmetry. The dimensions are not to scale. Note for maximum strain effect the mechanical gate should be preferably made out of a stiff metal and fixed e.g., in the third dimension.

II. BASIC PRINCIPLE

Before treating the possible device configurations we first discuss the basic principle and for the first time derive 150

Qdep + Qit + ψs + ϕm − ϕs , Cins

(3)

where Qdep is the depletion charge per unit area, Qit is the interface trap charge per unit area, Cins is the gate insulator capacitance per unit area, ψs is the surface potential and ϕm , ϕs are the workfunctions of the metal gate and semiconductor, respectively. In particular ϕs is important for the π -FET, since it depends on the semiconductor electron affinity χs and the bandgap Eg . Both these parameters are affected by the strain, and therefore by the converse piezoelectric effect [21], see also Section III. For an n-type bulk MOSFET holds that   Eg kT NV , (4) + ln ϕs = χs + q q NA and for a p-type bulk MOSFET   NC kT ϕs = χs + . ln q ND

(5)

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HUETING et al.: ON DEVICE ARCHITECTURES, SUBTHRESHOLD SWING, AND POWER CONSUMPTION OF THE π -FET

Finally for an ultrathin body (UTB) device, e.g., double-gate FET or FinFET, holds   Eg kT NC , (6) + · ln ϕs = χs + 2q 2q NV for both n- and p-type FETs. NA,D is the acceptor and donor concentration, NC,V is the effective density-of-states in the conduction and valence band, k is Boltzmann’s constant, and T is the temperature. Further,  (7) Qdep ≈ ∓ ±2 · q · εs NA,D ψs , with εs the semiconductor permittivity. The upper (lower) sign corresponds to an n-type (p-type) FET. The depletion charge in long channel UTB devices can generally be neglected. Since the potential barrier hence band alignment exponentially determines the subthreshold current (see also Eq. (11)), while transport parameters such as mobility μn,p and NC,V will have a less pronounced effect, in this work for simplicity we consider μn,p and NC,V to be independent of the strain hence the bias over the π -layer. From Eqs. (3)–(6) it can then be derived for the n-type bulk MOSFET that Cins + Cdep + Cit dVGS ,  = (8) dE dψs C · 1 + dχs + 1 · g ins

dVGS

q

dVGS

and for the p-type bulk MOSFET Cins + Cdep + Cit dVGS ,  = dψs C · 1 + dχs ins

(9)

dVGS

while for the UTB FET dVGS Cins + Cit  = dχs 1 dψs Cins · 1 + dV + 2q · GS

dEg dVGS

.

(10)

Here, Cdep and Cit are the depletion respectively interface dQ trap capacitance per unit area (Cdep = − dψdep , see Eq. (7)). s The terms depending on χs , and Eg in the denominators of Eqs. (8)–(10) form the tunable strain parameters caused by the converse π -effect. These parameters strongly depend on the device configuration as is discussed in Section III. Generally the following relation holds for the subthreshold current:      VDS ψs · 1 − exp ∓ , (11) ID = ±I0 · exp ± uT uT with uT = kT/q the thermal voltage. The upper (lower) sign holds for n-type (p-type) FETs. The prefactor I0 depends on the type of FET. So holds for the long channel bulk FET [10]: n2i 2 W (12) uT · Cdep , NA,D L with μn,p , W, L is the charge carrier mobility, gate width, and channel length, respectively. For long channel UTB devices holds: Abody I0 = qμn,p ni uT · (13) L I0 = μn,p

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with Abody = W · ts for the double-gate FET [26], Abody = WFIN · HFIN · NFIN for the FinFET, and Abody = π · R2 · NFIN for the gate-all-around (GAA) FET [27]. NFIN , WFIN , HFIN , ts , R are the amount of wires or fins, fin width, fin height, semiconductor thickness, and nanowire radius, respectively. So far there have been no reports in case of an aggressively scaled UTB π -FET below the ballistic limit, i.e., for a channel length that is near or less than the mean free path λ. For deriving a closed form relation for the subthreshold current below the ballistic limit the so-called flux method [29]–[31] or scattering matrix approach (SMA) [28], [32] can be used. For the nanoscale FET the electrostatics are not fundamentally different [33]. Neglecting short-channel effects and considering three scattering matrices through the source, channel and drain region it can be derived that basically Eq. (11) holds with   (14) I0 = q · vR BQ · ni · Abody , where vR is the Richardson velocity and 1−r T0 · (1 − r)2 . (15) = 1 − 2 (1 − T0 ) r + (1 − 2T0 ) 1+r Here the transmission coefficient T0 = λ/(λ + L) is assumed to be unity in the ballistic regime (L → 0) and the source/drain backscattering coefficients to be the same rS = rD = r. An important difference between Eq. (13) and Eqs. (14), (15) is that for the former in principle the integral of the potential barrier is important, while for the latter the peak potential barrier matters most. For a long channel device BQ ≈ λ/L and Eq. (13) is re-obtained. Note that for narrow UTB devices the channel quantum well in the subthreshold condition results in a constant offset of the band edges; this has no effect on the SS and therefore is not taken into account. In Eqs. (4)–(6) and Eqs. (12)–(14) both I0 and ψs depend on VGS . The former through ni , hence Eg , the latter because of χs , Eg and the electrostatics. Hence from Eqs. (11)–(14) we obtain dEg d ln(ID ) 1 1 dψs · =∓ + · , (16) dVGS a · kT dVGS uT dVGS with a = 1, 2 for the bulk FET and UTB FET respectively. Again the upper (lower) sign holds for n-type (p-type) FETs. Substituting Eqs. (8)–(10) in Eqs. (1) and (16) and after some manipulation we obtain for the n-type bulk FET: Cins + Cdep + Cit   m= , (17) (Cdep +Cit ) dEg dχs − Cins · 1 + dV · q dV GS GS BQ =

and for the p-type bulk FET: Cins + Cdep + Cit m=   (C +C +C ) dχs + ins qdep it · Cins · 1 + dV GS For the n-type UTB FET we obtain: Cins + Cit   m= dχs − Cins · 1 + dV GS

Cit 2q

·

dEg dVGS

,

dEg dVGS

. (18)

(19)

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and finally for the p-type UTB FET we arrive at: m=

 Cins · 1 +

Cins + Cit  dχs 2Cins +Cit · dVGS + 2q

dEg dVGS

.

(20)

In case of a negligible amount of strain we obtain the traditional text book equations [10], [25]: all terms in the denominators are zero except for Cins . For the π -FET, on the other hand, the parameters χs and Eg depend on the strain hence applied bias VGS across the π -layer. χs needs to increase, hence the minimum conduction band EC needs to drop, with increasing strain values for the n-type π -FET while for the p-type π -FET the maximum valence band EV needs to increase as confirmed by numerical calculations [21]. Therefore the following conditions for the π -FET should hold: dχs dVGS dEV dVGS

dEC = − 1q dV >0 GS

=

dχs q dV GS

−

dEg dVGS

(n − type) < 0 (p − type)

(21)

From Eqs. (1), (17), and (19) and the given conditions it can be concluded that the SS drops in the n-type π -FET compared to the same device without the π -layer. For the p-type FET this is more difficult to see. By checking the denominators of Eqs. (18) and (20) more carefully the terms Cins · (1 + dχs /dVGS ) and (Cins /2q) · dEg /dVGS add up to (Cins /q) (1 − dEV /dVGS ). Hence, we can also conclude that for p-type π -FET SS drops. However it will be less pronounced compared to an n-type π -FET [21] because | (1/q) dEV /dVGS | < |dχs /dVGS |, as addressed in Section III. Further, it indeed appears that a subthermal SS value (< ln(10) · uT ≈ 60 mV/dec) can be obtained in UTB devices provided that Cit is sufficiently low. However for the bulk FETs the SS strongly depends on the Cdep (and of course Cit ), though for the p-type bulk FET this is more important because of the additional positive right term in the denominator of Eq. (18). We will use Eqs. (17)–(20) for the discussion in the next section. III. DEVICE CONFIGURATIONS

To achieve subthermal switching performance as described in the previous paragraph, the transistor channel strain must be modulated by a control voltage. In recent work we have proposed to implement this by the integration of a piezoelectric material such as PZT or AlN [21], [22]. Fig. 2 shows the envisaged configurations of field effect transistors with a piezoelectric strain modulation layer. The most straightforward and compact arrangement is obtained by replacing the gate dielectric by a piezoelectric insulator and hence by placing it directly on the silicon, as depicted in Fig. 2(a). This arrangement benefits from the fact that piezoelectric materials exhibit a relatively high dielectric constant, but it is expected that a subthermal SS is not reached for this case. The reason for this is that the dielectric should be surrounded by charge, preferably a lot. In case of a long channel FET in subthreshold condition this 152

FIGURE 3. Schematic band diagram of the π -FET (Fig. 1) in the current flow direction just underneath the gate-dielectric. A potential barrier is formed at the drain side because of the high gate and drain potential. It is expected that this reduces the DIBL effect.

basically should be the depletion charge (or Cdep ) in the grey area: the higher the amount of charge the higher the field, hence π -effect. However, when we check Eqs. (17)–(18) we see that Cdep counteracts with the π -effect. Therefore the SS will be reduced by the π -effect but won’t reach a subthermal value. Related to this, simply replacing the gate dielectric by a piezoelectric insulator in a long channel UTB FET configuration will change the strain only slowly in the subthreshold regime as not all of the voltage drops over the dielectric (Cdep can be neglected). Hence the strain will indeed be modulated in this arrangement, but only strongly in accumulation and inversion. Further, the carrier mobility may deteriorate in the presence of a polar material such as a piezoelectric layer. There is one more topic to consider and that is the shortchannel effect (SCE). When we reduce the device dimensions of course the high amount of charge present in the source and drain regions will become dominant that increases the π -effect. As a result, there might be a reduced SS but again no subthermal values, both for bulk and UTB FETs. Also, depending on the shape of the source/drain doping profiles band-to-band tunneling will become more important because of the strain-induced Eg narrowing. Related to this, when using short channel π -FETs the drain-induced barrier lowering (DIBL) effect will be less compared to the classical counterpart. Since the gate-drain voltage at maximum current is near zero the field through the π -layer at the drain side will be low, and as a result the band alignment in the semiconductor is not affected. We basically obtain a change in the band alignment along the current flow direction, where a potential barrier is formed at the drain side, see Fig. 3. This makes the subthreshold current less sensitive to the drain bias. Of course this should be verified experimentally. From the technology point of view there is another issue. A π -material with a high piezoelectric response such as lead zirconate titanate (PZT) [34], [35] and Si (or perhaps any other semiconductor) technology are mutually not compatible. To combine these materials, and to avoid ferroelectric performance degradation and atom interdiffusion through interfaces, a so-called buffer or seed layer is required [36]–[38] to avoid direct contacting on a semiconductor. VOLUME 3, NO. 3, MAY 2015

HUETING et al.: ON DEVICE ARCHITECTURES, SUBTHRESHOLD SWING, AND POWER CONSUMPTION OF THE π -FET

FIGURE 4. Schematic cross section of a metal-ferroelectric-metal (MFM) capacitor on top of a semiconductor substrate. In our experiments [39], we used for the top electrode (source) Pt/Ti, for the bottom electrode (gate) an LNO/poly-Si/TiN stack, and for the gate dielectric SiO2 was used. For the discussion in the layer thicknesses are indicated. The dimensions are not to scale.

Earlier we did some experiments on metal-ferroelectricmetal (MFM) capacitors on top of a gated Si channel, see Fig. 4. For these capacitors a lanthanum nickelate, LaNiO3 (LNO), layer was used as a buffer layer for the PZT layer on top of a traditional poly-Si/TiN/SiO2 gate stack [39]. X-ray photoelectron spectroscopy (XPS) was used here to obtain the compositional depth profile of the fabricated multi-film stack. XPS analysis is generally used to get information on the material distribution in different layers and on interfaces. It can detect diffusion of impurity atoms (e.g., Pb) into the silicon channel below the PZT/LNO/poly-Si/TiN/SiO2 stack. This is important to know since the impurity diffusion can degrade the performance of the underlying transistor. Fig. 5 shows the XPS depth profile in such a capacitor. Starting from the surface the PZT layer is recognized. Below that layer the LNO buffer, poly-Si and TiN layers can be observed. Further down is the SiO2 gate dielectric. No diffusion of Pb in the Si layer is observed within the resolution limit of XPS (∼ 0.5 at. %). This gives an indication that, when deposited on devices, there will be no degradation on the transistor properties as confirmed in our Si π -FinFET data [22].

FIGURE 5. XPS depth profile of the MFM capacitor from top to SiO2 layer. In this experiment, LNO is used as buffer layer, the poly-Si and TiN layers are used as a gate, and the SiO2 layer is used as a gate dielectric. The layer stack is schematically drawn on top of the graph to guide the eye.

Given these considerations we chose to study the configurations in Fig. 2(b)–(d) in more detail. Here, the piezoelectric VOLUME 3, NO. 3, MAY 2015

film is positioned outside the gate stack. The gate metal both shields the horizontal (source-drain) field and may act as a diffusion barrier. Depending on the π -material additional buffer layers may be required. So basically there is no electrical contact between the π -layer and semiconductor body, rather an indirect mechanical contact. Of course, tunnel FETs [13], [20] or Junction-less transistors [40] could also be formed in each of these configurations. One advantage is that Qdep in all devices is no longer important for the π -effect because the full VGS can be applied over the π -layer. In case of long channel devices we can omit all Cdep terms in Eqs. (17) and (18). This means that irrespective the use of a bulk π -FET of any UTB π -FET a subthermal SS can be obtained. Note that in these configurations Cins in Eqs. (17)–(20) no longer depends on the π -layer properties. So far we have not discussed the mechanics and the mechanical boundaries. For planar devices, such as those depicted in Fig. 2(a)–(c), when we apply a voltage over the π -layer depending on the polarity of the voltage and π -material the π -layer thickness will deform. In conventional planar FET designs the top (or gate) metal is more or less free, i.e., mechanically floating. This means when we apply a bias over the π -layer some, perhaps most, of the electromechanical energy is not used to strain the semiconductor body and hence is lost. It is therefore advisory to mechanically fix the top metal in the third dimension using e.g., anchors attached to the either a substrate of (preferably) a stiff dielectric. This problem is more or less solved in the symmetric π -FinFET configuration as depicted in Fig. 2(d). In this case we have a symmetric mechanical boundary condition. However, in this configuration we need to have a good step coverage of the π -layer around the device, which is a problem since for this uniform deposition techniques such as atomic-layer deposition may be required [22] which is not straightforward in particular for ternary or quaternary compounds. For this AlN can be used as an alternative piezoelectric material, which can be deposited by ALD [41], [42]. However, as mentioned before AlN has a ten times lower piezoelectric response compared to PZT. In addition, the issue of the mechanical boundary condition can also be elegantly solved by utilizing a GAA device geometry encapsulated in stiff material. There is an indirect mechanical contact between the π -layer and semiconductor body in the configurations of Fig. 2(b)–(d), which requires more effort to reduce SS effectively. When the mechanical gate is connected to the source it can be derived for the strain in the (100) oriented semiconductor body [21]: ss = − 

ts cs

+

eπ VGS cπ cs tg tins cins + cg

+

tπ cπ

,

(22)

where tπ,ins,g is the thickness of the π -, insulator and gate metal layer (see also Fig. 4), cπ,ins,s,g is the stiffness of the π -, insulator, semiconductor and gate metal layer, 153

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and eπ is the piezoelectric (charge) constant. Note that the physical parameters eπ and cπ,ins,s,g are tensors but in this one-dimensional relation have been assumed to be scalars for simplicity sake. Consequently, shear strain components have been ignored as well. In real life these parameters, in particular cπ and eπ , depend on the crystal (and device) orientation and field direction. From Eq. (22) we can derive the χs and Eg strain dependence via the deformation potentials in the conduction band and valence band. Basically it can be summarized that: χs (ss ) = χs0 − C,eff · ss ,   Eg (ss ) = Eg0 + C,eff − V,eff · ss ,

(23) (24)

with Eg0 and χs0 are the bandgap and workfunction of the relaxed semiconductor, and C,eff , V,eff are the “effective” deformation potential in the conduction band and valence band of the semiconductor, respectively. These “effective” parameters are introduced to avoid numerous details [21], [43]–[47] which are not important for this discussion. More importantly, in case of III-V materials a tensile (compressive) ss value is required for the n-type (p-type) FET because C,eff and V,eff are both negative in sign. For germanium (Ge), Si on the other hand a compressive ss value is required irrespective of the type of FET (C,eff , V,eff is positive respectively negative in sign) [21]. Also |C,eff | > |V,eff | for all materials and consequently the converse π -effect is in principle more effective for n-type FETs. From Eqs. (22)–(24) we obtain relations for dχs /dV  GS (= −C,eff · ss /VGS ) and dEg /dVGS  (= C,eff − V,eff · ss /VGS ) needed for the SS, see Eq. (21). From Eqs. (22)–(24) we can also conclude the following. First, for reducing mechanical losses ultrathin and relatively stiff interfacial layers in between the π - and semiconductor body are required (e.g., hafnium-oxide (HfO2 ) instead of SiO2 ). In particular the stiffness is important for the gate metal since the workfunction of the metal could also depend on the amount of strain. This effect has been reported before for titanium-nitride (TiN) [48]–[50]. Because of its high stiffness relatively high stress values are required to change the workfunction. Second, the semiconductor body should preferably have a low stiffness and a high deformation potential (e.g., germanium, III-Vs [44], [47]), and third, the π -material should preferably have a high piezoelectric response, but also a high breakdown field Ecr [21]. Fig. 6 shows simulation data for three types of n-type Ge FinFETs [21]: a device without strain (i.e., relaxed), one with a fixed strain value of 1.6%, and another device with tunable strain (the π -FinFET) with PZT as a piezoelectric layer. In the latter the maximum strain level is 1.6% at VDS = 1 V. The simulations were performed in mixed-mode: Comsol Multiphysics was used for the mechanical domain and used as input for the TCAD Sentaurus (Synopsys) simulation tool used for the electrical domain. For comparison the analytical model obtained from [26] has been plotted in the same graph in which the conduction band has been adjusted depending on the amount of strain according to 154

Eq. (23) where C,eff ≈ 12.4 eV for Ge [43]. The results show that for an increased fixed strain value the subthreshold current increases exponentially while the SS does not change. However, for the π -FinFET the SS has been reduced to 50 mV/dec (T = 300 K), indicating that subthermal SS values can be obtained.

FIGURE 6. Simulated and modeled ID -VGS characteristics of an n-type Ge FinFET (Fig. 2(d)) with tunable strain (π -FinFET) and with constant strain [21] (T = 300 K). All devices have a 1.5-nm thick hafnium-dioxide (HfO2 ) layer for the gate dielectric and a 3-nm thick titanium-nitride (TiN) layer for the gate metal. The π -FinFET consists of a 10-nm thick PZT layer.

In summary, depending on the boundary conditions in the processing, mechanics and device physics several device configurations have been proposed and discussed for the π -FET concept. These configurations could potentially reach subthermal SS values. IV. POWER CONSUMPTION

The reason to investigate steep subthreshold slope devices is the promise of a lower power consumption. In this section we estimate the effect of strain modulation on the power consumption of a transistor that is used in digital logic circuitry. The total power consumption can be divided into two parts. The first is the dynamic power Pdyn , which in digital logic is the energy required to switch the transistor state [51] and multiplied by the number of switches per second. The second is the static power Pstat , given by the leakage current multiplied by the supply voltage. The strain modulation effect can be employed in different ways. For instance either the supply voltage VDD can be kept the same and consequently the leakage current Ioff is reduced, resulting in a lower Pstat , or the Ioff can be kept constant and the VDD is reduced, resulting mostly in a lower Pdyn . In the π -FinFET a piezoelectric capacitance is added parallel to the gate capacitance. For each cycle both must be charged and discharged, and as a result this adds up to Pdyn . Hence it is unlikely that the π -FinFET is able to reduce the Pdyn . However, it can reduce the Pstat at the cost of an increased Pdyn . We follow [51], and note that the Pdyn is given by the sum of the charge required to charge both the oxide Pins and the piezoelectric layer Pπ and find Pins = W · Lg · α · fclk fo

2 VDD Cins 2

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 2  VDD επ sπ · eπ Pπ = W · Lg · α · fclk fo + 2 tπ VDD   C,eff · ss Pstat = Ioff · VDD · exp uT

(26) (27)

where α is the switching activity factor, fclk is the clock frequency, fo is the tapering factor (the number of switches each transistor has to drive), W is the gate width, Lg is the gate length, and Ioff is the off-current of a device without strain (see e.g., Eqs. (11) and (13), with VDS =VDD , VGS =0). Note that the leakage through the piezoelectric layer can be ignored in this discussion since its current density is less than ∼10−4 A/cm2 which is much less than the value reported for the gate leakage [52], [53]. The band deformation due to the induced strain is given by C,eff · ss , where C,eff is the effective deformation potential. Further, tπ , επ , and sπ is the thickness, permittivity, and strain in the π -layer, respectively. tπ is calculated by assuming that the maximum field Ecr is over the π -layer when VDS = VDD , i.e., tπ = VDD /Ecr [21]. The strain values ss , sπ can be calculated using Eq. (22). Hence, the piezoelectric power scales with the sum of the permittivity and the strain in the piezoelectric layer. The equations can be used to estimate whether strain modulation can reduce the power consumption of a transistor. In the general case we can only answer that it strongly depends on all the material parameters, device dimensions, frequency of operation and usage of the devices. However, we can state that strain modulation can reduce the Pstat at the cost of an increased Pdyn , hence it can only be beneficial in circuits where Pstat dominates the total power consumption. An estimation for the device parameters in the future can be found in the ITRS roadmap [1]. We used the device parameters from the 2011 edition for the FEP4 Low Standby Power Devices Technical Requirements, other parameters used are summarized in Table 1. For the π -layer we considered PZT, for the semiconductor Ge, for the gate metal layer TiN, and gate insulator HfSiO. From this roadmap we estimated the expected Pstat and Pdyn for an n-type transistor, and these are shown in Fig. 7. The graph shows that Pstat exceeds Pdyn for technologies with gate lengths below 18 nm. Next, following Eqs. (26) and (27) we estimated the effect piezoelectric strain modulation can have on the power consumption. We tuned the piezoelectric layer thickness, and thus the strain modulation and corresponding power Pins , to obtain a minimal total power. To illustrate the numbers at L = 5 nm, the tuned piezoelectric thickness is 48 nm, its dielectric constant is assumed to be 150, while the gate oxide thickness is 0.5 nm. We found that from ∼ 8 nm gate length onward the estimated Pstat is significantly higher than Pdyn . There the strain modulation can reduce the total power consumption of a transistor, even at the cost of the additional Pdyn of the π -layer. VOLUME 3, NO. 3, MAY 2015

TABLE 1. Device parameters used for estimating the power consumption of the π -FET (see Fig. 7). Ecr is the breakdown field for PZT used to scale tπ (= VDD /Ecr ). Other parameters such as tins , VDD , Ioff , and gate length have been taken from [1]. Note that for the permittivity of PZT the high field (near Ecr ) value has been used.

FIGURE 7. Estimated power of an n-type transistor calculated from the ITRS [1] prognoses for device parameters and performance (black line). An estimate for the strain modulation effect on the power consumption is shown in red. Please note that the strain modulation is used to decrease the static power consumption. Hence, Pins is the same for both transistors.

V. CONCLUSION

In this work we have discussed the effect of the envisaged device configurations for the π -FET based on simple estimations. It is expected that a π -layer in direct contact with the semiconductor body will not result in subthermal SS values. However for the proposed device configurations subthermal SS can be reached depending upon the mechanical boundary conditions, such as mechanical material properties, interfacial layer thicknesses and device design. Based on the ITRS roadmap the main benefit in the power consumption is estimated to occur from 8 nm gate length onwards. In case of standby operation the total power consumption is primarily determined by the static power consumption which will then make the π -FET concept an attractive candidate. However for our experimental work more research is needed to obtain subthermal SS values following the guidelines of this work in addition to well controlled interfaces.

ACKNOWLEDGMENT

The authors would like to thank the Semiconductor Components Group and MESA+ Nanolaboratory staff members for their kind support. They also would like to thank SolMateS B.V., Enschede, The Netherlands, for the material supply. 155

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BUKET KALELI received the B.Sc. and M.Sc. degrees in physics from the Middle East Technical University, in 2007 and 2009, respectively, and the Ph.D. degree from the University of Twente, Enschede, The Netherlands.

ROB A. M. WOLTERS received the M.Sc. and Ph.D. degrees from the University of Twente, Enschede, The Netherlands, in 1974 and 1978, respectively. He was with Philips Research and NXP Research, Eindhoven, The Netherlands. Since 2004, he has been a Part-Time Professor with MESA+ Institute for Nanotechnology and the Chair of Semiconductor Components, University of Twente.

RAYMOND J. E. HUETING (S’94–M’98–SM’06) received the M.Sc. (cum laude) and Ph.D. degrees in electrical engineering from the Delft University of Technology (NL). In 2005, he joined the Semiconductor Components Group, University of Twente in the field of semiconductor device physics and modeling.

TOM VAN HEMERT received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the University of Twente. He is currently with TMC Physics. His research interest is in device concepts which aim at reducing the power consumption of integrated circuits.

VOLUME 3, NO. 3, MAY 2015

JURRIAAN SCHMITZ received the M.Sc. (Hons.) and Ph.D. degrees in experimental physics from the University of Amsterdam, in 1990 and 1994, specializing on radiation imaging detectors for the Large Hadron Collider. He was a European Organization for Nuclear Research (CERN) Summer Student in 1990. He joined Philips Research, Eindhoven, The Netherlands, in 1994, as Senior Scientist to work on CMOS device technology, characterization, and reliability. In 2002, he was a Professor of Semiconductor Components, University of Twente, Enschede, The Netherlands. His research interests include CMOS post-processing, novel materials, silicon devices, and wafer-level electrical characterization of devices. He has (co)-authored over 200 scientific papers and holds 16 U.S. patents.

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