On-Line Pruning of ZBDD for Path Delay Fault ... - Semantic Scholar

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PAPER

Special Section on Recent Advances in Circuits and Systems

On-Line Pruning of ZBDD for Path Delay Fault Coverage Calculation∗ Fatih KOCAN†a) , Mehmet H. GUNES†b) , and Atakan KURT††c) , Nonmembers

SUMMARY Zero-suppressed BDDs (ZBDDs) have been used in the nonenumerative path delay fault (PDF) grading of VLSI circuits. One basic and one cut-based grading algorithm are proposed to grade circuits with polynomial and exponential number of PDFs, respectively. In this article, we present a new ZBDD-based basic PDF grading algorithm to enable grading of some circuits with exponential number of PDFs without using the cut-based algorithm. The algorithm overcomes the memory overflow problems by dynamically pruning the ZBDD at run-time. This new algorithm may give exact or pessimistic coverage depending on the statuses of the pruned nodes. Furthermore, we re-assess the performance of the static variable ordering heuristics in ZBDDs for PDF coverage calculation [1]. The proposed algorithm combined with the efficient static variable ordering heuristics can avoid ZBDD size explosion in many circuits. Experimental results for ISCAS85 benchmarks show that the proposed algorithm efficiently grades circuits. key words: path delay fault, simulation, on-line pruning, ZBDD

1. Introduction In today’s deep-submicron era, quality of very large scale integration (VLSI) circuits overly depends on the accuracy and preciseness of manufacturing process. A slightly inaccurate and imprecise manufacturing process might introduce defects into a chip. The defects are abstracted by fault models such as stuck-at, stuck-open, bridge, delay and IDDq faults [2]. Delay testing of VLSI circuits involves a test of the ability of the combinational circuit or combinational part of sequential circuits to propagate signals in a specified time period [2]. Figure 1 illustrates a delay fault example. In this figure, for some delay fault, the correct value of z arrives after the clock transition which results in storing the wrong logic value in the flip-flop. Four fault models were proposed for resistive bridge defects and process problems that change the timing behavior of a circuit. These are gate delay and its special case transition delay [3], path delay [4] and segment delay [5] fault models. The path delay fault model is the more realistic one and assumes that gate deManuscript received October 7, 2004. Manuscript revised February 4, 2005. † The authors are with the Computer Science and Engineering Department of Southern Methodist University, Dallas, Texas, USA. †† The author is with the Computer Engineering Department of Fatih University, Istanbul, Turkey. ∗ A small part of this paper was presented at the IEEE International Midwest Symposium on Circuits and Systems, 2004. a) E-mail: [email protected] b) E-mail: [email protected] c) E-mail: [email protected] DOI: 10.1093/ietisy/e88–d.7.1381

lays lumped on a path are enough to cause a failure. Also, a circuit may not have any defects to cause delay failure, however, it still may have path delay faults due to incorrect cycle time choice. Consequently, circuits are tested for path delay faults to ensure that they meet their timing requirements. Path delay fault (PDF) testing of a circuit requires the tasks of test vector simulation, test vector generation, and fault coverage calculation. Path delay fault simulation and coverage calculation can be enumerative or nonenumerative [6]. In enumerative fault simulation and coverage calculation, a test vector is simulated and the number of paths detected by the vector is counted one by one. The number of paths in a circuit is exponential with respect to the circuit size (e.g. c6288 has ≈ 1020 paths), therefore, the time and space complexities of the enumerative algorithms are very high. As a result, a line of research is performed to solve the PDF simulation and fault coverage computations nonenumeratively, which is proved to be NP-hard [7]. In [8], path status graph (PSG) data structure is used to store PDFs and count the number of detected PDFs nonenumeratively. In [9], an efficient set data structure, called ZBDD proposed in [10], is used to store and count PDFs with the set operations. All these data structures may require exponential size memory at worst case. Usually, to overcome memory problems of PDF coverage calculation algorithms, two complementing techniques are employed: (1) Instead of exact coverage calculation, estimated coverage is preferred and (2) a circuit is virtually cut (proposed in [6]) into overlapping subcircuits each of which has a unique set of PDFs, and grading is performed on the virtual subcircuits. For example, the authors of [9] propose a basic nonenumerative algorithm, which gives exact coverage, and a virtual-cutbased one. The primary disadvantages of cut-based grading are (1) the presumption of memory overflow before it really happens, (2) loosing coverage due to overlapping subpaths

Fig. 1

Delay fault example.

c 2005 The Institute of Electronics, Information and Communication Engineers Copyright 

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problem [9] and (3) not knowing the minimum number of cuts to avoid the memory overflow. Moreover, the coverage loss and the cost of coverage calculation would increase with the number of cuts. Finally, the authors of [11] presents a cut-based PDF grading algorithm that reduces the complexity of the cut-based algorithm of [9] from exponential to polynomial. In this article, we propose a new coverage calculation algorithm, which is a modification of the basic algorithm in [9], to enable grading of many circuits with huge number of PDFs without switching to the cut-based algorithm. The new algorithm overcomes the memory overflow problems at run-time. It performs on-line pruning of ZBDD based on the number of detected PDFs passing through the nets and their testability values in the circuit under simulation. The new algorithm may give exact or pessimistic coverage value depending on the timing of the pruning and the statuses of the pruned nodes, i.e., nets. Furthermore, we re-assess the performance of the static variable ordering heuristics proposed in [1] for the ZBDD-based coverage calculation application. The proposed heuristics are different from the existing ones since in PDF coverage calculation variables are the nets in the circuit, not primary inputs. The remainder of the article is organized as follows. In Sect. 2, ZBDD-based path delay fault coverage calculation is surveyed briefly. Several static variable ordering techniques in ZBDD for PDF coverage calculation are presented in Sect. 3. The on-line ZBDD pruning algorithm is introduced in Sect. 4. The experimental results for the ordering heuristics and the proposed algorithm are given for ISCAS85 benchmarks in Sect. 5. Finally, in the last section, we conclude our work and give future directions.

Fig. 2

Table 1

Circuit c17.

Physical paths.

Physical Paths 1 · 10 · 22 2 · 16 · 22 2 · 16 · 23 3 · 10 · 22

3 · 11 · 16 · 22 3 · 11 · 16 · 23 3 · 11 · 19 · 23 6 · 11 · 16 · 22

6 · 11 · 16 · 23 6 · 11 · 19 · 23 7 · 19 · 23

2. ZBDD-Based PDF Coverage Preliminaries PDFs are detected by applying a set of a pair of test patterns to the circuit: the first pattern in a pair initializes the circuit while the second one propagates the fault. PDFs can be detected robustly, non-robustly, or functionally; however, the type of detection is an issue in simulation and test generation, not in coverage calculation. In coverage calculation, we apply test vectors one by one and find the ratio of uniquely detected PDFs over total number of PDFs. The coverage calculation must be repeated for every type of detection, if needed. In this work, we concentrate on robustly covered PDFs. We use c17 in Fig. 2 to illustrate the relationship between physical paths and PDFs, and also set-based coverage calculation. Table 1 lists all physical paths in c17. There are two PDFs on each physical path: (1) slow-to-fall and (2) slow-to-rise. These faults are modeled from the corresponding physical path by subscripting the first variable of the path with r (for rising fault) or f (for falling fault). For example, 1r · 10 · 22 and 1 f · 10 · 22 are the two faults on physical path 1 · 10 · 22. The primary inputs of c17 are the nets labeled 1, 2, 3, 6 and 7: nets 6 and 7 correspond to the 4th and 5th in-

Fig. 3

PDFs detected by v1 and v2 .

puts of the circuit, respectively. Thus, in a vector vi =< d1 , d2 , d3 , d4 , d5 >, di is the logical value the ith primary input. The two vectors v1 =< s0, s1, p1, s1, s0 > and v2 =< s0, p1, p1, s0, s0 > detect the highlighted paths in Figs. 3 (a) and (b), respectively. Here, si means the value of the line in the first pattern and in the second pattern is i; pi means the value of the line in the second pattern is i and in the first pattern is the opposite. v1 covers two PDFs: 3r · 11 · 16 · 22, and 3r · 11 · 16 · 23. Similarly, v2 covers 2r · 16 · 22 and 2r · 16 · 23. Therefore, the PDF coverage of these two vectors is 4/22. ZBDD stores compactly all these PDFs by sharing subPDFs such as 16 · 22 and 16 · 23. Our on-line pruning algorithm utilizes the StorePDF() function of [9] to build the set of PDFs detected by a test

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vector nonenumeratively. The procedure associates a set with each net in the circuit. A set on a net holds all of the detected partial PDFs that end in that net. The set of partial PDFs ending at a gate is computed by taking the union of its fanins’ sets and also by appending the label of the gate to all PDFs in the union. The union of the sets of the primary outputs gives the set of detected PDFs by a vector. We use Fig. 3 (b) to illustrate the procedure StorePDF(). Example 1: Let si be the set of net i. Then, s1 = {}, s2 = {2r }, s3 = {}, s6 = {}, s7 = {}, s10 = s1 ∪ s3 = {}, s11 = {}, s19 = {}, s16 = (s2 ∪ s11 ) · {16} = {2r · 16}, s22 = (s10 ∪ s16 ) · {22} = {2r · 16 · 22}, s23 = (s16 ∪ s19 ) · {23} = {2r · 16 · 23}. Therefore, the set of PDFs detected by this vector is s22 ∪ s23 = {2r · 16 · 22, 2r · 16 · 23}. In addition to this procedure, we utilize the following ZBDD functions: • Count(zbdd z): Return the number of combinations (i.e. PDFs) in ZBDD z. • Subset1(zbdd z, element e): Returns a zbdd (or a pointer to it) which holds all members of z with e.

Fig. 4

Subset operations in ZBDD.

• Subset0(zbdd z, element e): Returns a zbdd (or a pointer to it) which holds all members of z without e. Figure 4 illustrates the subset operations in a ZBDD; Fig. 4 (b) and (c) are the ZBDDs returned by subset0(z, 16) and subset1(z, 16), respectively. In the following sections, we present two complementing techniques to minimize ZBDD size explosion during the PDF coverage calculation. 3. Static Variable Ordering Techniques Many heuristics have been proposed to order variables (representing primary inputs) in ZBDDs to avoid size explosion; however, in ZBDD-based PDF coverage calculations, the variables represent the nets in a circuit, not the circuit primary inputs. This fact motivates the authors of [1] to investigate new ordering strategies since the number of nets in a circuit is relatively large as compared to the number of primary inputs. A brief survey of the proposed heuristics follows the illustration of the impact of the static variable ordering on the ZBDD size. Figure 5 (a), (b) and (c) show the internals of a ZBDD for various variable (i.e. net) ordering techniques.

Fig. 5

Static ordering of variables.

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In Fig. 5 (a), (b) and (c), the ordering, starting from the root, is (3r ,6r ,11,16,19,22,23), (11,3r ,6r ,16,19,22,23) and (3r ,6r ,16,19,11,22,23), respectively. The ordering in Fig. 5 (b) results in the smallest number of nodes in the ZBDD. The following new static ordering heuristics in [1] are proposed based on structural properties of the circuit undergoing PDF coverage calculation. • Variable Frequency (H1 ): Frequency of a variable is defined to be the total number of paths passing through this variable. This heuristic orders variables according to their maximum frequencies and puts the highest frequency variable at the root of ZBDD. When there are variables with equal frequencies, priority is given to the variable at the lower level. In case, the variables are at the same level, one of them is picked arbitrarily. For c17 (see Fig. 2), one valid ordering is < G11 , G16 , G23 , G22 , G3 , G6 , G19 , G2 , G10 , G1 , G7 >. • Level-and-topology (H2 ): This heuristic orders variables according to their levels starting from primary inputs (see Fig. 2). Given a well-drawn circuit, variables at the same level are ordered based on circuit topology. For every alternating level, variables are ordered from left-to-right and right-to-left within level. For c17, one valid ordering is < G7 , G6 , G3 , G2 , G1 , G10 , G11 , G19 , G16 , G22 , G23 >. • Level-and-frequency (H3 ): Similar to H2 with the exception that the variables at the same level are ordered according to their frequencies and for equal frequencies the priority is given to the variable which topologically comes first. For c17, one valid ordering is < G3 , G6 , G2 , G1 , G7 , G11 , G10 , G16 , G19 , G23 , G22 >. • Backward-Variable Frequency (H4 ): In this heuristic, backward path count algorithm is run on the circuit and the variables are ordered in increasing order according to their path counts. Level and topology information is used to break ties among the equal path counts. For c17, one valid ordering is < G3 , G6 , G11 , G2 , G16 , G1 , G7 , G10 , G19 , G23 , G22 >. • Forward-Variable Frequency (H5 ): Similar to H4 with the exception that forward path counts are used in place of backward ones and also the variables are ordered from lowest to highest; the lowest one is at the root. Heuristics H4 and H5 are derived from the ordering heuristic in BDDs [12]. Our heuristic uses path counts as weights, which are different from their weights. For c17, one valid ordering is < G1 , G2 , G3 , G6 , G7 , G10 , G11 , G19 , G16 , G22 , G23 >. 4. PDF Coverage Estimation Algorithm In this section, we present a new PDF coverage estimation

Notation β ζt A(i)/Ai Rt (i)/Ri,t Lt (i)/Li,t S t (i)/S i,t U t (i)/U i,t Dt (i)/Di,t St DWi,t

Table 2 Nomenclature. Description The set of nets in a circuit The set of removed nets at time t The set/size of all PDFs of net i The set/size of removed PDFs of net i at time t The set/size of lost PDFs of net i at time t The set/size of stored PDFs of net i at time t The set/size of undetected PDFs of net i at time t The set/size of detected PDFs of net i at time t The set of all stored PDFs at time t Detection weight of net i at time t

algorithm as an improvement over the basic grading algorithm of [9]. The new algorithm is capable of grading more circuits than the original basic algorithm therefore many circuits may be graded with the improved algorithm without switching to the cut-based coverage calculation to avoid the disadvantages of cut-based grading in Sect. 1. Note that certain circuits may still require cut-based grading. The new algorithm overcomes memory problems at run time (if it occurs at all). Nevertheless, the new algorithm may also cause coverage loss only if memory overflow occurs truly and depending on the statuses of the pruned nets. The new algorithm proceeds as the basic algorithm, and whenever memory overflow occurs, it removes the PDFs of some nets from the set of the detected PDFs. A PDF, say x1 · x2 . . . xn−1 · xn , is a PDF of net i iff net i ∈ {x1 , . . . , xn }. The algorithm picks a candidate net i, and removes all of its PDFs currently in the set. Selecting a net and removing its PDFs continues until the memory size drops below a threshold size. Note that, during the course of grading, memory problems may occur at different times. Therefore, each time, select-and-remove operations are repeated. Intuitively, we should choose a net for removal at some point in time (1) whose current coverage is relatively high, and also (2) it is unlikely that a new, undetected PDF of this net will be detected with the remaining test vectors. Whenever a PDF of a removed net is detected, the PDF would be assumed as re-detection and would not be admitted to the set of detected PDFs. In short, after a net is removed, all forthcoming PDFs of this removed net will be rejected, whether they are new or re-detected. Thus, rejected new PDFs will be lost because of this policy. However, note that, selecting a fully covered net for removal does not cause any loss in the coverage. The following subsections formulate the computations of undetected PDFs and detection weights of nets at run time, and also give the details of the proposed algorithm. The notations used in computations are listed in Table 2. 4.1 Computation of Undetected PDFs at Run-Time In order to calculate the number of undetected PDFs of net i at time t (Ui,t ), we need to know, in addition to Ai , the sizes of the sets of lost PDFs Lt (i), detected-and-removed PDFs Rt (i), and in-store detected PDFs S t (i) of this net at that time. The relationship among all these sets of net i is

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Algorithm 1 Remove Net(S t (i), i) Require: S t (i): The stored set of detected PDFs of i at t Require: i: Current net to remove for each net j ∈ S t (i) do R j,t ← R j,t + Count(S ubset1(S t (i), j)) end for Ri,t ← Ri,t + Count(S t (i))

Fig. 6

Fig. 7

Statuses of PDFs of net i at time t.

Forward and backward path counts on the lines of c17.

depicted in Fig. 6 and in Eq. 1. Note that among these sets, only S t (i) is stored in memory. From the sizes of the sets, Ui,t is calculated according to Eq. 2. Ai = Ri,t + Li,t + Ui,t + S i,t

(1)

Ui,t = Ai − Ri,t − Li,t − S i,t

(2)

Using gate-level path counting algorithms, we compute the maximum number of PDFs of net i, Ai , as follows. First, a forward path counting algorithm computes the forward path count values, and then a backward one computes the backward path count values. The details of path counting algorithms are covered in [6]. The maximum number of paths passing through a net is the multiplication of forward and backward path count values on this net. Hence, the maximum number of PDFs of a net is twice as the number paths passing via this line. Next example illustrates computation of the maximum number of PDFs on the lines. Example 2: Figure 7 illustrates the computation of forward and backward path count values on c17. The forward and backward path count values on the lines are given in a tuple: The first (second) element indicates the forward (backward) path count. For example, the number of paths passing through line 3, 4, 16, 17 and 23 are 1 × 4, 1 × 1, 3 × 2, 3 × 1 and 6 × 1, respectively. Hence, the maximum number of PDFs passing through these lines are 8, 2, 12, 6, and 12, respectively, i.e. A3 = 8, A4 = 2, A16 = 12, A17 = 6, and A23 = 12. To compute Ui,t , Ri,t , Li,t and S i,t must be known as well. Removal of net i implies removal of all of its detected PDFs that are currently in the set. As PDFs are removed from the stored set, Rs of all affected nets are updated. For example, when a PDF of net i, say x1 · x2 · . . . · i · . . . · xn−1 · xn , is

removed because of removal of i, not only is Ri incremented but also all R x j for j ∈ [1, n] is incremented by one. Note that some detected PDFs of this net may have been removed before because of removals of other nets earlier. Algorithm 1 shows the process of updating the removed number of PDFs of each involved net nonenumeratively. After every net removal, we update Li,t of all unremoved nets as follows. Let i be an un-removed net. Then, Eq. 3 can be used the compute the number of lost PDFs of i at time t. In the results section, we show that if all PDFs in a circuit are stored in a ZBDD, then the number of final nodes in that ZBDD is equal to the number of nets in the circuit. Therefore, computation of A(i) with subset operation is not costly.







 (3) Li,t =

A(i) ∩  A( j)

− Ri,t



j∈ζt

Since calculation of Li,t might be costly, we neglect this value in the calculation of Ui,t . This simplified version of ∗ is given in Eq. 4. Ui,t called Ui,t ∗ = Ai − Ri,t − S i,t Ui,t

Note that the set of all stored PDFs at time t is  St = S t (i)

(4)

(5)

i∈(β\ζt )

and the set of stored PDFs of net i is S t (i) = S ubset(S t , i)

(6)

Furthermore, during the course of grading, the following relation (Eq. 7) holds for all nets. S i,t + Ri,t ≤ Di,t ≤ S i,t + Ri,t + Li,t

(7)

4.2 Computation of Detection Weights at Run-Time Testability metrics for delay faults are presented in [13], [14]. Let Cl,r be the controllability measure of propagating 1p to line l, and Ol,r be the observability measure of logic 1p on the line. Similarly, let Cl, f be the controllability measure of propagating 0p to line l, and Ol, f be the observability measure of logic 1p on this line. From these two measures, two testability measures of net l are computed according to Eqs. 8 and 9. In summary, Wl,r (Wl, f ) measures the hardness of setting line l to 1p (0p) and propagating it to any primary outputs. (8) Wl,r = Cl,r × Ol,r

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Algorithm 2 On-line pruning algorithm pd fd ← 0 ζ←φ Compute Wi, f and Wi,r of all nets Compute Ai for all nets S ← Empty() for every test Vi = (Vi1 , Vi2 ) ∈ V do Nd ← S imulate(Circuit, Vi ) P(Vi ) ← S torePDF(Nd ) for each removed net p ∈ ζ ∩ Nd do P(Vi ) ← subset0(P(Vi ), p) end for S ← Union(S , P(Vi )) while memory size threshold exceeded do Find a net j with min DW j S ( j) ← subset1(S , j) pd fd ← pd fd + Count(S ( j)) ζ ← ζ ∪ { j} Remove Net(S ( j), j) S ← subset0(S , j) end while end for Total coverage ≥ Count(S ) + pd fd

5. Experimental Results We performed two sets of experiments to re-assess the performance of ordering heuristics and assess the performance of the pruning algorithm with a set of automatically generated robust test vectors (i.e., by a deterministic ATPG). We used the ISCAS85 benchmarks described in Table 3. For each benchmark, we tabulated the number of inputs and outputs (I/O), nets (Nets), paths (Paths), the number of robust test vectors (Vectors) and the coverage of robust test vectors (Coverage). We also used ZBDD functions available in CUDD package [15]. All experiments were performed on Pentium IV, 2.4 GHz, and 1 GB RAM with Linux OS. 5.1 Results for Ordering Heuristics

Wl, f = Cl, f × Ol, f

(9)

We use testability measures of the nets in conjunction with the number of undetected PDFs to realize the heuristic: Low testability and low un-detection together implies low detection weight. In short, the detection weight of net i at time t (DWi,t ) is computed according to Eq. 10. ∗ DWi,t = Ui,t × (Wi, f + Wi,r )

(10)

The concept of removing some PDFs at run time, whenever there is a memory problem, is incorporated into the basic PDF grading algorithm of [9]. The steps of this algorithm are given in Algorithm 2. In this algorithm, Simulate() performs a path delay fault simulation and returns the subcircuit detected by a vector. P(Vi ) is the ZBDD of the PDFs which are detected by vector vi . The algorithm precomputes testability measures of, and the maximum number of PDFs of the nets in a circuit. It proceeds as the basic algorithm and, whenever we detect a memory problem, it employs the idea of net removing. At the end, the sum of the number of removed PDFs, pd fd , and the number of PDFs in the stored set of PDFs, S , would give the lower bound on the number of detected PDFs. Table 4

We run the basic coverage algorithm of [9] with the proposed variable ordering heuristics. Table 4 tabulates the performances of the heuristics when the set of robust test vectors are applied. It presents the performance in terms of final, peak node counts and build times for each heuristic. In the T otal row, we give the sums of the final nodes and the ZBDD build times of the circuits. We observe that the performance trends of the heuristics are consistent with the published ones in [1], in which a set of random robust test vectors were applied. H1 is the worst in final node counts and at least 2.5 times larger than H2 − H5 for all benchmarks. H2 − H5 are very close to each other in their final node counts. In terms of peak node counts, H4 gives the smallest peak node counts for all benchmarks. H4 is on average 1.85 times smaller than H1, H2, H3 and H5 for all benchmarks. Furthermore, in terms of ZBDD build time, H4 outperforms the others 1.21 times on average. H4 captures the topological structure of the circuit and also puts Table 3 c880 c1355 c1908 c2670 c3540 c5315 c7552

Description of benchmarks.

I/O

Net

Paths

Vectors

Coverage

26/60 41/32 33/25 233/140 50/22 178/123 207/108

417 514 855 1053 1647 2184 3404

8642 4173216 729057 679960 28676670 1341305 726494

7189 43389 37265 11529 20161 18177 52457

7484 17911 27064 10619 25752 37421 52019

Heuristics: (Final Nodes/Peak Nodes/Build Time (sec)) in ZBDD Manager.

Name

H1

H2

H3

H4

H5

c880 c1355 c1908 c2670 c3540 c5315 c7552 Final Peak Time

17865/44968/3.34 38884/73584/6.84 54980/110376/16.45 10267/128772/22.42 107850/205422/29.67 33169/145124/82.08 71488/196224/236.13 334503 904470 396.33

4649/78694/3.08 6325/52122/6.34 26820/81760/17.23 3400/233016/36.25 22968/101178/21.83 10044/246302/96.11 16445/323974/303.89 90651 1117050 484.73

4361/60298/2.91 6427/52122/6.36 24397/87892/17.02 3526/159432/32.78 22646/93002/22.17 10506/128772/60.67 16658/258566/222.51 88521 840084 364.42

4433/36792/2.56 6281/43946/5.98 24328/74606/12.33 4111/120596/18 23397/75628/29.09 11287/70518/69.77 18320/75628/215.67 92157 497714 353.4

4259/59276/2.98 6427/52122/6.42 24344/87892/17.95 3961/159432/36.42 22339/93002/25.69 9888/127750/41.66 16048/256522/238.16 87266 835996 369.28

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the nets with the highest frequencies closer to the root of the ZBDD. If a high-frequency net is placed somewhere close to the leaves of the ZBDD, then we increase the probability of creating more duplicates of the same net, thereby increasing the probability of increasing the total number of nodes in the ZBDD. We believe that the success of H4 is due to capturing the structure of the circuit and the frequencies of the nets simultaneously. Additionally, we stored all of the PDFs in a circuit assuming that a fictitious vector set detected all of the PDFs (as in Table X of [9]) and reported the number of live (Final) and peak (Peak) nodes, and the ZBDD build time (Time) in the first of half of Table 5. In this experiment, the variables are statically ordered in the ZBDD according to H4. In the second half of the table we included the results from Table X of [9] in which the results were given for the same experimental setting. For example, storing all PDFs of c880 requires 687 live and 50078 peak nodes, and 0.3 sec in our setting while 9,708 live nodes and 1.32 secs in [9]. Our method reduces the number of nodes significantly and builds the ZBDD faster than their ordering method in all benchmarks except for c5315. 5.2 Results for the Pruning Algorithm Table 6 tabulates the results for our basic and dynamic pruning algorithms in the first half and the robust results of the basic algorithm of [9] in the second half. The results of dynamic pruning are given inside the parenthesis as the differences from the respective basic values. The authors of [9] provides two sets of results for different set of robust test vectors in Tables VII and VIII, respectively. In terms of coverage, the results in Table VII of [9] close to our results, although our robust vector set is significantly larger than theirs. Therefore, we only compare our results with the robust results in Table VII of [9]. From Table VII, we excerpted the number of vectors (Vectors[9] ), the coverage of Table 5 c880 c1355 c1908 c2670 c3540 c5315 c7552

Storing all PDFs.

Final

Peak

Time

Final[9]

Time[9]

687 937 1189 1870 2291 3749 5016

50078 257544 261632 162498 627508 245280 499758

0.3 0.6 1.2 4.6 5.5 13.1 19.2

9,708 122,107 79,878 53,529 155,649 109,815 131,017

1.32 8.91 8.48 6,10 39.44 8.28 22.70

Table 6 Name c880 c1355 c1908 c2670 c3540 c5315 c7552

Live 4649(-266) 6325(-335) 26820(-352) 3400(-221) 22968(-35) 10044(-891) 16445(-161)

Peak 86870(-4088) 61320(-8176) 83804(-12264) 179872(-0) 87892(-0) 104244(-9198) 124684(-2044)

the vector set (Coverage[9] ), final node count (Final[9] ) and ZBDD build time (T ime[9] ). In our basic algorithm, no pruning is applied at run time and H4 is used as the ordering heuristic. For each circuit, the number of live nodes (Live), peak nodes (Peak), simulation time (Time), and coverage (Coverage) are tabulated. The number of removed PDFs (Removed PDFs) due to pruning is reported for the pruning algorithm. Note that with Live nodes we mean the maximum number of nodes reached during the course of grading which is different from the final node count. For example, in c880, the basic algorithm calculates the coverage in 2.55 sec. with a total of 4649 live and 86870 peak nodes in ZBDD manager. The total coverage is 7484 PDFs. For dynamic pruning algorithm, we mimic the memory overflow problem by applying pruning at three times: after application of 90%, 92%, and 95% of the test vectors. Under this scenario, in c880, the pruning algorithm calculates the coverage in 2.55 + 0.64 sec. with a total of 4649 − 266 live and 82782 − 4088 peak nodes in the ZBDD manager. The reported coverage is 7484 − 6 PDFs: 6 PDFs are lost because of the removal of some nodes on the detected PDFs. Removed PDFs column indicates that 681 PDFs are removed from the ZBDD as a result of pruning. The results indicate that our basic algorithm outperforms the basic algorithm of [9] in terms of number nodes in ZBDD. However, in some large benchmarks our basic algorithm requires more ZBDD time due to the large number of test vectors used in our experiments: compare Vectors column in Table 3 to Vectors[9] column in Table 6. Dynamic pruning algorithm requires more time and less number of nodes than our basic algorithm and looses coverage in some benchmarks. This coverage loss can be avoided by careful selection of the nodes for removal from the ZBDD, by examining the remaining vector set. In our experiments, we tried the pruning three times toward to the end of coverage calculation process. A few pruning did not yield noticeable reduction in the ZBDD size and also the additional operations such as Remove Net() in the pruning algorithm resulted in increase in grading time compared to our basic grading algorithm. 6. Conclusions and Future Work We proposed a new ZBDD-based PDF grading algorithm to enable grading of many circuits with huge number of PDFs without using the cut-based algorithm. The proposed algorithm combines an efficient static variable ordering heuristic

Comparison of the our basic, pruning and basic[9] algorithms. Time 2.55(+0.64) 6.13(+1.37) 16.48(+2.79) 17.91(+3.5) 21.2(+1.71) 47.53(+4.66) 185.97(+21.02)

Coverage 7484(-6) 17911(-0) 27064(-1) 10619(-88) 25752(-0) 37421(-6) 52019(-4)

Rem. PDFs 681 1458 516 879 76 1900 423

Vectors[9] 1,596 9,856 7,647 2,403 4,377 4,038 16,121

Coverage[9] 6,599 16,843 22,953 9,230 21,873 33,922 52,566

Final[9] 8,846 15,480 34,319 10,411 40,278 26,282 40,602

Time[9] 2.54 11.52 22.94 6.03 25.85 22.28 95.52

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and on-line pruning of the ZBDD. The on-line pruning algorithm dynamically prunes the ZBDD during the coverage calculation whenever a memory overflow occurs. This algorithm may result in coverage loss depending on the statuses of the pruned nodes. Experimental results show that the proposed techniques outperforms the published results in terms of the number of nodes and ZBDD-build time. In the future, we will investigate better techniques to prune the ZBDD. These heuristics should identify and remove the nodes from ZBDD that cause the ZBDD size explosion. Acknowledgments The authors thank Professors M.K. Michael and S. Tragoudas for providing the robust test vectors. Additionally, we thank the reviewers, whose comments improved the paper.

[14] W.C. Wu and C.L. Lee, “A probabilistic testability measure for delay faults,” Proc. ACM/IEEE Design Automation Conference, pp.440– 445, 1991. [15] F. Somenzi, “CUDD: CU decision diagram package,” Deparment of Eletrical and Computer Engineering, Univ. of Colorado, Boulder, http://vlsi.colorado.edu/˜fabio/cuss

Fatih Kocan received his BS degree in Computer Science and Engineering at Hacettepe University in Turkey. Later, he received his M.Sc. and Ph.D. degrees in the area of Databases and VLSI/CAD areas, respectively, from Case Western Reserve University. He is currently at Southern Methodist University, Dallas, TX, U.S.A. His current area of research includes algorithms, VLSI/CAD and FPGA/CAD.

References [1] F. Kocan, M.H. Gunes, and M. Thornton, “Static variable ordering in ZBDD for path delay fault coverage calculation,” Proc. IEEE Int’l. Midwest Symp. on Circuits and Systems, pp.I-97, I-500, 2004. [2] M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000. [3] J.A. Waicukauski, E. Lindbloom, B.K. Rosen, and V.S. Iyengar, “Transition fault simulation,” IEEE Des. Test Comput., vol.4, pp.32– 38, April 1987. [4] G.L. Smith, “Model for delay faults based upon paths,” International Test Conference, pp.342–351, Nov. 1985. [5] K. Heragu, J.H. Patel, and V.D. Agrawal, “Segment delay faults: A new fault model,” Proc. IEEE VLSI Test Symposium, pp.32–39, April 1996. [6] I. Pomeranz and S.M. Reddy, “An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.13, no.2, pp.240–250, Feb. 1994. [7] D. Kagaris and S. Tragoudas, “On the nonenumerative path delay fault simulation problem,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.21, no.9, pp.1095–1101, Sept. 2002. [8] M.A. Gharaybeh, M.L. Bushnell, and V.D. Agrawal, “The pathstatus graph with application to delay fault simulation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.17, no.4, pp.324– 332, Sept. 1998. [9] S. Padmanaban, M.K. Michael, and S. Tragoudas, “Exact path delay fault coverage with fundamental ZBDD operations,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.22, no.3, pp.305– 316, March 2003. [10] S. Minato, “Zero-suppressed BDDs for set manipulation in combinatorial problems,” Proc. ACM/IEEE Design Automation Conference, pp.272–277, 1993. [11] F. Kocan and M.H. Gunes, “On the zbdd-based path delay fault coverage calculation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.24, no.7, July 2005. [12] S. Minato, N. Ishiura, and S. Yajima, “Shared binary decision diagram with attributed edges for efficient boolean function manipulation,” Proc. ACM/IEEE Design Automation Conference, pp.52–57, 1990. [13] H.C. Tsai, K.T. Cheng, and V.D. Agrawal, “A testability metric for path delay faults and its application,” Proc. ASP Design Automation Conf., pp.593–598, Jan. 2000.

Mehmet H. Gunes received B.S. degrees in electronics engineering and computer science and engineering from Isik University, Istanbul, Turkey, in 2002, and MS degree in computer engineering from Southern Methodist University, Dallas in 2004. He is pursuing the PhD degree in Computer Science at the University of Texas at Dallas. His current research interests are VLSI/CAD and networks.

Atakan Kurt received his BS degree in Computer Science and Engineering at Hacettepe University in Turkey. Subsequently he received his M.Sc. and Ph.D. degrees in the area of Databases from Case Western Reserve University. He is currently teaching at Fatih University in Turkey. His current area of research includes algorithms, databases, XML, and web services.