Optimization of Floor-Planning using Genetic Algorithm - ScienceDirect

Available online at www.sciencedirect.com

Procedia Technology 4 (2012) 825 – 829

C3IT-2012

Optimization of Floor-planning using Genetic Algorithm T. Singhaa, H. S. Duttab, M. Dec b

a Royal Thimphu College, Thimphu,, Bhutan Kalyani Government Engineering College, Kalyani, Nadia, India. c DETS, Kalyani University, Kalyani, Nadia, India.

Abstract Floor-planning is one of the key design flow of VLSI chip designing process. This paper presents a novel approach to solve the VLSI floor planning problems. This approach is based on iterative prototypes optimization with evolved improvement (POEMS) algorithm. It uses a genetic algorithm (GA) for local search on each iteration, because both algorithms have already proven useful for solving similar problems. It adopts a non-slicing structure B* tree for the placement of rectangle modules. B*-trees are based on ordered binary trees. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree operations, like search, insertion, and deletion in only O(1), O(1) and O(n) times respectively. While existing representations for non-slicing floor-plans need at least O(n) time for each of these operations, where n is the number of modules. GA has been implemented and tested on popular benchmark problems. Experimental results show that GA can quickly produce optimal solutions for all tested benchmark problems.

© 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of C3IT Open access under CC BY-NC-ND license. Keywords: Floor-planning; POEMS algorithm; Genetic algorithm; B*-tree Representation.

1.

Introduction

Floor planning decides how to arrange the modules on a chip under the constraint that no two modules are overlap while controlling the area, wire length, and other performance indices to be optimal. So the goal of this paper is that to find out a good floor-planning technique which gives a better optimal solution in chip designing. Floor-plans can be divided into two categories, the slicing structure and the non-slicing structure. A slicing structure can be represented by a binary tree whose leaves denote modules and internal nodes specify horizontal or vertical cut lines. For non slicing floor plans, there are different techniques such as sequence pair [1], bounded slicing grid (BSG)[2], O-tree[3] and B* tree[4, 5]. Sequence pairs can be used to floor plan hard rectangular blocks by simulated annealing [6, 7, 9].To handle non-slicing floor-plans, this paper propose an iterative optimized framework which uses GA for local search on each iteration and adopts an ordered binary-tree based representation, called B*-trees[5] for the placement of rectangle modules. Inheriting from the particular characteristics of the ordered binary tree, the B*-tree has many advantages compared with other representations. The B*tree is very flexible,

2212-0173 © 2012 Published by Elsevier Ltd. Open access under CC BY-NC-ND license. doi:10.1016/j.protcy.2012.05.135

826

T. Singha et al. / Procedia Technology 4 (2012) 825 – 829

very fast and easy for implementation. It does not need to construct constraint graphs for area cost evaluation. 2. Methodology 2.1. POEMS algorithm The POEMS method [8] works in iteration. Before the first iteration, an initial solution is generated. This solution is called a prototype. The aim of the following iterations of the POEMS algorithm is to find the best modification of the prototype with use of the genetic GA, which serves as a modification optimizer. The prototype modifications are obtained by applying sequences of defined actions onto the prototype solution. If an improvement is found after each iteration, the prototype is replaced. In every iteration, a steady-state genetic algorithm is executed in order to find the optimal action sequence. First, a population of N random action sequences of length L is created. The sequences are composed of individual actions and their parameters. The evolution is started, and a selection, crossover and mutation operators are used in order to breed the action sequences. The fitness function of each action sequence is defined as a fitness of the prototype solution after being modified by the particular sequence evaluated. The overall program schema is shown in figure 1. 2.1. 1. Prototype A prototype is the initial solution created and improved by the POEMS algorithm. Its creation is a very important step, because the initial position highly influences the space searched. As the solutions are binary trees, so best fit heuristic method is introduced here to create trees from the initial set of modules. 2.1.2. Best-fit heuristic method The best-fit heuristic is a general name for a greedy rectangle packing algorithm. The principle is to select the best fitted module for each hole in the final placement. Both holes and modules are stored in a queue and the algorithm iterates until the module queue is empty. After each placement of the module, the whole list is updated. In this method first, it rotates all modules so they are wider than higher and sorts them by width (descending) and height (ascending). This array represents a queue of the modules. Then, the tree is built level by level. On each level, a certain limited horizontal space must be filled. Initially, the space to be filled equals to the width of the widest rectangle or the square root of all modules area, whichever is bigger (this is further referred as the original value). Until the module queue is empty, the algorithm selects the first module from the queue, which can be placed into the space. Then, the module is removed from the queue and the space is shortened by its width. If there is no such module small enough to fit into the space, the current level is ended and a new level is started with the space reset to the original value. 2.1.3. Actions Each action in the POEMS algorithm [8] represents a certain parameterized modification of the prototype. Every action has a Boolean flag that enables or disables the action. If the action is disabled, it does nothing to the input tree. Individual actions are joined together to sequences that are optimized by the GA. This algorithm used six actions- rotate action, flip action, mirror action, exchange value action, exchange node action and hang node action. Rotate action flips and mirrors sub-trees of every node in the whole sub-tree starting from the specified tree node. Flip action flips (rotates) the module of the specified tree node. A mirror action changes the left and the right child of the specified tree node. This action does nothing on the leaf node. An exchange value action takes two specified nodes and swaps their values. The tree structure is not changed; only the shape of resulting placement is different. The exchange node action takes the first node specified and inserts it at the position of the second node specified. The second node is placed on the original position of the first node. This operation is permitted only if the first node does not lie in the sub-tree of the second node and vice versa. A hang node action takes the specified source node and places it as the left or the right child of the target node specified. If the target node is located in

T. Singha et al. / Procedia Technology 4 (2012) 825 – 829

the sub-tree starting from the source node, nothing is done. If the target node contains a child at the target position, the child is replaced by the source node and inserted at the original position of the source node.

Fig. 1: Overall program schema

2.2. Genetic Algorithms (GA) The genetic algorithm [6] is a method for solving both constrained and unconstrained optimization problems that is based on natural selection, the process that drives biological evolution. At each step, the genetic algorithm selects individuals at random from the current population to be parents and uses them to produce the children for the next generation. Over successive generations, the population "evolves" toward an optimal solution. Here each individual in the population of GA represents a sequence of actions, which, if applied to the prototype floor-plan, creates another floor-plan. 2.2.1.Fitness Function The fitness value used is the negative amount of the unused area (TUA) (total area of the enclosing rectangle without the area of placed modules) i.e. q(f) = í TUA(f). 2.2.2.Selection Here roulette selection procedure is used to select parent. Roulette selection chooses parents by simulating a roulette wheel, in which the area of the section of the wheel corresponding to an individual is proportional to the individual's expectation. The algorithm uses a random number to select one of the sections with a probability equal to its area. 2.2.3.

Multi Point Crossover

This paper used three point crossover methods to shuffle the different characteristics of an individual and create children out of parents inheriting the characteristics directly. As in two point crossover method it chooses three points A, B and C at random and based on these three the offspring’s are generated. So the characteristics of parents are uniformly distributed among the children. 2.3. Mutation Mutation options specify how the GA makes small random changes in the individuals in the population to create mutation children. Mutation provides genetic diversity and enables the GA to search a broader space. This paper proposes uniform mutation method. It is a two-step process. First, the algorithm selects a fraction of the vector entries of an individual for mutation, where each entry has a probability Rate of being mutated. In the second step, the algorithm replaces each selected entry by a random number selected uniformly from the range for that entry. 2.4. B*-Tree Representation

827

828

T. Singha et al. / Procedia Technology 4 (2012) 825 – 829

B*-Tree [5, 10] is an efficient, flexible, and effective data structure for non-slicing floor-plans. During the creation of prototype by using the best-fit heuristic method, a B*-tree is being built. The first module placed in space is marked as the B*-Tree root. The next module in the same level is placed as the left subtree of the previous module and the first module on the next level as the right sub-tree of the first module in the current level. In this way the tree is built. Each node in a B*-Tree gets a unique integer number, which is used as its address. As each address is an integer, minimum and maximum values must be known at the creation time. Minimum value is defined as 0, maximum value as n-1, where n is a number of modules in the problem set. 3. Experimental results The experiment employed MCNC/GSRC benchmarks [13, 14] for the VLSI floor-planning problem. It compared with Simulated Annealing (SA) and Differential evolution (DE) algorithms. The results obtained in this project are better compared to other techniques. The experimental results are shown in Table 4.1 for Area estimation. 3.1. GSRC benchmark Two benchmarks (n10, n100) were selected from GSRC [14] and tested. The results are shown in Table 4.2. In the table, setup parameters with the resulting used area, unused area statistics and the computation time are displayed. The test indicates that the longer (in the terms of iterations) is the algorithm executed, the higher quality of the result can be achieved. Table 4.1: area comparisons

Table 4.2: The GSRC benchmark results

ami33 ami49

No. of Modules 33 49

SA Area (mm2) 1.36 43.34

Xerox

10

Hp

9

Circuits

DE Area (mm2) 1.22 36.22

GA Area (mm2) 1.17 35.45

20.47

19.19

19.35

9.57

9.293

8.83

Test n10 n10 n100 n100

I

G

10 100 10 100

10 10 10 10

N 3 3 3 3

S 50 50 50 50

Used area 0.223 0.223 0.179 0.179

Unused area 0.017 0.009 0.036 0.025

Table 4.3: MCNC benchmark results Test Ami33 Ami33 Ami49 Ami49 Xerox Xerox Hp Hp

3.2.

I 10 100 10 100 10 100 10 100

G 10 10 10 10 10 10 10 10

N 3 3 3 3 3 3 3 3

S 50 50 50 50 50 50 50 50

Used area (mm2) 1.16 1.16 35.44 35.44 19.35 19.35 8.83 8.83

Unused area (mm2) 0.162 0.082 7.4 5.65 1.78 1.57 0.883 0.553

MCNC benchmark

Five benchmarks (ami33, ami49, apte, hp, Xerox) were selected from MCNC [13] and tested. The results are shown in Table 4.3. The algorithm performance trend is the same as for GSRC benchmarks. The result of this benchmark also shows that as the number of iteration increases the better optimization

829

T. Singha et al. / Procedia Technology 4 (2012) 825 – 829

is achieved by decreasing the unused area. In Ami33, 12.3% area is unused when I is 10 and 6.6% area is unused when I is 100. So as iteration increase better optimization is achieved.

(a)

(b)

(c)

(d)

Fig.2.(a) n100 (17% Dead when I=10), (b) n100 (12.4% Dead when I=100), (c) Ami33(12.3% dead ), (d) B* tree of the placement.

4.

Conclusions and Future Scope

The algorithm is implemented using the Java programming language and tested on public benchmark data available on the website (GSRC [13], MCNC [14]). The results were compared with the SA (simulated annealing) and DE (differential evolution) algorithms [10]. It was very difficult to compare all algorithms simultaneously as most of them have multiple setup parameters, which significantly influence the solution quality and the computation time. The experiments show that the suggested algorithm is competitive in quality, and even slightly better than all the other algorithms tested. Therefore a solution for the 2D rectangle packing problem (floor-planning) is designed, implemented and tested. Now further development of the algorithm could include dealing with pre-placed or soft modules, rectilinear modules. That can be done by splitting these rectilinear shapes into rectangles and modifying the placing algorithm to keep those corresponding rectangles compacted. Another possibility is to calculate the wire length between the blocks and optimize it. In that case fitness calculation will be changed. References 1.

H. Murata, K. Fujiyoshi, S. Nakatake, and Y.Sajitani,“VLSI module placement based on rectangle-packing by the sequence-pair,” IEEE Trans. on Computer Aided Design, vol. 15, pp. 1518-1524, Dec. 1996. 2. S.Nakatake, K.Fujiyoshi, H.Murata, and Y.Kajitani,” Module Placement on BSG-Sructure and IC layout Applicaios,”Proc.ICCAD,pp 484- 491,1996. 3. P.-N. Guo, C.-K. Cheng, and T. Yoshimura, “An O-Tree Representation of Non- Slicing Floorplan and Its Applications,”Proc.DAC, pp. 268–273, 1999. 4. R.Stron and K.Price, “Differential evolution-a simple and efficient adaptive scheme for global optimization over continuopus spaces”, Tech.Rep. TR-95-102, International computer science Institute (ICSI), Berkely, Calif, USA, March 1995. 5. Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu,“B*-Trees: A new representation for nonslicing floorplans,” Design Automation Conference, pp. 458-463. 2000. 6. Guo P.N., Takahashi T., Cheng C.-K., Yoshimura T.: Floorplanning Using a Tree Representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 281–289, 2001. 7. T.C. Chen, Y.W. Chang: Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing, IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 24, pp. 637- 650, 2006. 8. J. Kubalik, J. Faigl, “Iterative Prototype Optimisation with Evolved Improvement Steps”, Lecture Notes in Computer Science, Springer, 2006. 9. M. Tang, and X. Yao, “A Memetic Algorithm for VLSI Floorplanning”, IEEE Transactions on Systems, Man, and Cybernetics, Part B, vol. 37, pp. 62-69, 2007. 10. D. J. Moni, S. Arumugam and D. G. N. Rani, “VLSI Floor Planning relying on Differential Evolution Algorithm”, AIML Journal, vol. 7, pp. 62-67, 2007. 11. http://vlsicad.eecs.umich.edu/BK/CompaSS/results/mcnc opt.html 12. http://vlsicad.eecs.umich.edu/BK/CompaSS/results/gsrc opt.html