Performance-constrained worst-case variability minimization of VLSI ...

Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits A. Dharchoudhury and S. M. Kang Department of Electrical and Computer Engineering, Beckman Institute and Coordinated Science Laboratory University of Illinois at Urbana-Champaign, IL 61801. Abstract{ This paper describes a new technique to design circuits such that the variability of the circuit performances due to device parameter uctuations meets specications for all values of the environmental parameters (such as operating temperature or voltage supply). The worst-case value of the performance variability is minimized and specications on the nominal value of the performance measure are handled simultaneously. Response surface models are used to provide ecient and accurate estimates for the performance values and variability during the optimization. This technique has been successfully applied to signicantly increase the parametric yields of a BiCMOS voltage-to-current converter circuit and a CMOS clock driver circuit.

I. Introduction VLSI circuit performances are functions of three kinds of circuit parameters: (a) designable parameters such as nominal channel widths of MOS devices, (b) device parameters such as MOS gate-oxide thickness and threshold voltage, and (c) environmental conditions such as operating temperature, power supply voltages and circuit excitations. The randomly varying device parameters and environmental conditions are also called internal noise and external noise parameters, respectively 1]. The variability in a circuit performance measure due to the internal noise parameters alone is called internal variability . The objective in many statistical design problems is to design circuits which satisfy, for all environmental conditions, some speci cations on the internal variability of the circuit performance. In addition, there may be speci cations on the nominal value of the performance measure. Traditional variability minimization approaches do not distinguish between internal and external noise parameters, and seek to minimize the This research was supported in part by the Joint Services Electronics Program (N00014-90-J-1270) and by the Semiconductor Research Corporation (SRC92-DP-109).

total performance variability. Moreover, they adopt a two-stage Taguchi-like technique of rst minimizing the variability and then tuning the nominal performance value. The technique presented in this paper minimizes the worst value (with respect to the external noise parameters) of the internal performance variability. This ensures that the internal variability speci cations are met for all values of the external noise parameters. Furthermore, constraints on the nominal value of the performance measure are handled simultaneously with the variability minimization. This approach is called performance-constrained worst-case variability minimization (PC-WCVM).

II. Formulation The n designable parameters (transformed, if necessary) are denoted by d and the design space is denoted by D
R d . The n internal noise parameters are assumed to be correlated Gaussian random variables they can be transformed into a set of independent zero-mean Gaussian random variables, denoted by the random vector u. Thus, u  MV G(0 ), where  is the diagonal covariance matrix of u. The n external noise parameters can be scaled such that the resultant transformed external noise vector e is distributed uniformly over the hypercube H = ;1 1] e . Each of the above transformations is linear and the original circuit parameters can be easily obtained from the transformed parameters. The circuit performance measure r is a function of d, u and e. Thus, d

n

u

e

n

r = r(d u e)

(1)

where r(:) is an implicitly known function. This implicit function (equivalently, the simulator) is replaced by a response surface model 2, 3]. For the purposes of this work, a quadratic response surface of r in terms of d, u and e is used, but the proposed variability minimization methodology is independent of the particular

modeling technique used. The response surface model for r is denoted by r^(:). Consider the variability in the performance measure that is caused by the internal noise parameters alone. This internal variability can be quanti ed by an average measure such as the mean ^ and a deviation measure such as the standard deviation ^ . Both these quantities are functions of d and e only, since the eect of u has been averaged out. In particular, ^ and ^ can be estimated by the following formulae, where N is the size of a Monte Carlo sample of the internal noise parameters. N (2) ^r (d e) = N1 ^r(d u e) i=1

Notice that a single performance measure leads to a multi-criteria optimization (MCO) problem in 7 multiple performance measures can, therefore, be handled within the same formulation. Moreover, the above formulation handles both internal variability and nominal value speci cations for r simultaneously. This is more direct and general than the \on-target" strategy of Taguchi 4, 5]. The inner-maximization, which computes the worst-case internal variability, leads to a non-dierentiable objective function for the WCVM and the PC-WCVM problems.

N 2 ; i=1 N ; 1 ^r : (3) The standard deviation ^ will be used to develop our formulation any other statistical variability measure may be equivalently used. In this paper, we consider the following variability minimization problem: nd d 2 D s:t: ^r (d e) < ub 8 e 2 H: (4) Here  is a speci cation on the standard deviation of the circuit performance measure, and H is the hypercube de ned earlier. This is a natural statement of the statistical design problem in many cases where the objective is to satisfy an (internal) variability speci cation for all values of the external noise parameters (e.g. for all values of temperature in a given range). The above problem is equivalent to the following worst-case variability minimization (WCVM) problem: nd d 2 D s:t: ^rwc (d) = max ^ (d e) < ub (5) e2H r

The functional relationship between the circuit parameters and the performance measure is approximated by a response surface model, denoted by r^(:). This model is constructed as follows: (i) Obtain M points in the d, u, e]-space using Latin Hypercube Sampling (LHS) 6]. (ii) Simulate the circuit and extract the performance values at these M design points. (iii) Fit a model for the performance measure in terms of the circuit parameters using these M values. For the purposes of this paper, the Maximally Flat Quadratic Interpolation (MFQI) technique 3] is used to do the tting, but many other methods are available. Since the response surface is valid within a certain sampling region, it loses accuracy when the design points obtained during optimization move beyond this region. When such a situation arises, a new response surface is constructed and the optimization is restarted from the last point 7].

r

r

r

r

X

^r (d

e

vuu XN ) = t N 1 1 ^r(

{

d u{ e)2 ;

r

ub

where the maximum of the internal performance variability ^ over the hypercube H is its worst value ^ (d). The nominal value of the performance measure is de ned as ^r0(d) = ^r(d u0 e0 ) (6) where u0 and e0 are the nominal values of the internal and external noise parameters, respectively1 . Constraints on the nominal performance value may be imposed leading to the performance-constrained worstcase variability minimization (PC-WCVM) problem: nd d 2 D s:t: ^rwc (d) < ub and a  ^r0 (d)  b (7) wc r

r

Note that ^ is a function of d only, whereas ^r is a function of d and e. 1

r0

III. Implementation Details A. Circuit Performance Modeling

B. Computing Worst-Case Internal Variability

At particular values of d and e, the value of the internal performance variability is computed based on a Monte Carlo sample of the internal noise parameters using the response surface r^(:) (e.g. the standard deviation is computed via (3)). The simplistic procedure outlined below computes the worst-case value of the internal variability (over the hypercube H ) at a particular design point d. (i) Obtain P = N e equally spaced grid points in H , denoted by e1 e2 : : : e . (ii) Compute ^ (d e ), for i = 1 2 : : : P . (iii) ^ (d) = maxf^ (d e ) i = 1 : : : P g. n

P

wc r

r

{

r

{

Since n is usually small (1-4), the number P is not e

unreasonably large. Note that Step (ii) requires N response surface evaluations for each of P grid points, where N is the size of a Monte Carlo sample of the internal noise parameters. Since response surface evaluations are computationally inexpensive however, the cost of the above process is not prohibitive. An optimization-based method may also be used to compute the worst-case internal variability. The technique described here is, however, much simpler to implement and has been found to be suciently accurate in practice. C. Optimization Techniques and Circuit Penalty Two techniques have been used as the optimization engines for PC-WCVM: (i) Simplex Method and (ii) Quadratic Programming Method. The objective function for both these techniques is called the circuit penalty and is described below. First, a variability penalty p (d) is de ned as wc (8) p (d) = 100 ( ^r (d) )


ub




where  is the user-speci ed upper-bound on the internal variability. Next, de ne a performance penalty p (d) as follows. Let a and b denote the lower and upper bounds, respectively, on the nominal performance value r^0 . If a smaller value of r is more desirable (e.g. r is a delay measure), p (d) is de ned as ub

r

r

0 pr (d) = 100 ( ^r b(d;) ;a a ) (9) If, on the other hand, a larger value is more desirable (e.g. r is the gain of an ampli er), p (d) is de ned as 0 pr (d) = 100 ( ^r a(d;) ;b b ) (10) Both the variability and performance penalties assign a penalty of 0 to a \good" value and a penalty of 100 to a \bad" value. Linear interpolation is used for intermediate values. Various other nonlinear relationships between the penalty and the actual value may be used, based on the relative desirability of the values. The circuit penalty p(d) is taken to be the larger of p (d) and p (d). The circuit penalty serves as the objective function during PC-WCVM. This technique is similar to the minimax method of converting an MCO problem to a single objective optimization problem. r




r

IV. Applications to VLSI Circuits The worst-case variability minimization technique described in this paper has been implemented in iEDI-

SON3.0 8]. In this section, we present two casestudies of the application of this methodology: a BiCMOS voltage-to-current converter circuit and a CMOS clock driver circuit. A. BiCMOS Voltage-to-Current Converter Circuit

This circuit, shown in Fig. 1, converts the input voltage V to an output current I . The variability minimization problem is to design the circuit such that the ratio of the standard deviation to the mean value of I is less than 1% for all values of V in the operating range. The designable parameters are the nominal values of R1 and R2 , denoted by DR1 and DR2, respectively. The internal noise parameters are: (i) random variation in R1 , (ii) random variation in R2 , (iii) random variation in R , (iv) channel length reduction of M1, (v) channel length reduction in M2, (vi) variation in forward beta of npn transistors, and (vii) variation in forward beta of pnp transistors. The external noise parameter is the input voltage V , which varies over a range of 15V, 30V]. In this example, LHS is used as the experimental design technique and MFQI is used to t a quadratic response surface of I in terms of the designable and external and internal noise parameters. The Simplex method is used as the optimization engine. In the rst experiment, the WCVM approach is used to minimize the ratio of the standard deviation ^ and the mean ^ of I . There are no constraints on the nominal value of I . The results are shown in Table I, where ^0 and ^0 denote the mean and the standard deviation of I when the external noise parameter V is at its worst-case value for (^ =^ ). A total of 145 SPICE simulations are required to reduce the worst-case value of (^ =^ ) by 60% and to increase the parametric yield from 60% to 99%. There is no signi cant improvement beyond this nal design point, indicating that this point may be a local minimum. Since the value of the standard deviation increases by a large amount in the rst experiment, the second experiment uses the PC-WCVM approach with the standard deviation as the variability measure and imposes constraints on the nominal value of I . Table I shows the worst-case value of ^ , the nominal value r^0 , and the worst-case value of the ratio (^ =^ ) at the initial and nal design points of this experiment. A total of 225 SPICE simulations are required and the parametric yield is increased to 100% at the nal point. Both experiments show a large improvement in the parametric yield of the optimized circuit as compared to that of the initial circuit. It is to be noted that the optimizations above are done in stages, in

out

out

in

ext

in

out

r

r

out

out

r

r

out

in

r

r

r

r

wc

out

r

r

r

VDD VDD

Vbias M3

M4

INM

Q4

INP M1

M2

Q2

Q5

R ext

OUT

V in

Q1

Q6

R1

I out M5

R

Q3

2

GND

Figure 1: BiCMOS Voltage-to-Current Converter Circuit TABLE I Results of Experiment 1 and Experiment 2 for Voltage-to-Current Converter Circuit Expt. 1 Expt. 2

Initial Final

DR1 (K )

DR2 (K )

0.7 28.0 2.277 8.245 DR1 (K ) DR2 (K ) Initial 0.7 28.0 Final 3.28 18.42

(^r =^r )wc (%) ^0r (A) ^r0 (A) Yield (%) Sim. 3.16 8.43 0.267 60 1.26 89.24 1.12 99 145 ^rwc (A) r^0 (A) ( ^r =^r )wc (%) Yield (%) Sim. 0.27 12.63 3.16 60 0.62 84.95 0.76 100 225

where each stage entails the construction of a new response surface as explained in Section IIIA. B. CMOS Clock Driver Circuit

The CMOS clock driver circuit is shown in Fig. 2(a). The performance measure of interest is the clock skew S , which is de ned to be the larger of the rising skew S1 and the falling skew S2 (Fig. 2(b)). The designable parameters are the nominal widths of the transistors M1 (DW 1), M2 (DW 2), M3 (DW 3), M4 (DW 4), M5 (DW 5), and M6 (DW 6). The internal noise parameters are the gate-oxide thickness, the channel length and width reduction of the NMOS transistors, and the channel length and width reduction of the PMOS transistors. The external noise parameters are the power supply voltage EV dd varying from 4.75V to 5.25V and the operating temperature ETnom varying from 300C to 800 C. The variability minimization problem is to ensure that (i) the spread in the value of S is less than 0.05 ns for all values of EV dd and ETnom and (ii) the nominal value of S is less than 0.5 ns. At particular values of d and e, the response surface for S is used in conjunction with a Monte Carlo sample of the internal noise parameters to compute the clock skew values. The dierence between the maximum and minimum of these values is the estimated spread s^ (d e). Note that the nominal r

value r^0 is the value of the clock skew when both the internal and external noise parameters are nominal, and it is dierent from the mean which is the average over the internal noise parameters. The PC-WCVM approach is used and the objective is to minimize s^ subject to constraints on r^0 . The quadratic programming method (as implemented in NPSOL 9]) is used to perform the optimization. As seen from Table II, the worst-case value of the spread in the clock skew is reduced by 87% and the nominal value is reduced by 72.5%. A total of 260 simulations are required to construct the response surfaces during the various stages of the optimization. The initial design point does not satisfy the constraint on the nominal clock skew and the parametric yield is therefore zero at that point. The parametric yield at the nal design point is 100%. r

wc

V. Conclusions In this paper, a new technique for minimizing the variability of VLSI circuit performances has been presented. In many practical statistical design problems, the objective is to nd the values of the designable parameters such that the internal performance variability meets speci cations for all operating conditions. The technique described in this paper computes the worst-case value of the internal variability with respect to the external noise parameters. This worst-

MP1

CLK MP2

MP3 CLK

MN1

MN2

MN3 time

CLKin

S MP4

CLK

MP5

r

S

f

CLK MN4

MN5 time

Figure 2: (a) CMOS clock driver circuit, (b) Illustration of rising skew S1 and falling skew S2 TABLE II Results of PC-WCVM for Clock Driver Circuit Initial Final

Design Point d (m) 3,6,3,6,3,6] 1.7,11.1,16.3,26.9,2.5,38.6]

case variability is then minimized by varying the design point. This ensures that the internal variability speci cation is met for all external parameter values. Constraints on the nominal value of the performance measure are handled simultaneously with the variability minimization. Experimental design and response surface methods are used to model the circuit performance in terms of the designable and internal and external noise parameters. The successful and ecient application of this performance-constrained worst-case variability minimization method has been demonstrated. In a BiCMOS voltage-to-current converter circuit, the parametric yield is increased from 60% to 100%. In a CMOS clock driver circuit, the variability of the clock skew is reduced by 87% and the nominal value is reduced by 72.5%. Multiple performance measures can be elegantly handled in the proposed framework, and its implementation is the subject of future work.

s^r wc

(ns) r^0 (ns) Yield (%) Sim. 0.311 1.398 0 0.04 0.384 100 260

3] 4] 5] 6] 7]

Acknowledgment We would like to thank Dr. Norman Elias of Philips for providing the voltage-to-current converter circuit and for many helpful suggestions and discussions.

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8] 9]

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