... 45nm CMOS technology in Cadence Virtuoso Analog Design Environment at. 45nm technology and simulated using Spectre simulator. This adder cell can be ...
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ScienceDirect Procedia Materials Science 10 (2015) 789 – 792
2nd International Conference on Nanomaterials and Technologies (CNT 2014)
Power-Aware Alternative Adder Cell Structure Using Swing Restored Complementary Pass Transistor Logic at 45nm Technology T. Bhagyalaxmi*, S. Rajendar, S. Srinivas a
Vardhaman College of Engineering, Shamshabad, Hyderabad, India
Abstract In this paper, a novel low power 20T alternative adder cell featuring modified swing restored complementary pass transistor logic (SR-CPL) is proposed. This alternative adder cell structure performs better in terms of power dissipation, propagation delay and power-delay-product (PDP) when compared with 26T SR-CPL and other adder cells implemented using conventional logic styles. As compared with 26T SRCPL adder cell, the proposed adder cell reduces power by 23.15%, delay by 6.15% and PDP by 27.91%. This design is carried-out using a TSMC 45nm CMOS technology in Cadence Virtuoso Analog Design Environment at 45nm technology and simulated using Spectre simulator. This adder cell can be used as a computation element in various DSP architectures and microprocessors resulting in high performance. © Published by Elsevier Ltd. This © 2015 2015The TheAuthors. Authors. Published by Elsevier Ltd. is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the International Conference on Nanomaterials and Technologies (CNT 2014). Peer-review under responsibility of the International Conference on Nanomaterials and Technologies (CNT 2014) Keywords: swing restored complementary pass transistor logic, adder cell, logic style, low power, power-delay-product
1. Introduction The fundamental arithmetic operation which is widely used in DSP architectures and microprocessors is addition. The adder cell is used in many modules to perform operations such as subtraction, multiplication, division etc. In many of these systems, the critical path of adder determines the performance of the system. Therefore, there is always been an increasing research contributions in the area of arithmetic computation. On the other hand, the power consumption is critically important in modern integrated circuits especially for low voltage, low power applications. There are three major sources of power dissipation in CMOS circuits: switching power, short-circuit power and leakage power. Reducing any of these components of sources of power dissipation
2211-8128 © 2015 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the International Conference on Nanomaterials and Technologies (CNT 2014) doi:10.1016/j.mspro.2015.06.021
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will lead to overall system power reduction. Apart from this, in modern high performance processing applications, there is a need for the design of very high speed circuits. The power-delay-product metric relates the amount of energy spent during the realization of the desired task (Mariano Aguirre-Hernandez et.al.,2011). The PDP of the adder cell would affect the systems overall performance (A. M. Shams et.al., 1999). This Paper presents a novel low power adder cell using an SR-CPL logic style with an alternative logic structure. This proposed full-adder cell is more power efficient and reduces the number of transistors as compared to the conventional SRCPL based adder cell. This paper is organized as follows. Section II describes the existing full-adder cells implemented in various logic styles: Static CMOS, CPL, DPL and SR-CPL. Section III proposes a novel low transistor count (20T as compared to 28T SR-CPL), low power adder cell. Section IV presents the discussion on simulation results and comparisons of performance metrics of the proposed design with the existing design mentioned in the literature. Finally, conclusions are presented in section V. 2. Existing Full-Adder Cells Different logic styles have been discussed in the literature for the optimization of low power full-adder. The various logic styles considered for the performance comparison with the proposed alternate logic structure are static CMOS (standard CMOS) (N. Weste et.al., 1998), complementary pass transistor logic (CPL) (K. Yano et.al.,1990), double pass transistor logic (DPL) (Mariano Aguirre-Hernandez et.al.,2011) and swing-restored complementary pass transistor logic (SR-CPL) (R. Zimmerman et.al., 1997). The static CMOS logic style is straight forward and universal but results in high input loads due to substantial number of large PMOS transistors. The CPL consists of fast differential stage due to the cross coupled CMOS pull-up transistors. This differential stage, on the other hand, leads to considerably large short circuit currents. DPL provides full swing on the output signals. The combination of large CMOS transistors and insufficient dual-rail logic makes DPL not competitive to other pass transistor logics and to static CMOS. SR-CPL is derived from CPL which performs swing restoration and output buffering at the same time. This logic style is used in the proposed design and the logic structure is modified to reduce the power and area. 3. Proposed Alternate Structure For Full-Adder Cell The proposed alternate logic structure shown in Fig. 1 is derived from the swing-restored complementary pass transistor logic with some modifications in the carry generation structure which reduces power and area due to reduced number of transistors. The proposed full-adder cell implementation requires only equivalence gates (XOR/XNOR) along with primary inputs A, B and C and their complementary inputs A , B and C . The Sum and Cout expressions are Sum
Cout
A B C A B C A A B C A B
Fig. 1 Block Diagram of the Proposed Adder Cell Logic Structure
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The equivalence gates (XOR/XNOR) are realized using swing restored complementary pass transistor logic and the Sum and Cout expressions are realized using two multiplexers as shown in Fig. 2. As compared with adder cell implemented using SR-CPL logic, this proposed logic eliminates 6 transistors involved for the computation of AND/OR logic. As the number of transistors decrease, the complexity and thereby the area and power consumption decreases. By using this scheme, the critical path delay for both sum and carry generation is same and these signals are generated at the same time.
Fig. 2 Proposed Alternate Structure for Full-Adder Cell
4. Results and Discussions The proposed adder cell structure is compared with the existing full adder cell structures to obtain their performance metrics. Fig. 3 shows the simulation setup model. The schematics were designed using a TSMC 45nm CMOS technology in Cadence Virtuoso Analog Design Environment, and simulated using Cadence Spectre Simulator. Table I shows the simulation results for the performance comparison of full adders, regarding power consumption, propagation delay and PDP. All the full adders were supplied with 1.0V and the maximum frequency for the inputs was 1GHz. From the simulation results, it is evident that the power consumption is decreased by 23.15% and power-delayproduct is reduced by 27.91% as against the conventional 26T adder using SR-CPL. The decrease in the transistor count eventually results in the optimum utilization of the device area.
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Fig. 3 Simulation Setup Model
Table I. Performance Metrics Comparison of Various Adder Cells Logic Style
Transistor
Power
Delay
PDP
Count
(uW)
(ps)
(uW*ps)
Static CMOS
28
1.75
68.45
119.78
CPL
30
4.10
62.01
246.36
DPL
28
2.48
28.15
69.81
SR-CPL
26
2.29
29.92
68.51
Proposed Adder Cell
20
1.76
28.08
49.42
6. Conclusions An alternative full adder logic structure using swing restored complementary pass transistor logic is proposed. In order to analyze the advantages of this adder cell, the performance is compared with several other full adder cells. From the simulation results, it is evident that the performance metrics like power dissipation, propagation delay and PDP are optimized for this proposed design. Hence this adder cell can be used as a computation element in various DSP architectures and microprocessors resulting in high performance. References A. M. Shams and M. Bayoumi, 1999. Performance evaluation of 1-bit CMOS adder cells, in Proc. IEEE ISCAS, Orlando, FL, 27-30. K. Yano, K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, 1990. A 3.8 ns CMOS 16x16-b multiplier using complementary pass-transistor logic, IEEE J. Solid-State Circuits, 388-395. Mariano Aguirre-Hernandez and Monico Linares-Aranda, 2011. CMOS Full-Adders for Enery Efficient Arithmetic Applications, IEEE Tran. on VLSI Systems, 718-721. M. Suzuki, M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, 1993. A 1.5 ns 32-b CMOS ALU in double pass-transistor logic, IEEE J. Solid-State Circuits, 1145-1150. N. Weste and K. Eshraghian, 1998. Principles of CMOS VLSI Design, A System Perspective. Reading, MA: Addison-Wesley, ch. 5. R. Zimmerman and W. Fichtner, 1997. Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid-State Circuits, 1079-1090. S. Agarwal, V. K. Pavankumar, and R. Yokesh,2008. Energy-efficient high performance circuits for arithmetic units, in Proc. 2nd Int. Conf. VLSI Des, 371-376. T. Bhagyalaxmi, S. Rajendar, Y. Pandu Rangaiah, 2014, Performance Analysis of Alternative Adder Cell Structures using Clocked and NonClocked Logic Styles at 45nm Technology, Proc. IEEE ICACCI, New Delhi, 620-623.
