Low-Complexity Filter and Interpolator Design for ATSC DTV Systems Yong-Kyu Kim, Chang-Seok Choi and Hanho Lee
Jin-Gyun Chung
Department of Information and Communication Engineering Inha University, Incheon, Korea E-mail :
[email protected]
Division of Electronic Engineering Chonbuk National University, Jeonju, Korea
Abstract—This paper presents the low complexity partially folded architecture of a transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200MHz and 385MHz, respectively. Keywords-component; digital signal processing(DSP), FIR filter, interpolation, digital TV(DTV)
I.
The interpolator is generally used to calculate new samples at arbitrary time instants in between existing discrete-time samples. A polynomial-based interpolation filter can be efficiently implemented by using Farrow architecture [4]. Interpolation methods using polynomials have been investigated [5][6]. Among others, spline interpolations are very useful methods for smoothing out noisy data [7]. This is because they offer a good tradeoff between simplicity and efficiency in controlling the degree of smoothing. In this paper, we present a low-complexity FIR filter and interpolator of DTV tuner components for ATSC systems. Also, a novel architecture of the FIR filter and interpolator are proposed with the aim of reducing hardware complexity and improving interpolation efficiency. This design has a lower number of gate counts and a shorter critical path delay in comparison to the conventional architecture. II.
INTRODUCTION
In order to administer limited frequency resources and offer higher quality service, the existing analog TVs have been replaced with digital TVs in many countries. For this transition, the Advanced Television Standard Committee (ATSC) standards [1] have been proposed. With these ATSC standards, a Digital TV (DTV) receiver for the cable broadcasting system is required. This receiver has been used in many fields, including High-Definition TV (HDTV), set-top boxes, VCR/DVDs, and PDAs. In particular, the DTV tuner is one of the DTV receivers and is a major power expender. Therefore, low-cost DTV tuner Integrated Circuits (ICs) for the digital TV system are required. They play a role in selecting the desired frequency and down-converting for the intermediate frequency. The digital FIR filter and interpolator are the most fundamental Digital Signal Processing (DSP) components for the CMOS DTV tuner. The FIR filter has the advantages of stability and easy implementation, but the large number of filter taps can lead to excessive hardware complexity. Therefore, folding techniques [2][3] have been proposed as a means of reducing hardware. A significant advantage of the folded FIR filter architecture is that it can lead to reduce the hardware complexity compared to the corresponding unfolded one. The sampling frequency of the FIR filter output is generally increased by the interpolator.
FIR FILTER AND INTERPOLATOR DESIGN FOR DTV TUNER
As shown in Fig. 1, the DTV tuner consists of a digital FIR filter, interpolator, up-converter, and analog circuits. In this section, we show the steps for designing the digital FIR filter and interpolator. A. Low complexity FIR Filter Design With respect to the FIR filter in the DTV tuner, low complexity is the primary goal for minimizing the hardware size and power consumption. Therefore various low area reduction strategies have been applied. To reduce hardware complexity, several techniques such as the filter design with non-multiplier, Canonical Signed Digit (CSD) representation of coefficients, and folding techniques are used. Also, Common Sub-expression Elimination (CSE) methods based on CSD coefficients can reduce the number of adders required for the multipliers of FIR filters. CSD methods have been used to minimize the non-zero bits. However, CSD methods are not appropriate for the high order FIR filter Design. In [8] a CSE algorithm using binary representation of coefficients is presented for the implementation of a higher order FIR filter. The FIR filter using this algorithm has a lower number of adders than that of the CSD-based CSE method. The CSE method, which is same as Binary Sub-expression Elimination (BSE), is used to eliminate a redundant binary Common Subexpression (CS) that occurs within a coefficient.
"This research was supported by the MKE(The Ministry of Knowledge Economy), Korea, under the ITRC( Information Technology Research Center) support program supervised by the NIPA(National IT Industry Promotion Agency)" (NIPA-2011-C1090-1111-0007)
978-1-4577-0711-7/11/＄26.00 ⓒ2011 IEEE
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Figure 1. Block diagram of DTV tuner. Figure 2. Interpolation using Cubic spline function. TABLE I.
NUMBER OF GROUPED COMMON SUB-EXPRESSIONS OF FIR FILTER (138TAPS)
y recon (kT ) =
1
c((n
k
− l )Ts ) β 3 ((l + μ k )Ts )
(2)
l = −2
Binary representation of coefficient
CSD representation of coefficient
No. [1001]and [100-1]
67
32
No. [111]and [10-1]
54
59
No. [101]and [1001]
112
62
No. [11]and [101]
127
88
No. ungrouped CSs
11
18
ͤ
where Ն is the cubic B-spline function, c(nTs) are B-spline coefficients, and Րk is the fractional interval [9]. Assuming ͑Րk =0, coefficients can be determined by using Eq. (2) Y (nTs ) =
1
c((n − 1)T )β s
l = −2
3
(lTs )
(3)
1 (c((n + 1)Ts ) + 4c( nTs ) + c((n − 1)Ts )) 6 = (c ∗ hd )nTs =
In Table I, the occurrence frequency of a CS is defined as the number of the same CS being reused or repeated for the filter coefficients. The number of grouped CSs for a binary representation of coefficients is smaller than the CSD representation of coefficients. Therefore, the binary representation of coefficients is more favorable for reducing the adders in the filter. B. Interpolation Filter Design Using Spline Function Spline-based interpolation is a convolution-based interpolation where the interpolation kernel is a piecewise polynomial generated by a B-spline. It is composed of two operations: a preliminary iterative filtering to get the spline coefficients and a mixed discrete-continuous convolution to generate reconstructed samples at the interpolation range. Usually, B-splines of three degree (cubic) are preferred as they provide sufficient quality and acceptable computational load. As shown in Fig. 2, the cubic spline interpolation is a piecewise continuous curve, with continuous first and second order derivatives. A third degree polynomial is constructed between each point. In Fig. 2, it is assume that samples passed the FIR filter are y(nTs). After the FIR filter, samples y(nTs) are taken at uniform intervals Ts. The samples at correct symbol timing, t=kT, is interpolated from the samples y(nTs) using an interpola-tor. Based on the interpolation theory, the value of a reconstructed signal yrecon(t) can be expressed as
y recon (kT ) =
With the aid of the z-transform, the equation can be expressed [9]:
c( z ) =
s
s
−1 3 − 3 3 −6 3 1 S ( x) = 1 μ μ 2 μ 3 ⋅ − 3 0 3 6 1 4 1
[
]
1 ck −1 0 ck ⋅ 0 ck +1 0 c k + 2
(5)
An IIR filter has two poles. A preliminary iterative filter is divided into two filters as follows [12]: 6 p1 1
+ −1 p z 1 − 1 − p12 1 = H1 ( z ) + H 2 (z )
(1)
H iter ( z ) =
n = −∞
where h(t) is a interpolation function. In cubic B-spline, Eq. (2) can be substituted for Eq. (1). That is, Eq. (6) can be changed into
(4)
In Fig. 4, there are two parts, which are the IIR filter and approximate FIR filter [10]. In the IIR filter, the B-spline coefficients are determined by using input samples y(nTs). In the Farrow interpolation filter, the reconstructed samples yrecon(t) are calculated. The Farrow structure is a sufficient structure for obtaining piecewise polynomial approximations [10]. According to the piecewise polynomial model, the generation of reconstructed samples at an arbitrary position is possible. The cubic polynomial degree in the Farrow structure is represented by a 4x4 matrix. In the case of cubic B-spline interpolation kernel, the reconstructed samples are generated by the following equation [11]:
∞
y(nT )h(t − nT )
Y ( z) H d ( z)
− 6 p1 1 − p12
z
−1 z − p1
(6)
H1 is a 1 tap IIR filter and H2 is an approximate FIR filter, respectively
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(a)
Figure 3. Proposed partially transposed folded FIR filter architecture.
(b) Figure 5. Phase delay of (a) continuous delay control interpolation filter, (b) spline interpolation filter using sub-filter.
(a)
form between the folded and unfolded form of the filter, featuring higher throughput than the fully folded, and requiring less hardware than the unfolded.
(b)
The architecture of partially folded FIR filter architecture was shown in Fig. 3. And the detailed explanation of the proposed FIR filter architecture was addressed in our previous paper [13].
(c) Figure 4. Block diagram of the proposed (a) spline interpolation filter using sub-filter before reconstructing samples, (b) IIR filter H1(z), (c) partially folded approximated FIR filter H2(z).
III.
PROPOSED PARTIALLY FOLDED FIR FILTER AND SPLINE INTERPOLATOR USING SUB-FILTER
A. Proposed Partially Folded FIR Filter Architecture Folding technique has been proposed as a means of reducing the hardware complexity. Folding technique can be easily adapted to FIR filters since they includes a repetition of multiplication and addition. A significant advantage of the folded FIR architecture is that they lead to reduced hardware in comparison to the corresponding unfolded schemes and the clock skew problem does not exist. Also, the way of combining folded and unfolded filters is very efficient in comparison to the fully folded filters. Partially folded filter is an intermediate
B. Proposed Cubic B-Spline Interpolator using Sub-Filter In this section, cubic B-spline interpolator architecture using sub-filter is presented. The disadvantage of the conventional cubic B-spline is the increase of errors at a rapid slant. This leads to a deteriorated performance of the filter. It is possible to estimate the samples by using the spline polynomial after going by t. At this time, the dashed line placed on high is more deteriorated in comparison to the original signal that indicates a solid line. In order to decrease the errors, it is possible that a sample that has a more approximate position to the original curved line in comparison to the dashed line placed on high can be obtained if a sample at y0 can be moved to a position that has a sample value of y0+Յ. By moving Յ͑ up or down, the performance of interpolation can be improved. A movement Յ͑ can be expressed as a form of the sub-filter, as shown in Fig. 4(a). Also, the overall spline interpolation architecture can be divided into three parts: a composed IIR filter, an approximate FIR filter, and a cubic B-spline reconstruction filter. In general, the Farrow architecture of the continuous delay control has been widely used [4] in designing the interpolation filter. This structure has the disadvantage of increasing the constant multiplier and delay according to the filter coefficient. However, the cubic B-spline interpolation architecture has six constant multipliers, twelve adders, and three delay devices, multipliers, three adders, and three delay devices compared to the continuous delay control that has sixteen, respectively.
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TABLE II.
IMPLEMENTATION RESULTS OF SEVERAL FIR FILTER
filter has a folding factor of six, its latency has six times as long as that of the unfolded architecture.
ARCHITECTURES
Unfolded FIR filter Coefficient using BSE method Technol -ogy Total # of Gates Clock rates
Coefficient using CSD method
90-nm, 1.1V
Coefficient using BSE method 90-nm, 1.1V
Proposed Folded FIR filter Coefficient using BSE method 90-nm, 1.1V
Folded FIR filter
21,137
22,349
9,727
8,550
185 MHz
180 MHz
190 MHz
200 MHz
15Txor +13Tnand+Tf
12Txor+Tmux +11Tnand+Tf
Critical Path
15Txor +13Tnand+Tff
Latency
138 clocks (745 ns)
f
f
138 clocks (745 ns)
828 clocks (4305ns)
V.
This paper presents the design and implementation of the partially folded FIR filter and cubic B-spline interpolation filter using sub-filter for ATSC broadcasting DTV systems. To implement a low complexity FIR filter, the optimization of filter coefficients was needed. To do this, the CSE method, which shares coefficients expressed as binary representation, is used. Instead of using a delay unit, a control manner of the filter coefficients using a multiplexer is proposed. As a result, the proposed architecture has 60% less hardware complexity than the unfolded architecture. Also, it has 12% less hardware complexity than the other folded architecture. The overall interpolation filter architecture using sub-filter and cubic Bspline has a more efficient interpolation performance. Also, it has 16% less hardware complexity than the conventional continuous delay control architecture. The proposed FIR filter and interpolator has potential applications in DTV tuner for ATSC broadcasting DTV systems.
11Txor+Tmux+ 9Tnand+Tff 828 clocks (4140 ns)
TABLE III. IMPLEMENTATION RESULTS OF THE PROPOSED CUBIC BSPLINE STRUCTURE USING SUB-FILTER AND CONTINUOUS DELAY CONTROL ARCHITECTURE Continuous delay control structure
Proposed Cubic B-spline structure using sub-filter
90-nm, 1.1V
90-nm, 1.1V
Technology
REFERENCES
Total # of Gates
5,500
4,643
[1]
Clock Rates Critical Path
350 MHz 8Txor+Tmux+6Tnand+Tff
385 MHz 6Txor+Tmux+5Tnand+Tff
[2]
Latency
216 clocks (615 ns)
216 clocks (560 ns) [3]
IV.
CONCLUSION
RESULT AND COMPARISION
The proposed partially folded FIR filter and overall interpolation filter were designed in Verilog HDL and simulated to verify its functionality by using MATLAB and ModelSim. The synthesis steps were carried out by using SYNOPSYS design tools and 90-nm CMOS technology optimized for a 1.1V supply voltage. Table II shows the implementation results of the proposed partially folded FIR architecture, unfolded architecture, and conventional folded architecture. The proposed partially folded FIR filter architecture operates approximately at a clock frequency of 200 MHz and requires approximately 60 % and 12% fewer gate counts than the unfolded and conventional folded architecture, respectively. The latency of the proposed architecture is six times as long as that of the unfolded architecture because the folded architecture has a folding factor of six. In the unfolded part, architecture using coefficients expressed as binary representation has 6% less hardware complexity than the architecture using coefficients expressed as CSD representation. Table III shows the implementation results of the overall interpolation filter architecture. The proposed cubic B-spline interpolation filter architecture that uses the sub-filter has 16% less hardware complexity than the continuous delay control architecture. It also operates approximately at a clock frequency of 385MHz. Because the proposed interpolation
[4]
[5]
[6]
[7] [8]
[9] [10]
[11]
[12]
[13]
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