www.ietdl.org Published in IET Power Electronics Received on 26th September 2010 doi: 10.1049/iet-pel.2010.0311
ISSN 1755-4535
Reduced switching loss pulse width modulation technique for three-level diode clamped inverter P.K. Chaturvedi1 S. Jain2 P. Agarwal3 1
Electrical Engineering Department, Samrat Ashok Technological Institute, Vidisha, MP, India Electrical Engineering Department, National Institute of Technology, Bhopal, India 3 Electrical Engineering Department, Indian Institute of Technology, Roorkee, India E-mail:
[email protected] 2
Abstract: Multilevel inverters are used to reduce the harmonics and to achieve high-voltage, high-power capability but switching losses are increased because of increased device count. Switching losses can be reduced by either soft switching techniques or by modifying modulation technique employing space vector-based PWM techniques or sinusoidal PWM-based techniques. In this study, a carrier-based closed-loop control technique has been developed to reduce the switching losses based on insertion of ‘no switching’ zone within each half cycle of fundamental wave. It effectively reduces the switching losses of three-level inverter without need of any complex mathematical expressions as involved in space vector-based techniques. An improvement of about 5% in efficiency for a switching frequency of 5 kHz is observed with proposed technique over conventional SPWM technique based on efficiency improvement factor (EIF). Simulation and experimental results are presented to validate the proposed technique.
1
Introduction
Multilevel inverters have now become proven technology in medium- and high-voltage applications. They have the advantage of producing high-voltage, high-power capability with improved voltage quality. It also eliminates the use of problematic series–parallel connections of switching devices. Recent advances in power semiconductor technology results in development of fast switching devices such as insulated gate bipolar transistor (IGBT) and metal oxide semiconductor field effect transistor (MOSFET). It has made the use of highfrequency switching modulation techniques in power inverters to reduce the harmonic contents in output voltage. Generally, switching frequency is increased to reduce the filtering requirement in almost all the inverter topologies, which increases the switching losses thus reducing the system efficiency. Since there are 12 switching devices in three-level inverter and more in higher level inverters, switching loss problem becomes more serious. Fig. 1 shows the structure of three-level diode clamped inverter and Table 1 gives the switching sequences to generate the three-level output voltage for phase ‘A’. Conventional space vector (SVPWM) and other PWM techniques sacrifice with switching losses to improve the harmonic profile of the output voltage. Switching losses can be reduced by employing slight topological modifications to achieve soft switching technique [1] or by employing new type of switching technique such as zero current switching or zero voltage switching [2]. However, these methods cannot be applied directly to the ready-made system [3]. A flexible control platform is presented [1] that allows rapid prototyping of soft switching topologies. An analysis of different auxiliary resonant commutated pole IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393–399 doi: 10.1049/iet-pel.2010.0311
(ARCP) topologies shows that all switching commands can be synthesised with synchronised signals of two-level ARCP converters. The control platform is developed on an XCS2000 DSP card from AixControl and programmed in Verilog hardware description language (VHDL) [1]. Soft switching techniques for control of power converters are used to improve the performance of system, and it allows high-frequency operation with reduced acoustic noise and electromagnetic interference (EMI), reduced switching losses, reduced dv/dt and di/dt stress across each switch and better controllability. However soft switching operation restricts the modulation process at some stage such as in the case of resonant DC link topology, in which the benefits of using very high switching frequency are partially reduced when working with delta modulation technique. Comparison of SVPWM and SPWM techniques as applied in quasiresonant soft switched two-level inverter is proposed in [4]. SVPWM technique is proposed for closed-loop control of induction motor with reduced switching losses [5]. Proportional–integral (PI) regulators have been used to improve the steady state and dynamic performance. Kaku et al. [3] presented the switching loss reduction technique based on SVPWM by stopping the control pulses to devices for some duration. This duration is calculated instantaneously based on load power factor angle. A discontinuous modulation technique is presented in [6] to reduce the switching losses. In this method, the reduction of switching losses depends on load power factor therefore not suitable for multilevel inverters. However, three-level inverter provides 27 output voltage space vectors resulting in more complex control and the degree of freedom to generate the command vector increases. Complexity increases with number of levels. 393
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Fig. 2 Linearised switching characteristics of controllable switch (IGBT/MOSFET) [8]
Fig. 1 Structure of three-phase, three-level diode clamped inverter
Table 1 Sa1 1 0 0
Switching states of three-level diode clamped inverter Sa2
S ′a1
S ′a2
Output pole voltage (VAo)
Output phase voltage (VAn)
1 1 0
0 1 1
0 0 1
+Vdc +Vdc/2 0
+Vdc/2 0 2Vdc/2
A comparison of total harmonic distortion (THD) and switching losses in conventional two-level inverter with multilevel inverters (three-level and five-level) at different switching frequencies has been presented in [7]. It also optimised the switching frequency for lowest possible THD and switching losses. In this paper, a closed-loop, carrier-based control technique has been developed to reduce the switching losses based on insertion of ‘no switching’ zone within each half cycle of fundamental wave. It effectively reduced the switching losses of three-level inverter without any complex mathematical expressions as involved in space vector-based techniques. An improvement of about 5% in efficiency for a switching frequency of 5 kHz is observed with proposed technique over conventional SPWM technique in terms of efficiency improvement factor (EIF). Simulation and experimental results are presented to validate the proposed concept. For experimentation and consequently the generation of control pulses for all power switches of the inverter, dSPACE DS-1104 has been used as real-time control platform.
2
Switching loss calculations
In various applications of inverters, total power losses can be divided into following parts: switching losses, snubber losses, conduction losses and off-state losses. Generally, switching losses depend on switching frequency of power semiconductor devices and instantaneous value of device voltage and current during switching interval. In low switching frequency applications, the proportion of switching losses is very less and can be neglected because total switching time is much less than the switching cycle. Switching losses become dominant part of the total power loss in high switching frequency applications. Off-state 394 & The Institution of Engineering and Technology 2011
losses are insignificant for normal ambient temperature. Conduction losses are proportional to magnitude of load current [8]. Consider a single controllable switch (IGBT/MOSFET) connected across a DC voltage of value Vdc . Current through switch during ON time is considered as Idc . Fig. 2 shows the waveforms of voltage across and current through the switch when it is operated at a switching frequency of fs ¼ 1/Ts , where Ts is the switching period. To simplify the expressions, the switching waveforms are represented by linear approximations. In the figure, VM and iM are the voltage across and current through the MOSFET [3, 8 – 11]. Instantaneous voltage and current through the switch can be expressed as v(t) = Vdc − (Vdc − Von ) i(t) = Idc
t tc,on
t tc,on
(1) (2)
Hence the average switching power loss Psw and switching energy Esw in the switch are Psw
tc,on + tc,off tc,on + tc,off 1 1 V I V I = + (3) Ts Ts 6 dc dc 3 on dc 1 (4) Esw = Psw dt T
where tc,on is the turn on time and tc,off is the turn off transition time. Equation (3) shows that switching power loss in a semiconductor switch varies linearly with the switching frequency and switching times. Therefore with the devices having short switching times, it is possible to operate them at higher switching frequency, thus avoiding excessive switching power losses in the device [3, 8]. Equation (4) gives the total switching energy during turn-on and turn-off intervals.
3 Proposed reduced switching loss PWM technique This section presents the proposed reduced switching loss PWM technique to reduce switching losses without the need of load power factor angle using simple sinusoidal PWM strategy. Fig. 3 shows the block diagram of proposed method and Fig. 4 shows the control scheme. IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393 –399 doi: 10.1049/iet-pel.2010.0311
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Simulation results
A simulation model of the proposed technique is developed in MATLAB/Simulink environment. The parameters used for simulation study are given in Table 2. Phase voltage (Van), line voltage (Vab) and line current (ia) with conventional SPWM technique is shown in Fig. 5. Frequency spectrums of inverter line voltage (Vab), load line voltage and load current (ia) with conventional SPWM technique are shown in Fig. 6. The load voltage and load current are shown sinusoidal after filtering. Phase voltage (Van), line voltage (Vab) and line current (ia) with proposed Fig. 3 Block diagram of reduced switching losses PWM technique Table 2
Switching losses can be reduced by reducing either switching frequency or instantaneous values of voltage and current at the time of switching as indicated in (1) – (4). The presented technique is based on simple SPWM method with addition of variable off-set signal to the modulating waveform so that control pulses for devices are stopped for some duration (‘no switching’ zone) within each half cycle of fundamental wave. The positioning of this ‘no switching’ zone can be controlled by controlling the parameters of PI regulator at DC side and load side. To maintain the harmonic profile of inverter voltage, it is necessary to place the ‘no-switching’ zone at the centre of the positive and negative peaks of the load current. The controller consists of two regulators, one for DC voltage control and other for load voltage control with modulation index controller as given in Fig. 4. The PI and off-set calculator block determines the appropriate off-set signal to be added to actual modulating signal to compensate for any increase in switching frequency. This off-set signal continuously adjusts the ‘no switching’ zone within each half cycle of fundamental wave. The proposed method can be applied for any power factor angle therefore does not require sensing of power factor angle. Although, it is necessary to optimise the controller parameters to place this ‘no switching’ zone in the middle of the voltage wave within each cycle to optimise the switching loss and THD. The possible ‘no switching’ durations for each phase is 1208 in the positive half period and further 1208 in negative half period. Considering the symmetry of three phases, the ‘no switching’ duration must be 608 for positive and negative peak value region of load current, respectively [3]. The three-level PWM generator block places the ‘no switching’ duration appropriately according to the requirement.
Simulation parameters
DC link parameters DC link voltage DC link capacitor Filter parameters filter inductance filter capacitance Load parameters rated line-line voltage frequency load resistance load inductance switching frequency
680 V 2200 mF 5.2 mH 100 mF 415 V 50 Hz 15 V 24.2 mH 2 kHz
Fig. 5 Phase voltage (Van), line voltage (Vab) and line current (ia) with conventional SPWM technique (at switching frequency of 2 kHz)
Fig. 4 Control scheme of proposed reduced switching loss PWM technique IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393–399 doi: 10.1049/iet-pel.2010.0311
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Fig. 6 Harmonic spectrums a Inverter line voltage (Vab) b Load line voltage (after filter) c Load current (ia) with conventional SPWM technique
reduced switching loss PWM technique are shown in Fig. 7. Frequency spectrums of inverter line voltage (Vab),
load line voltage and load current (ia) with proposed reduced switching loss PWM technique are shown in Fig. 8. The load voltage and load current are still shown sinusoidal after filtering with the same filter components. It is clear that, for approximately 608 durations, the switching pulses are stopped thus reducing the switching losses for the same switching frequency. Load voltage (after filter) is almost same in both the cases in terms of its magnitude and THD. However, line current is somewhat more distorted because of redistribution of charge among two DC link capacitors. Load voltage and current THD are still within 5% limit imposed by IEEE 519-1992 standard. The performance of the proposed reduced switching loss PWM technique is verified using EIF which is given as EIF =
Fig. 7 Phase voltage (Van), line voltage (Vab) and line current (ia) with reduced switching loss PWM technique 396 & The Institution of Engineering and Technology 2011
h1 − h2 h2
(5)
where h1 and h2 are the efficiencies of inverter with proposed and conventional methods, respectively. Efficiency of inverter IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393 –399 doi: 10.1049/iet-pel.2010.0311
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Fig. 8 Harmonic spectrums a Inverter line voltage (Vab) b Load line voltage (after filter) c Load current (ia) with proposed reduced switching loss PWM technique
system can be defined as Table 3
h=
Pout Pin
(6)
It is observed that for load power factor angle of 308 and less, the improvement in efficiency with proposed method is not significant. EIF is reduced for load power factor angle more than 30o. Table 3 shows the effect of switching frequency on inverter efficiency with conventional and proposed method. Inverter efficiency has been improved by about 6% for a switching frequency of 5 kHz using the proposed method. It also indicates that EIF is more prominent at higher switching frequencies. This performance is comparable with that given by Kaku et al. [3] using SVPWM technique. IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393–399 doi: 10.1049/iet-pel.2010.0311
Efficiency of inverter
Switching frequency, kHz
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Efficiency in % Conventional method
Proposed method
79.0 78.1 74.2 70.7 68.1 64.2 61.7 59.4 57.1 55.4
79.5 79.0 75.3 71.7 69.4 66.2 64.8 62.6 62.0 61.3
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Experimental verification
A laboratory prototype of three-phase, diode clamped or neutral-point clamped inverter has been developed for experimentation. The experimental parameters are listed in Table 4. The dSPACE DS1104 has been used for real-time control of the inverter. Figs. 9a and b show the experimental results of phase voltage (Van) and line voltage (Vab) with conventional SPWM method and with proposed reduced switching loss PWM technique at switching frequency of 2 kHz. It clearly shows the effect of inserting ‘no switching’ zone within each half cycle of fundamental wave for reduction in switching losses. Fig. 10 shows the harmonic spectrums of inverter line voltage, Vab , with conventional SPWM technique and proposed reduced switching loss PWM technique. These results are in close confirmation with simulation results. Fig. 11 shows the load voltages and load currents with proposed reduced switching loss PWM technique. Harmonic spectrums of load voltage (Vab) and load current (ia) with the proposed reduced switching loss PWM technique are presented in Fig. 12. The measured THD are well within the specified limits of 5% imposed by IEEE 519-1992 standard. Table 4
Fig. 10 Harmonic spectrums of inverter line voltage (Vab) a Conventional SPWM technique b Proposed reduced switching loss PWM technique
Experimental parameters
DC link voltage DC link capacitor load resistance load inductance carrier frequency
100 V 2200 mF (each) 45 V 5.2 mH 2 kHz
Fig. 11 Load voltages and load currents (after filter) with proposed reduced switching loss PWM technique CH1, CH3, CH5: load line voltages Vab , Vbc , Vca (scale: 50 V/div) CH4, CH6, CH2: load currents ia , ib , ic (scale: 5 A/div)
Fig. 12 Harmonic spectrums a Load voltage (Vab) b Load current ia with proposed reduced switching loss PWM technique
Fig. 9 Experimental results of phase voltage (Van) and line voltage (Vab) (at switching frequency of 2 kHz) (x-axis: time – 10 ms/div; y-axis: top trace: 50 V/div; bottom trace: 100 V/div) a Conventional SPWM method b With reduced switching loss PWM strategy 398
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The efficiency of the inverter system is measured to observe the reduction in switching losses. An improvement of about 5% in efficiency for a switching frequency of 5 kHz is observed with the proposed technique over conventional SPWM technique. The performance of the inverter system is also observed in terms of EIF, which is defined in (5). Table 5 shows the effect of load power factor angle on EIF experimentally for different switching frequencies and compared with simulation results. It IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393 –399 doi: 10.1049/iet-pel.2010.0311
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EIF at different load power factor angles
Load power factor angle, deg
Efficiency improved factor, EIF, % 1 kHz
5 10 15 20 25 30 35 40 45 50 55 60
2 kHz
3 kHz
5 kHz
Sim
Exp
Sim
Exp
Sim
Exp
Sim
Exp
1.8 1.8 1.8 1.8 1.8 1.8 1.7 1.6 1.5 1.4 1.3 1.2
1.6 1.6 1.6 1.6 1.6 1.6 1.5 1.4 1.3 1.2 1.1 1.0
2.9 2.9 2.9 2.9 2.9 2.9 2.7 2.5 2.5 2.4 2.3 2.1
2.7 2.7 2.7 2.7 2.7 2.7 2.5 2.3 2.1 2.0 1.9 1.8
3.8 3.8 3.8 3.8 3.8 3.8 3.4 3.2 3.1 2.9 2.8 2.5
3.6 3.6 3.6 3.6 3.6 3.6 3.2 3.0 2.8 2.7 2.4 2.2
4.9 4.9 4.9 4.9 4.9 4.9 4.7 4.6 4.5 4.4 4.3 4.1
4.7 4.7 4.7 4.7 4.7 4.7 4.5 4.3 4.1 3.9 3.6 3.2
Sim – simulation; Exp – experimental
indicates that EIF is more prominent at higher switching frequencies. Approximately 4.6% increase in EIF is achieved at 5 kHz switching frequency as compared to 1.6% at 1 kHz. Switching losses are reduced and efficiency is increased by approximately 5% for the developed laboratory prototype with the proposed technique. Using the proposed method, every phase of the inverter can be switched off for 120 with 608 for positive half cycle and 608 for negative half cycle. It is observed that if the load power factor angle f ≤ 308, the ‘no-switching’ zone can be set in the centre of the peak value region of the load current so that the switching loss can be minimised. If load power factor angle f . 308, there is less influence on the reduction of switching losses.
6
Conclusion
A simple ‘reduced switching loss PWM’ technique is proposed using SPWM technique, based on stopping the switching pulses for some duration within each half cycle of voltage wave to further reduce the switching losses. It effectively controls the switching frequency by introducing the ‘no switching’ zone in each half cycle of fundamental voltage wave. The duration of ‘no switching’ zone is determined using PI regulator based on load voltage and load current. An improvement of about 5% in efficiency for a switching frequency of 5 kHz is observed with proposed technique over conventional SPWM technique based on EIF. Experimental and simulated results have been presented to validate the effectiveness of the proposed technique. THD contents in inverter output voltage and current are also found within 5% specified limit imposed by IEEE 519-1992
IET Power Electron., 2011, Vol. 4, Iss. 4, pp. 393–399 doi: 10.1049/iet-pel.2010.0311
standard both in simulation and experimentation. The obtained results are comparable with the space vector PWM-based switching loss reduction technique [5] without any complex calculations involved in redundant switching state estimation.
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References
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