SOLUTION BRIEF – PROGRAMMABLE LOGIC
PuPCI - PCI BUS Target Interface using low-cost ALTERA PLDs Solution Brief SB11
Vendor:
June 2003, version 1.3
Features:
PFEIFER Elektronik Krasna 69 468 21 Bratrikov Czech Republic Europe
[email protected]
Family: MAX3k, MAX7k
Especially optimized for the Altera® MAX3k device architecture Supports 32-bit 33MHz PCI Highly optimized User-configurable PCI configuration space Target-only solution Fully synchronous design Fully hardware tested Fitable into the lowest speed grade MAX3128A device Some designs support automatic 32-bit unique serial number and PCI slot number identification (see SB26 – PCI List program) ü This PCI design is copy-protected
ü ü ü ü ü ü ü ü ü
General Description: Target Application: PCI Local Bus, Buses, Interfaces, Low-cost, cost-sensitive, security solutions
This document treats with an especially developed and world−unique PCI solution using low-cost programmable logic devices. This PuPCI solution is fitable into low-cost small-package MAX3128ATC100-10 device. RSTn CLK IDSEL FRAMEn IRDYn
ALTERA, PCI Local Bus, MAX, MAX3128A
C/BEn[3..0]
AD[31..0]
PAR TRDYn STOPn DEVSELn PERRn SERRn INTAn
PuPCI target-only design
Keywords:
CONFIG. DATA
TAR_ADDRESS[31..0]
DATA_TO_PCI[31..0]
DATA_FROM_PCI[31..0]
TAR_VALID_BYTES[3..0]
TAR_ACCESS TAR_READ_WRITEn TAR_BUSY TAR_INT_REQ
Fig. 1 - PuPCI (Mega)function - principle
We offer: -
-
Very cost effective easy PCI Target solution using low-cost MAXs Full development of a customer’s PCI to X solution using MAX PLD, development samples, final JTAG file or serial bit stream file, full customer support PuPCI function for licensing, available in AHDL (or VHDL) format
Copyright © 2003 PFEIFER Elektronik, All Rights Reserved.
PuPCI
Revision 1.3
PCI function in PLD
Contents CONTENTS .........................................................................................................................1 LIST OF FIGURES .............................................................................................................1 LIST OF TABLES ...............................................................................................................1 FEATURES ..........................................................................................................................2 SUPPORTED PCI BUS COMMANDS...............................................................................3 PCI CONFIGURATION SPACE ........................................................................................4 SIMULATION .....................................................................................................................5 DEVICE UTILIZATION COMPARISON .........................................................................6 OPERATING CONDITIONS..............................................................................................6 SAMPLE PUPCI SOLUTIONS ..........................................................................................7 DOCUMENT REVISION HISTORY .................................................................................9
List of Figures Fig. 1 - PuPCI (Mega)function - principle ..............................................................................1 Fig. 2 - PuPCI in EPM3128ATC100-10 device (PCI to 8bit multiplexed bus+delay)..............2 Fig. 3 - PCI to 8bit multiplexed bus bridge .............................................................................5 Fig. 4 - Universal 32bit I/O card using PuPCI.........................................................................7 Fig. 5 - 8bit I/O card with multiplexed bus using PuPCI .........................................................8
List of tables Table 1 - PCI Bus Command Support Summary.....................................................................3 Table 2 - PCI Bus - Supported Configuration Registers ..........................................................4 Table 3 - Typical utilization results for the PuPCI Target Interface (Mega)function using ALTERA MAX3k PLDs ................................................................................................6 Table 4 - Recommended Operating Conditions.......................................................................6 Table 5 - Universal 32-bit I/O card registers ...........................................................................7 Table 6 - Document revision history.......................................................................................9
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 1 of 10
PuPCI
Revision 1.3
PCI function in PLD
Features This section describes the features of the PuPCI function. The PuPCI function is a parameterized function implementing a 32-bit PCI-2.2 target interface module that has been designed and optimized for ALTERA low density programmable logic devices. The PuPCI function is fully compliant with the functional and timing requirements of the PCI specif. v2.2 and has been successfully tested on many of PC motherboards and PC configurations. The PCI function is based on our own developed PuPCI core and supports the following features: - Supports 32-bit 33MHz PCI - User-configurable PCI configuration space - PCI Target only solution - Fully synchronous design - Fully hardware tested - Highly optimized - Fitable into the lowest speed grade MAX3128A device - Some designs support 32-bit unique serial number - Designed for PC-AT compatible computers, 5V/3.3V PCI - Supports Memory and I/O Space Thanks to the effectiveness of the developed PuPCI solution, MAX3128A devices can be used. 100 pin TQFP package offers low price and sufficient space for solution like a 8bit universal I/O card or 8bit multiplexed bus to PCI cards. Thanks to the PLD usage, no configuration device is needed. This one-package solution is cheap, easy and copy-protected. It is the direct competitor to the classical ASIC solution. Note: Fitability of any user/customer design is not guaranteed (EPM3128 device especially). Pin assignment can depend on the actual design very strongly. On the other hand, 100%-utilized EPM3128A PCI device was already successfully tested.
Fig. 2 - PuPCI in EPM3128ATC100-10 device (PCI to 8bit multiplexed bus+delay)
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 2 of 10
PuPCI
Revision 1.3
PCI function in PLD
Supported PCI Bus Commands The PuPCI function responds to standard configuration, I/O and memory read/write commands. See Table 1. Table 1 - PCI Bus Command Support Summary
C/BEn[3..0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 A B C D E F
PCI-2.2 Command
Supported
Interrupt acknowledge Special cycle I/O read I/O write Reserved Reserved Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual access cycle Memory read line Memory write and invalidate
No No Yes Yes No No Yes Yes No No Yes Yes No No No No
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 3 of 10
PuPCI
Revision 1.3
PCI function in PLD
PCI Configuration space Table 2 shows PCI configuration space contents and registers. All the user or PCI configurable are highlighted. Table 2 - PCI Bus - Supported Configuration Registers Address 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH … …
Byte 3
2
1
0
DeviceID VendorID Status register Command register Class Code Revision ID Header Type Latency Timer Cache Line Size BIST Base Address Register 0 Base Address Register 1 Base Address Register 2 Base Address Register3 Base Address Register 4 Base Address Register 5 CardBus CIS Pointer SubsystemID Subsystem VendorID Expansion ROM Base Address Register Capabilities Pointer Reserved Reserved Reserved Reserved Reserved Reserved Reserved Maximum Latency
Minimum Grant
Interrupt Pin
Interrupt Line
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Table 2 shows the PCI Bus configuration space, user configurable registers are highlighted.
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 4 of 10
PuPCI
Revision 1.3
PCI function in PLD
Simulation The most used solution based on the PuPCI function is PCI to 8bit-multiplexed bus with configuration and interrupt register. This solution can be fitted to low-cost MAX3128A device. Fig. 3 shows the simulation results using MAX+Plus II development environment (simulator). It is easy to see that: - Card base address is 0x8000h. - Low 8bits (0x79h) from the address from PCI are transferred to the multiplexed bus directly. The card occupies 256B of I/O space. - This example presents PCI read cycle: the device responds 0x12h back to the PCI. - The PuPCI based chip generates ALE, CSn, E and RD/WRn signals automatically. - PCI bus cycle is delayed to generate min.70ns (85ns) access signal width properly. This timing is selectable in steps of PCI clock width (30 ns).
Fig. 3 - PCI to 8bit multiplexed bus bridge
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 5 of 10
PuPCI
Revision 1.3
PCI function in PLD
Device utilization comparison Table 3 shows typical utilization of selected ALTERA MAX3k line devices using PuPCI function based designs. Table 3 - Typical utilization results for the PuPCI Target Interface (Mega)function using ALTERA MAX3k PLDs Function \ Device utilization
EPM3064A
EPM3128A
EPM3256A
PCI Target Kernel only
~100%
~ 50 %
~ 25%
PCI Target, 8-bit I/O
Project doesn’t fit.
~ 64 %
~ 31%
PCI to 8-bit MUXed bus bridge, PC 256B I/O space, full Interrupt with global enable, 2 user bits, non-burst version
Project doesn’t fit.
~ 81 %
~ 40 %
PCI to 8-bit MUXed bus bridge, PC 256B I/O space, full Interrupt with global enable, 8 user bits, register for programmable I/O access width, selective/fast access to the user register in the address area, non-burst version
Project doesn’t fit.
Project doesn’t fit.
~ 56 %
Full 32-bit I/O card, selectable port direction (8b+8b+16b), direct input and written data registers, 256B I/O or Memory space, full Interrupt with global enable, 8 user bits, programmable I/O access width, acknowledge/wait signal, selective/fast access to the user register in the address area, burst version
Project doesn’t fit.
Project doesn’t fit.
~ 89 %
Operating Conditions Table 4 shows recommended operating conditions of PCI designs based on the PuPCI function and fitted into EPM3128 and EPM3256 devices. These devices are selected as to be low-cost and usable PCI device solution. Table 4 - Recommended Operating Conditions Parameter
Device / Conditions
Min
Typ
Max
Unit
PCI CLK frequency
EPM3128ATC100-5
-
33
49*
MHz
PCI CLK frequency
EPM3128ATC100-7
-
33
46
MHz
PCI CLK frequency
EPM3128ATC100-10
-
33
37
MHz
PCI CLK frequency
EPM3256ATC144-7
-
33
46
MHz
PCI CLK frequency
EPM3256ATC144-10
-
33
35
MHz
*Note: Some designs with PuPCI can be modified to reach 66MHz PCI.
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 6 of 10
PuPCI
Revision 1.3
PCI function in PLD
Sample PuPCI solutions Fig. 4 shows a universal 32bit I/O card principle structure. The solution is based on PuPCI function and is suitable for EPM3256ATC144-7 devices. It includes PCI core, 32bit input data latch register, 32bit output register and 16bit mode register.
Input Latches
XCLKO
XCLKI
Connector
Byte Output Enable
Output Buffers
INT mode selector 16b MODE Register
32b Input Data Latches
32b Output Data Register
PCI I/O Logic, Latches and Buffers
Fig. 4 - Universal 32bit I/O card using PuPCI
Table 5 shows card’s registers, its relative addresses and functions in dependence on PCI access cycle type. Table 5 - Universal 32-bit I/O card registers Address Base +0 Base +4
Write Access Output Data No function
Read Access Written Output Data Input data
Base +8
Mode Register
Actual Mode Register content + XLCKI input actual state
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 7 of 10
PuPCI
Revision 1.3
PCI function in PLD
Fig. 5 shows a universal 8bit I/O multiplexed bus card principle structure. The solution is based on PuPCI function and is suitable for EPM3128ATC100-10 devices. This solution has selectable INTEL/MOTOROLA interface and can support programmable I/O access time (WR/RD/E pulse width 33 - ca 500 ns, constant or variable).
xINT
Connector
8b MODE Register
RDn WRn ALE CSn RESETn
CNTI
INT mode selector
Mode select
MODE
Input Latches & Output Buffers Input Latches
Counter
Aux.Logic, I/O registers, MUX
PCI I/O Logic, Latches and Buffers
Fig. 5 - 8bit I/O card with multiplexed bus using PuPCI
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 8 of 10
PuPCI
Revision 1.3
PCI function in PLD
Document revision history Table 6 - Document revision history REVISION
REVISION HISTORY
DATE (DD/MM/YYYY)
1.0 1.1 1.2 1.3
Original Issue PMinPCI added, EPM3256 only PuPCI in MAX3128 added PuPCI in MAX3128 info updated
19/12/2001 26/06/2002 10/11/2002 23/06/2003
Copyright © 2001,2002,2003 Petr PFEIFER, PFEIFER Elektronik. All Rights Reserved. PFEIFER Elektronik Krasna 69 468 21 Bratrikov Czech Republic, Europe All other product names are trademarks, registered trademarks, or service marks of their respective owners. Printed in the Czech Republic, EU
Copyright © 2001,2002,2003 PFEIFER Elektronik
Page 9 of 10
