rail-to-rail common-mode range input stage with ... - IEEE Xplore

IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 28, NO. 6, JUNE 1993

661

Constant-G, Rail-to-Rail Common-Mode Range Input Stage with Minimum CMRR Degradation J. Francisco Duque-Camllo, Member, IEEE, JosC M. Valverde, and Raquel PCrez-Aloe

AbstractAn this paper the inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated on the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as function of the input common-mode voltage, it provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in regard to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2-pm feature size are given.

"ss Fig. 1. Typical input stage for high-input-swing amplifiers.

I. INTRODUCTION

A

NALOG blocks must be designed to operate over a higher and higher percentage of the total supply voltage as a consequence of the continued scaling of CMOS VLSI technologies [ 11. One particular aspect of this trend consists of the design of CMOS amplifiers with capability to handle rail-to-rail input common-mode (CM) signals. Simple routine analysis demonstrates the severe limitations of differential pairs to deal with input CM signals in one of the supply directions. A common method of realizing CMOS amplifiers with wide-input common-mode range (CMR) consists of using complementary input differential pairs [ 2 ] . Because there is some problem on controlling the quiescent point, the dc and ac small-signal currents from both pairs are added in two shared loads. Fig. 1 illustrates the typical input stage used in amplifiers with extended CMR. Amplifiers with composite input pairs suffer from some undesirable shortcomings, which can be summarized by stating that their magnitudes show large deviations from their values at midsupplies when the input CM voltage sweeps from Vss to VDD[3], [4].These shifts are due to the different biasing operation conditions of the input pairs as function of the common-mode component Thus, from certain input C'M voltages near the rails, one of the input pairs is cut off, and the total transconductance (Gm) is almost halved in regard to its value for CM signals in the midrange between supplies. This change in transconductance does not allow the optimization of amplifier compensation. Moreover, the optimization of noise performance is also avoided since Manuscript received September 8, 1992; revised January 11, 1993. This work was supported by C.I.C.Y.T. (Spain) under Grant TIC-91.1059. The authors are with the Department of Electrhica e Ing. Electromechica, Universidad de Extremadura, 0607 1 Badajoz, Spain. IEEE Log Number 9208 1 16.

the thermal noise, which is inversely proportional to G,, increases when one of the amplifier differential pairs is OFF. Solutions to achieve an almost constant transconductance have been focused on designing the transistors input pairs operating in weak inversion overall range and controlling the bias current levels in a complementary way [5]-[8]. Since the transconductance of the MOS transistor in weak inversion, as well as its bipolar transistor counterpart, is proportional to the quiescent current, a nearly constant amplifier transconductance can be achieved. However, the more disappointing parameter in high-inputswing amplifiers is, indeed, the common-mode rejection ratio (CMRR). Regardless of the differential gain values, CMRR values in the range of 20-30 dB are very often provided by this kind of amplifier. This fact can become unacceptable in some critical noninverting amplifier applications. For example, if a generic amplifier in unity-gain follower configuration is considered, the steady-state error can be easily derived and expressed as

where A,., and Adm are the amplifier common-mode and differential-mode gains, respectively. Fig. 2 plots this error as function of the CMRR for an amplifier in unity-gain follower configuration with Ad,, = 66 dB. As can be seen, degradation on the rejection to input CM signals must be avoided as much as possible if an accurate signal processing is to be maintained. In amplifiers with rail-to-rail input CMR, the lowest CMRR figures arise just before the input commonmode voltage is able to completely cut off any of the bias current sources. More precisely, these low values show up in the input CM signal ranges where the output node of one

0018-9200/93$03.00 0 1993 IEEE

I

__I

1 -

662

12

lEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 6, JUNE 1993

error

(U)

I I

03

4t

I

\

I I I I

Fig. 3. Conceptual circuit schematic to illustrate the principle of operation. 0 16

20

6

t

26

30

I 36

40

46

60

66

80

86

CMRR (dB) Fig. 2. DC error in a unity-gain follower for different CMRR values.

through which the portion of current due to the channel length modulation flows. The bias current source I B provides a welldefined dc current value. In response to any input signal variation AK, it is assumed that the circuit forces a fraction CY of the current variation i to circulate through the portion of transistor M 3 without channel modulation. So, it can be easily deduced that this partial positive feedback loop causes the following effective output conductance seen from the drain node of M3:

of the bias sources becomes a low-impedance node. In these ranges, usually known as transition regions, the CMRR is inversely proportional to the offset variation (AVos) in regard to the input common-mode voltage counterpart (AX,=,). The amplifier offset voltage shift accounts for the difference in random offset between both differential input pairs. In that sense, a bipolar amplifier with constant G, has been proposed [ 5 ] . The circuit is biased by means of a simple crossover network, which activates only the input differential pair that where go3 is the output conductance of M 3 and it is clear operates properly for a given level of the input common-mode that CY is the gain of the feedback loop. As indicated in (2), voltage. However, such a circuit does not take advantage of the observe that if the feedback factor CY is equal to one, the output maximum transconductance value available, and shows low node of bias transistor M 3 becomes ac ground since no extra CMRR since the sole transition from one input pair to another current flows through its output conductance and, therefore, the is carried out in a very narrow CM input signal range. response i to any input signal is exclusively determined by the This paper introduces a bias current circuit that, incorporated transconductance (gml) of the driver transistor M 1 . Hence, with any rail-to-rail CMR amplifier input stage, provides a the circuit of Fig. 3 provides, simultaneously, a well-defined constant G, and minimum CMRR degradation. The principle dc current and ac response. of operation of the proposed circuit is described in Section To maintain the circuit of Fig. 3 stable, the amount of 11. Section I11 deals with general considerations for maximum positive feedback applied has to be limited. A simple analysis CMRR design in this kind of amplifier along with the operation of its equivalent small-signal circuit allows us to conclude that of the proposed input stage. Concretely, it is shown how the stability is ensured providing that the following condition the circuit, controlled by the amplifier input CM component, is fulfilled: accomplishes two positive feedback actions to cancel out the finite output conductance of two MOS transistors. Thus, (3) a gradual and complementary transition between amplifier differential input pairs is carried out, where its maximum slope is well-defined by the transconductances of other two Note that the above condition means that the circuit becomes transistors. As a consequence, the CMRR is maximized and unstable if the value of the positive feedback factor dominates the transconductance is kept almost constant provided that the over the local negative feedback effect associated with the drivers of the amplifier are biased in weak inversion. The finite output impedance of the current mirror M 2 , M 3 . The ac behavior of the circuit of Fig. 3 is mainly determined proposed structure along with the classical approach have been by the relative position of its dominant pole and zero, which fabricated in a CMOS 2-pm test chip. Experimental results are located at obtained from its measurement are given in Section IV. 11. PRINCIPLE OF OPERATION

In order to illustrate the principle of operation in which the proposed bias current control circuit is based, the conceptual circuit schematic of Fig. 3 will be considered first. In it, transistor M 3 (enclosed by a Gaussian surface) has been decomposed in the transistor itself, through which the current follows the ideal quadratic law, and the output resistance

where C D B 3 and C G S ~account for the drain-bulk and gate-source parasitic capacitances of transistors M 3 and M 1 , respectively.

663

DUQUE-CARRILLO er al.: CONSTANT-G, RAIL-TO-RAIL COMMON-MODE RANGE INPUT STAGE

111. PROPOSED BIAS CIRCUIT FOR RAIL-TO-RAIL INPUTSTAGES The CMRR and the Vas of an input stage are always inversely proportional to each other since they are originated from the same source: device mismatch. As pointed out in Section I, two offset transitions, which are carried out in narrow ranges of input CM voltages, can be observed in typical input stages with complementary differential pairs (Fig. l), as a consequence of their difference between random offsets. In these ranges of input CM signal, one of the biasing currents, or I B ~ decreases , from the nominal design value either IBN to zero. To improve the CMRR, the transition zone width should be maximized and therefore, the ratio AV,,/A~,,, minimized. An ideal and theoretical limit of the maximum V assuming width supply would an voltage, ideal be, constant-slope obviously, simulationsthe show rail-to-rail totalthat supply the transition maximum voltage. andThus, limit f5on CMRR improvement with regard to the classical biasing approach that can be achieved arises in the range of 24-28 dB for typical VOS, values of the transistor bias current sources (0.3-0.4 V). Transistors with higher ~ O S , values (wider transition regions) improve the CMRR in classical schemes, however, the range of input CM voltages with high rejection to CM signals and constant G, is even more reduced. Therefore, it can be said that currently there is a challenging task on the design of amplifiers with rail-to-rail input CMR and simultaneously, high CMRR and constant

_ _ -- - -- - - , ,

I

VDD

I

go4 I I

M4

I

"ss

- - - - - - - - -Fig. 4. Double partial positive feedback loop.

gmpii[;-alfil$$

fgd

gm2(v2-v.) g03

-a2 f i 2

- - -

Ip

2

Fig. 5. Simplified small-signal equivalent circuit of Fig. 4.

Fig- 5 Can be expressed as

Gm. In order to make clear the implementation of the above considerations to achieve high-input-swing amplifiers with high CMRR and constant G,, the circuit of Fig. 4 is now studied. Here, every transistor is assumed without channellength modulation effects except the transistors M3 and M4, which have been decomposed in the transistor itself and the output conductance. All the current mirrors of the circuit have been dimensioned to provide unity gain. The current subtractors ensure a complementary nature in the currents I1 and 4 since

Therefore, in response to any V; variation, the current variations AI1 and AI2 go in opposite directions. These changes are complemented by the p-MOS and n-MOS current subtractors, and injected through the portions of transistors M3 and M4 that follow the ideal quadratic law, respectively. A simplified small-signal equivalent circuit of this double positive feedback loop is shown in Fig. 5. Now, and in spite of the theoretical unity gain of the current mirrors pointed out above, it is assumed that fractions a1 and a 2 of currents AI1 and AI2 are injected back through the ideal portion of transistors M4 and M3, respectively. Values of feedback factors a1 and a2 different from one account for errors in the gain of current mirrors as a consequence of the unavoidable mismatches in their devices. For low-frequency signals, currents AI, and AI2 in the equivalent circuit of

+

+

where Do = (1 go3/gml)(l go4/gm2) - ala2 is the dc term of the determinant of the system and in it, the effect of every feedback action is clearly seen. If the driver transistors M1 and M2, which operate in strong inversion, are designed with aspect ratios to compensate their difference in carrier mobility, the dc current that flows through every transistor in the circuit of Fig. 4 is nearly IBwhen V , = 0, and gml % gm2 E gm as well. At this point, and assuming that a1 and a2 are very close to one, (6a) and (6b) reach their maximum value:

Note that under these circumstances the source nodes of M1 and M2 are ac ground since no extra current flows through go3 and go4. Concretely, the double feedback action carried out in the circuit cancels out the response component due to the effect of the finite output resistance of transistors M3 and M4, respectively, and therefore, the response is exclusively given by the well-controlled transconductance value of drivers M1 and M2. For # 0 the dc currents I1 and 1 2 are not equal; (7) is not fulfilled, however, the transconductances of M1 and M2 still control the response as indicated in (6). Assuming the internal pole of every current mirror at much higher frequencies, the dominant poles in the circuit of Fig. 4

664

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 6, JUNE 1993

are the roots of the following equation:

M1A M1B

. [(1+=)(1+=).-a1a2]

=O

(8)

where C3 and C4 represent the total parasitic capacitances at the drain nodes of transistors M 3 and M4, respectively. The ac behavior for low frequencies is determined by the relative position of these dominant poles respect to the zeros given in (4b). It should be realized that the dominant poles and zeros can be roughly canceled for a1 and a2 values close to one. In regard to the stability of the double positive feedback loop of Fig. 4, (8) indicates that the circuit will remain stable provided that the total positive feedback amount a l a 2 does not overcome the negative feedback originated by the finite output resistance of transistors M 3 and M4. That is, (OlQ2) m ax

= (1

+

E) + E). (1

1-,

%Ip

Fig. 6. Bias circuit for rail-to-rail CMR input stages for constant G,,, and minimum CMRR degradation.

(9)

In practice the maximum limit of the total amount of positive ) relaxed, since the local negative feedback ( Q ~ L Yis~ more feedback at the output of every current mirror transistor must be included in the right hand of (9). Hence, the structure of Fig. 4 provides, simultaneously, well-defined bias current levels ( I B ) for V , = 0, compleFig. 7. Chip microphotograph. mentary nature in currents Il and I2 for any V , # 0, and a well-controlled maximum slope (gml = gm2 = g, for node of transistors M6 and M5 must be tied to the commoncy1 = a2 = 1) of the sole transition, which as a consequence, can make a very gradual transition. These features can be source node of the n-channel ( M l n , M 2 n ) and p-channel advantageously exploited to control the bias current levels in ( M l p , M2p) input pairs, respectively. As discussed above, the any rail-to-rail common-mode range input stage if constant common-source transistor pairs MlA, M1B and M 2 A , M 2 B transconductance and minimum CMRR degradation want to are introduced so that the bias current circuit responds only to and be achieved. However, a last feature must be included in the the CM component of the input signals circuit of Fig. 4 to be useful for such a biasing purpose. It IV. EXPERIMENTAL RESULTS consists of implementing the necessary circuitry to ensure that the circuit just responds to the CM component (K,,,) of two A test chip has been designed and fabricated in a standard input signals. The detection of the CM component based on CMOS p-well process with 2-pm feature size. Fig. 7 shows the the common-source node of a simple differential pair is a microphotograph of the prototype. The chip contains several frequently used technique, yet this approach generates in its blocks. The rail-to-rail input stage of Fig. 1 along with the bias response a significant nonlinear term of the input differential- circuit of Fig. 6 and a classical biasing scheme made up of two mode component [9] and, therefore, it should be simple current sources have been separately included. Thus, avoided in applications such as the control of the CM in fully the parallel connected differential input pairs can be extemally differential amplifiers when low distortion in the processing biased by means of any of the other two blocks. In this way of V&, is required. Nonetheless, high-swing complementary the comparison between performances will be more realistic input pairs are usually implemented in amplifiers designed since important magnitudes in the context of this work, such for noninverting applications, and there the input differential- as the CMRR, rely on the device mismatches. In addition, a mode component can be neglected in regard to the common- simple OTA based on the composite input pair of Fig. 1 was mode counterpart. Thus, not only is common-mode detection also included on chip. Firstly, the dc currents I B N and I B P ,along with the current based on the common-source node of differential pairs suitable for these noninverting applications, but it could even be left IL through one of the shared loads, were measured when the out without any significant loss of performance. input CM swept from VSS to VDD.The chip was supplied Keeping in mind the above considerations, the circuit shown with f 2 . 5 V. The shared loads were implemented by two in Fig. 6, which has been derived from the structure of Fig. 4, passive and extemal 10- kR resistors. In Fig. 8(a), two current along with two parallel connected differential pairs (Fig. I), sources biased the parallel connected input differential pairs. values, one of the input pairs is cut off and is proposed as a rail-to-rail common-mode range input pair From certain with constant G, and high CMRR. In particular, the drain as a consequence, the dc current and total transconductance are

q-.

-

DUQUE-CARRILLO et al.: CONSTANT-C, RAIL-TO-RAIL COMMON-MODE RANGE INPUT STAGE

uA

665

uA

I

-2

-1

0

1

2

-2

1

1

0

2

Vi.cm

Vi,cm (a)

p. Fig. 8. DC currents I ~ . v . l ~ and

I

Ibn

IbD

(b)

IL as function of the input CM voltage: (a) classical scheme, and (b) proposed circuit.

mV divided by a factor of 2 when compared with its design value 10 for Vz,,, = 0. Fig. 8(b) plots the dc currents in the proposed input stage. Now, the complementarity between I B N and I B B ~ can keep an almost constant transconductance level over the entire CM input range. Unfortunately, the process used for chip fabrication did not have available any model for weak 6 inversion design, and for this reason every driver transistor was designed to operate in strong inversion. However, and just to show the proposed input stage capability to maintain a constant G, if those models were available, the deviation I 1 in the measured dc currents 1~ was calculated. The classical biasing approach showed a 54% maximum variation from its value at midrange (Fig. 8(a)), while the current deviation was 0’ kept lower than 4% with the proposed input stage. -2 -1 0 1 2 On the other hand, if all the local negative feedback effects Vi,cm existing in the current control circuit of Fig. 6 are evaluated and included in (9), it is found that, at least in the particular Fig. 9. Offset voltage of an arbitrary sample versus input CM component. case of the present design, the sum of all W / L transistor one offset transition when its bias currents are controlled current mirror mismatches in the loop should be higher than with the proposed circuit. The transistors M l A , M 1 B and +lo% to cause instability. In addition, it is a well-known MZA, M 2 B of Fig. 6 were set at one tenth the aspect ratios fact that the sensitivity of any structure to device mismatches of the input devices M l n , M2n and M l p , M2p of the circuit is greatly reduced when a high number of transistors are shown in Fig. 1, respectively. Thus, the maximum rate of offset involved in the circuit, since each individual deviation has change in the transition zone, which occurs at midsupplies, is a minor impact on the performance of the whole circuit and, proportional to 2gmlA = 2 g m 2 ~= 12 pA/V for I B = 20 therefore, random parameter deviations are averaged out. For pA according to (7). This soft and gradual transition reduces these reasons, every current mirror in the loop was designed the common-mode gain over 18 dB in regard to the classical with unity gain without obtaining any stability problem in a technique, since, as pointed out above, this gain is proportional package of six samples. However, more conservative designs to the offset variation. Obviously, W / L ratios of the transistors in this sense could be implemented, decreasing the total M l A , M l B and M 2 A , M 2 B must be chosen in order positive feedback amount. This can be done by designing the to minimize the maximum slope in the transition region current mirrors M12-M3 and M9-M4 in the circuit of Fig. for maximum CMRR improvement. However, excessively 6 with certain gain B slightly lower than one. The value of reduced aspect ratios in these transistors go prematurely gain B should be chosen in such a way that, even under the out to either transistor M 3 or M4 from saturation, in worst case of severe mismatching, the amount B2alaz fulfills such a way that their output conductance can be dominant the stability criteria. However, the maximum slope of the tran- over the transconductance of M l A , M 1 B or MZA, MZB, sition deviates progressively more from the transconductance respectively. As a consequence, a higher maximum slope value of transistors M 1 A and M 2 A when B is reduced. results and, besides, does not appear at midsupplies. Amplifiers based on complementary input pairs, as any The offset voltage transitions of an arbitrary sample as function of the input CM component are plotted in Fig. crossover network, suffer some degree of crossover distortion. 9. As observed, the high-swing input stage shows just To evaluate this effect the total harmonic distortion (THD) has

88 t

I

T

I

I

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 6. JUNE 1993

666

,.,*I

Feature 1 allows either a constant G , (if driver transistors operate in weak inversion) or decreases the G , variations (if driver transistors operate in strong inversion). The second feature achieves a minimum CMRR degradation and, therefore, maximum accuracy in the processing of the input signal.

/ I

0.1

0.08

REFERENCES

0.06 0.04 0.02 0’

0

I

0.5

1

1.5

2

I

I

2.5

3

3.5

I

1

4

4.5

6

Vin,p-p ( V I Fig. 10. THD for different input amplitudes at 10 kHz. (1 V/div)

Y. Tsividis, Operation and Modeling of MOS Transistor. New York: McGraw-Hill, 1987. T. S. Fiez, C. H. Yang, J. J. Yang, C. Yu, and D. T. Allstot, “A family of high-swing CMOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. 24, pp. 1683-1687, Dec. 1989. J. A. Fisher and R. Koch, “A highly linear CMOS buffer amplifier,” IEEE J. Solid-state Circuits, vol. 22, pp. 330-334, June 1987. M. Steyaert and W. Sansen, “A high-dynamic range CMOS op amp with low distortion output structure,” IEEE J . Solid-state Circuits, vol. SC-22, pp. 12W1207, Dec. 1987. J. H. Huijsing and D. Linebarger, “Low-voltage operational amplifier with rail-to-rail input and output ranges,” IEEE J . Solid-State Circuits, vol. SC-20, pp. 1144-1150, Dec. 1985. J. F. Duque-Carrillo, R. PCrez-Aloe, and A. Morillo, “Push-pull current circuit for biasing CMOS amplifiers with rail-to-rail input commonmode range,” IEE Electron. Lett., vol. 27, pp. 2122-2125, Nov. 1991. M. Pardoen and M. Degrauwe, “A rail-to-rail input/output CMOS power amplifier,” in Proc. IEEE Custom Integrated Circuits Conf (San Diego, CA), May 1989, paper 25.5. J. F. Duque-Camllo, R. PCrez-Aloe, J. M. Valverde, and A. Morillo, “A family of biasing circuits for high input swing CMOS operational amplifiers,” in Proc. IEEE Int. Symp. Circt. Syst. (San Diego, CA), May 1992, pp. 3021-3024. J. F. Duque-Canillo, “On the control of the common-mode component in CMOS continuous-time fully-differential signal processing,” Analog Integrated Circuits and Signal Processing, to be. published, Sept. 1993.

J. Francisco Duque-Carrillo (M’86) received the 0

5

10

15

20

25

30

us Fig. 11. Transient amplifier response in unity feedback configuration to a 2.25-V step and C L = 200 p F ( I ) classical scheme, and (2) proposed circuit.

been measured in the unity-gain follower configuration. Fig. 10 plots the THD for different amplitudes of a 10-kHz input signal. As expected, higher distortion levels are introduced by the new input stage in regard to the classical one for small input signal amplitudes, while the opposite situation arises for input signals with higher amplitudes. Finally, Fig. 11 illustrates the slew-rate limitation of the complete amplifier. A 2.25-V step was applied to the amplifier in unity feedback configuration with a capacitive load of 200 pF. Different slew rates can be observed in the transient response when the amplifier is biased with the classical approach. However, a constant and maximum slew is maintained over the entire range when the proposed circuit controls the bias currents.

M.Sc. degree in electronic physics from the University of Seville, Seville, Spain, and the Doctor in physics degree from the University of Extremadura, Badajoz, Spain, in 1979 and 1984, respectively. From 1986 to 1987 he obtained a NATO Fellowship which allowed him to work as a Visiting Scholar at the Electrical Engineering Department of Texas A&M University, College Station. In 1988 he was working for AT&T Microelectronic in Madrid, Spain, and Allentown, PA. Currently he is with the University of Extremadura, Badajoz, Spain, as an Associate Professor. His research interests focus on the area of analog integrated circuit design.

Jose M. Valverde was born in Badajoz, Spain. He finished his studies in electronics at the University of Extremadura, Badajoz, in 1987. Since 1989 he has held a Research Assistant position in the Department of Electronics at the same University, where he currently is a Ph.D. candidate. His research interest focus on instrumentation and IC design for biomedical applications.

V. CONCLUSIONS An input stage suitable to be incorporated on the design of any amplifier topology with rail-to-rail input CMR has been presented. As demonstrated by measured results, the principle of operation in which it is based provides 1. a well-defined and complementary dc current levels in the differential pairs and for any vi,,, value, and 2. a well-controlled and gradual transition between pairs when V,,,, goes over the entire input range.

Raquel Perez-Aloe received the B.S. and M.S. degrees in physics from the University of Extremadura, Badajoz, Spain, in 1986 and 1989, respectively. She is currently working towards the Ph.D. degree in the field of programmable hearingaid devices.