Reliability Characterization and Modeling Solution to ... - IEEE Xplore

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

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Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses Laurent Negre, Student Member, IEEE, David Roy, Florian Cacho, Patrick Scheer, Sebastien Jan, Samuel Boret, Daniel Gloria, and Gérard Ghibaudo, Senior Member, IEEE

Abstract—In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices. Index Terms—Aging, compact model, hot carrier, load-pull, model, MOSFET, PSP, radio frequency, reliability.

I. INTRODUCTION

S

INCE several years, radio frequency (RF) and analogmixed-signal (AMS) CMOS technologies serve the enormous momentum of the wireless market. The increasing demand requires technologies meeting the highest standards of performance and reliability. As depicted in Fig. 1, a benchmark of RF CMOS cut-off frequency trends across technology generation shows that channel length downscaling enable aggressive performances. In contrast to these ever-increasing performances, reliability is becoming a growing up concern. RF products are generally targeting mission profiles where voltage swings are far beyond digital perimeter. As an example Power Amplifiers are subjected to high input power and in this way to voltage and current exceeding the nominal value. Today’s reliability models have been developed at device level to be more predictive at product level. These reliability models are generally based on accelerated tests done under constant bias (DC) stress conditions and without experiments covering the real mission profile conditions. In this context new concerns will arise on the validity of the models, the aging of key parameters, the interpretation of peak value over the whole signal. Thus, a key challenge is to extend current reliability models allowing quantification and prediction of both DC and RF performances evolution under DC and RF/AMS stress conditions. Manuscript received September 30, 2011; revised November 18, 2011; accepted December 18, 2011. Date of publication February 17, 2012; date of current version April 25, 2012. This paper was approved by Guest Editor Georg Boeck. L. Negre, D. Roy, F. Cacho, P. Scheer, S. Jan, S. Boret, and D. Gloria are with STMicroelectronics, Technology Platform Sustaining/Electrical Characterization and Reliability, F-38926 Crolles, France (e-mail: [email protected]). G. Ghibaudo is with the IMEP-LAHC, 38016 Grenoble Cedex 1, France. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2012.2185549

Fig. 1. Benchmark of NMOS cut-off frequency ation.

across technology gener-

Over the last twenty years, several works have considered the extension of the reliability models in AC and RF/AMS cases. The study in [1] revealed a correlation between the RF figures of Merits ( and ) degradation and DC performance degradation. An interesting suggestion of this work was to study the physical degradation of the small signal model parameters in order to predict the RF performance degradation from the DC performance degradation. The study in [2] modeled RF performances degradation under AC stress conditions. However, this study was limited to empirical adjustments of model parameters to represent the stressed device behavior. Regarding RF stress conditions [3]–[5], the studies were restricted to the application of RF power considering only the frequency domain and in this way couldn’t use a quasi-static approach based on DC reliability models. To effectively investigate the device aging in the AC/RF range, a specific methodology will be developed and discussed in this paper. In Section II, a review of reliability phenomena and associated DC model will be done. Then, the aging formalism will be detailed in Section II-C to enable the extension of the reliability models in the AC and RF range. In Section III, the complete experimental and analytical methodology for such an extension will be presented. Based on this methodology, modeling of DC and RF performances under DC, AC and RF stress conditions will be performed on 40-nm technology node in Section IV and V.

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II. HOT CARRIERS RELIABILITY CONCERN The front-end physical phenomena mostly responsible for the transistor degradation are Hot Carrier (HC), Bias Temperature Instability (BTI) and Time Dependent Dielectric Breakdown (TDDB). However, with the MOS channel length downscaling the HC is becoming a first order concern for RF/AMS applications. A. Hot-Carrier Phenomenon The HC phenomenon appears with the combination of gate voltage and drain voltage applied to the transistor. The so-called hot carriers refer to carriers that gain high kinetic energy through regions of high electric field. Thus, under saturation conditions, the majority of the carriers transit in the pinch-off region by ballistic transport and experience no scattering events. Under the influence of the lateral field effect, a fraction of those hot carriers interacts with the interfacial layer enabling a transfer of energy. Several mechanisms can explain such interactions and are listed in [6]; an important one is the impact ionization (II). A few carriers generated via impact ionization are redirected and injected in the gate oxide. A direct measurement of these carriers is done through the bulk current which is proportional to the hole-electron pairs generated via II. Carriers injected in the gate oxide can either contribute to the gate leakage current or generate defects by Si-H bond dissociation in a region closed to the gate/oxide interfacial layer. Several types of bonds excitations can occur depending on the energy (voltage) and the flow (current) of carriers. Recent work [7] highlights three main bonds excitations. • Single Vibrational Excitation (SVE) is related to higher energetic carrier that has enough energy to break Si-H bond. • Electron Electron Scattering (EES) is due to energy exchange between two carriers. One carrier promotes the other into higher energy and allows Si-H breaking. • Multiple Vibrational Excitation (MVE) is due to a series of low energetic carriers that accumulate enough energy to break Si-H bond. In addition to the HC phenomenon described above, another important configuration has to be introduced i.e. the nonconducting HC [8]. This configuration appears when there’s no channel . The high energy of the minority carrier transport also contributes to the degradation.

Fig. 2. Representation of the lifetime for the 40 nm technology, defined as and the time to reach a fixed saturated current drift, as function of revealing the three HC modes.

EES, MVE) a general expression of range is given by [7], [9]

in the whole

(2)

, and are constant associated to where each excitation type. and respectively refer to the bulk and drain current. Physical descriptions of the other constants are detailed in [7]. As shown in Fig. 2, this multimode HC model clearly consider the existence of three independent modes. However, the nonconducting HC phenomenon is not accounted for yet. C. From Static (DC) to Radio Frequency (RF)

B. Hot-Carrier Physical Model Under HC stress, the amount of degradation undergones to the device follows a power law dependence of the stress time and has been empirically verified in [6] (1) represents the degradation of a parameters e.g. linear or saturated current, threshold voltage, maximum of transconductance. The parameter depends on many parameters such as the device architecture, the device geometry and the bias conditions. Based on the three excitations described before (SVE,

The HC model has historically been developed for DC conditions. However, in RF/AMS applications, the model should be able to take into account time-varying voltage and current profiles. To account for these conditions, the HC model built from DC conditions should be used through the quasi-static approximation i.e. the possibility to assume the time-varying conditions as a succession of DC conditions. Considering the three modes HC model for a drift of the linear drain current under time-varying conditions, (1) becomes (3)

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Fig. 3. Experimental setup used to perform DC and RF signal stresses. The stress can be interrupted periodically to characterize DC and RF parameters.

with

(4) Equation (3) can be differentiated at both sides as done below (5) This differentiation allows the evaluation of the instantaneous rate of additional degradation as a function of the cumulated degradation (6) This result can be rewritten to obtain (7)

analysis of the transistor’s aging. That’s why it will be mandatory in this study to built and validate RF aging model using time varying voltage and current. However, it is important to note that this model is based on quasi-static approximation. In this context, one can imagine that a frequency discontinuity exists so that the non quasi-static model would be no longer applicable for reliability study. Indeed, the RF stress could induced a non equilibrium leading to a dissociation between the current’s flow and the carriers energy. As described before, degradation mechanisms for DC case are essentially based on a coupling of current and energy. In that case a discontinuity of the model could appear for higher frequency. As mentioned in [12], this frequency limitation can be evaluate through the pulsation (9) where is the mobility and the substrate factor. Thus, it is generally assumed that a frequency signal over introduce non-quasistatic effects. The carrier’s delay time become equal to the signal period and the MOS transistor is no more governed by electrostatic equations. III. RF RELIABILITY METHODOLOGY A. Experimental Procedure

Since the time power law exponent used is valid for all stress conditions and provided that the quasi-static approximation holds, Equation (7) leads to the total degradation drift which is obtained thanks to the integration of the instantaneous degradation rate linked to the corresponding instantaneous voltage as

(8)

This result introduces the so-called Age function already reported in the literature [10], [11]. This age formalism associated to the three modes HC model clearly highlights that RF reliability needs to be performed by using time domain analysis rather than frequency domain analysis. Indeed, frequency domain analysis is limited to power aspect, so that a major part of the information is lost and does not allow for a quantitative

As presented in Fig. 3, a passive load pull setup is used in order to perform DC or RF stress which is periodically interrupted for DC and RF measurements. Concerning the stress, the parametric analyzer and the synthesizer are used to apply DC and RF stress component on the Device Under Test (DUT) respectively. For the measurements, the parametric analyzer and the vector network analyzer (VNA) are used to monitor DC parameters and scattering (S) parameters from 1GHz to 50GHz respectively. The power meter is used to monitor the input power level delivered by the synthesizer and the impedance tuners are used to control the impedances presented to the DUT. The spectrum analyzer is used to monitor the output power level and also to take into account signal distortion induced by harmonics generation. The use of switches allows to automatically calibrate the bench, extract and apply the RF signal, and also measure S-parameters of the DUT. By this way, setup configurations between different calibration steps and measurements are highly repeatable and the measurement accuracy is improved.

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The following methodology is used to extract the large signal waveform applied at a frequency to the device level. 1) A list of tuners position is chosen to cover a broad range of impedances at in the Smith chart. 2) Off wafer access characterization: two 1-port calibrations are done using Short-Open-Load method in order to calibrate the VNA at coaxial level i.e. switch 1 and 4. A full 2-port calibration is done at probe level, so that S-parameters of the input/output access can be extracted by combining measurements of three on-wafer standards i.e. short, open and load. 3) Optimum position to maximize the power gain at is determined by large signal measurements. 4) Large signal measurements (i.e. vs ) are done at fundamental fstress and harmonics frequencies. 5) S-parameters measurements of the de-embedded standards and of the device are done to analytically extract the input impedance at device level as a function of frequency. The impedance is extracted using the two port network formula ((10)) from the input and output reflection coefficient. Then, using at the stress frequency, input and output power applied at the device plane are extracted (10) 6) As the spectrum does not provide information about the phase of the output signal, Harmonic Balance simulation using ADS software is performed taking into account the entire environment induced by the load pull setup. The DUT is simulated using a PSP compact model aligned on DC and RF measurements. The application of this procedure allows an accurate extraction of the signal waveform. Then, the following methodology is performed to apply the RF stress and also to accurately monitor DC and S-parameters. 1) At probe level, a full 2-port short-open-load-thru calibration is used and on wafer de-embedding is done using open and short structure to put the reference planes at the edges of the device [13]. 2) A DC bias is applied to stress the DUT while a RF signal can be applied on the gate or the drain. The stress is periodically interrupted for the DC and S-parameters measurements at different bias conditions. A list of key bias conditions is provided in [14]. Furthermore, S-parameters of the device at the DC stress bias are measured to monitor the DUT input impedance vs. the stress time in order to match the stress signal waveform in real time.

ment, Y parameters are the bridge between measured S-parameters and the SSEC. They are converted from S-parameters measured at different bias conditions following [15]. As described in [16], the extraction is divided into two parts. First, the drain and source parasitic resistances are extracted and then all the other SSEC elements are evaluated. Except for the parasitic resistance that are considered bias independent, the lumped elements have to be extracted at all the bias conditions and at low frequency to avoid substrate coupling effect [17]. Concerning the parasitic series resistances, several extraction methods have been presented in the literature [18]. However, as revealed in [18] these methods are very sensitive to the noise introduced by S-parameters measurements leading to uncertainties. As the essential value for reliability analysis is the relative variation, an alternative solution is to fix an arbitrary value for drain and source parasitic resistances so that it will be possible to empirically evaluate a potential drift of those resistances induced by a stress condition. This de-embedding is done using the admittance matrix that represents the part of the SSEC included in the box of the Fig. 5 (11) where parameters are converted from measured parameters of the DUT [13]. The parameters of the admittance matrix are given by (12) (13) (14)

(15) and . After some mathematical transformations, each lumped elements can be obtained from the following expressions:

with

(16) (17) (18) (19) (20)

B. Small Signal Extraction Procedure A direct analysis of S-parameters drift would not give sufficient physical information on the MOSFET aging. Thus, physical interpretation of S-parameters drift is feasible through the extraction of small signal equivalent circuit (SSEC). The SSEC of a common source MOSFET presented in Fig. 5 is composed of physically-based lumped elements. All capacitances represent the sum of the intrinsic (channel) and extrinsic (fringing and overlap) capacitances. To extract each lumped ele-

The diagram of Fig. 4 illustrates the extraction methodology developed to address reliability in the RF domain from characterization to analyses. IV. MODELING

OF

DC PARAMETERS AGING INDUCED HC STRESSES

BY

A progressive approach will be adopted to validate HC models on 40-nm nMOSFET starting from AC to RF stress.

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Fig. 4. Diagram of the complete methodology to address reliability in the RF domain.

TABLE I LIST OF AC STRESS WITH THE MINIMUM AND MAXIMUM PEAK VOLTAGE APPLIED ON THE DRAIN (VDS) AND THE GATE (VGS)

Fig. 5. Conventional small signal equivalent circuit of a MOSFET in common source configuration.

Fig. 7. Waveform and instantaneous rate are represented for each AC stress referenced in Table I. Fig. 6. Experimental degradation of the linear current (symbol) as a function of stress time for different DC stress conditions distributed in the three HC modes and confronted to the HC model (lines). An extrapolation of the experimental data and the model is done at nominal bias condition showing a single power law trend.

tracted parameters will be used in the following to model AC and RF stress condition. A. AC Stress

As explained in Section II-C, DC aging model will be used via quasi-static approximation to predict aging induced by time-varying stresses. The HC DC model detailed in Section II is fitted with measurements originating from devices stressed at DC conditions covering a broad range. The model that will be used in this study is presented in Fig. 6 and confronted to experimental DC data set. Likewise, an extrapolation of the data set and the model at the nominal biasing value is presented. This extrapolation forms a single power trend highlighting the accuracy of the aging model. It is also important to note that each extracted parameters is linked to a physical description as reported in [7] and these ex-

In order to investigate the transition between DC and RF stresses, experiments have been carried out to validate HC model for pulsed (AC) stress. Two opposite AC stress are applied on the gate and the drain through a pulse generator. The waveform has a rising and falling time of 5 . The pulse duration is 12 . As listed in Table I, three stress conditions have been selected following a specific distribution of the three HC modes. Using the DC model extracted from DC stresses and (6), the instantaneous rate of each HC mode can be evaluated over one period for each AC stress. The measured waveforms and associated instantaneous rate are presented in Fig. 7.

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Fig. 8. Experimental degradation of the linear current (symbol) as a function of stress time for different AC stress conditions (Table I) confronted to the HC model (lines).

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

Fig. 9. The waveform and instantaneous rate evaluated for an RF stress power dBm at GHz on the drain with a static bias of V of V. and

The application of the quasi-static approximation allows the integration of the instantaneous rate over the whole stress time so that the drift of the linear current has been predicted in Fig. 8 and is in agreement with the experimental data. B. RF Stress Now that HC model has been validated for AC stress, the methodology presented in Section III will be applied in the RF range. For the application of RF stress, nMOSFET have been used with gate length m, total gate width m, number of fingers . The device has a common source configuration and is embedded in a Ground-Signal-Ground RF test structure. Each RF stress condition has been reproduced at least on three devices and show consistent behavior with the results presented in the following. The first stage involves a control and extraction of the signal integrity. As illustrated in Fig. 10, RF power stress of dBm at GHz has been applied on the drain with a static bias at V and V. This stress condition has been selected to avoid amplification phenomenon and to induce HC only in mode 3. The DUT acts as a resistance and in this case tuners are positioned in 50 configuration. As presented in Fig. 9, the stress waveform has been extracted showing a peak value of 1.8 V. The evaluation of the instantaneous aging rate clearly highlights the impact of the mode 3 and allows the modeling of the linear current drift. The confrontation of experimental data and the HC model is presented in Fig. 10. The step ahead is now to apply an RF stress on the gate of the transistor. Two cases have been studied with a static bias at V. Two RF powers of at GHz and GHz have been provided by the RF synthetizer. The power has been selected under class A condition so that the gate voltage is always above the threshold voltage and the drain voltage is always positive over the stress time. Thus, the waveforms and respective instantaneous rates are presented in Fig. 11. Both stresses conditions induced high energetic carriers in the channel and are consistent with the HC mode 1. This leads naturally to the modeling of the linear drain current drift

Fig. 10. Experimental degradation of the linear current (symbol) as a function of stress time confronted to the HC model (lines). The stress power of dBm at GHz is applied on the drain with a static bias of V V. and

Fig. 11. Waveform and instantaneous rate evaluated for an RF stress power of dBm at GHz and GHz on the gate with a static bias of V.

that is compared to experimental data in Fig. 12. This study shows the relevance of the prediction of the HC model for frequency up to 10 GHz.

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Fig. 12. Experimental degradation of the linear current (symbol) as a function of stress time confronted to the HC model (lines) for 2 RF stress conditions. The dBm at GHz and GHz are applied on the stress power of V. gate with a static bias of

Fig. 14. Experimental degradation of the linear current (symbol) as a function of stress time confronted to the HC model (lines) for an RF stress conditions in class AB condition.

Fig. 13. Waveform and instantaneous rate evaluated for an RF stress power of dBm at GHz on the gate with a static bias of V V. and

Nevertheless, the HC model presented here has its limitation. Indeed, when an RF stress is applied with sub-threshold gate voltage, the model underestimates the transistor degradation. As an example of this disruptive modeling, an RF power of dBm at GHz with a static point at V and V is applied on a matched transistor i.e. the matching is performed as defined in the methodology in Section III. The extracted waveforms are presented in Fig. 13. The drain waveform is subjected to harmonics distortions because a high power has been applied inducing non-linearities in order to obtain sufficient performances degradation on the transistor. Under this stress condition, the HC model underestimates the DC performances such as the linear current drift as presented in Fig. 14. This error can be explained by the RF stress condition which induces a gate voltage under the threshold voltage up to 36% of the stress time. As already defined in Section II, this condition introduces nonconducting HC phenomenon and impact the degradation. Unfortunately, this phenomenon is not included in the HC model. Another interesting point is linked to the overlap of HC modes leading to a double time dependence of the linear

Fig. 15. Extracted (marks) and simulated (lines) RF parameters before (black) and after (red) 1000 s of RF stress.

current drift. The double time dependence can be observed at on Fig. 14. More details are given in [19], these time dependencies can be justified by the interaction and defects location between the mode 1 and non-conducting HC. V. INTEGRATION OF RF PARAMETERS AGING AT COMPACT MODELING LEVEL Regarding the analysis of the degradation of SSEC elements induced by HC stress, we have already revealed in [20] that the SSEC degradation focuses primarily on , , . Furthermore, the study done in [14] has shown that the HC mode 3 is the most critical stress regarding RF performances aging. In this way, the RF stress presented in Fig. 9 will be the most significant one in the SSEC reliability modeling. The key elements of the SSEC impacted by the RF HC stress (i.e. , , ) are shown before and after of the RF stress application in Fig. 15. The degradation of those lumped elements have already been physically explained in [20], [21] by the threshold voltage , the mobility , the drain series resistance and the drain overlap flat-band voltage drift .

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Fig. 16. Measured (marks) and simulated (lines) S-parameters before (black) V and V. and after (red) RF stress at

The degradation of the and can mainly be explained by the drift of the threshold voltage and the effective mobility . By this way, the understanding of the drift of the explains the drift of the cut-off frequency . Indeed, Park et al. have shown in [1] a direct correlation between the degradation of and the degradation of . The extraction of the at V and variable is illustrated in Fig. 15. Under this condition, two dominant parts can be considered: At low , the extrinsic part is dominant including fringing (spacer localization) and overlap (LDD localization) capacitances whereas at higher the oxide capacitance tends to be dominant. One can observe the critical decrease of this extrinsic part that has been explained by the shift of the local flat band voltage in the n+ poly/n- LDD overlap region. In addition the drain parasitic resistance is degraded. The increase of is revealed through the decrease of the at high (Fig. 15) and also through the drift of the at V and V (Fig. 16). Based on these physical explanations and the flow detailed in [22], the time evolution of both DC and RF macroscopic parameters has been implemented in PSP with a correction of the compact model parameters. Thus, parameters responsible for carrier mobility, threshold voltage, velocity saturation, and channel length modulation have been adjusted and an external drain resistance has been included to represent the behavior of the stressed device. Nevertheless, as the drift of the flat-band voltage in overlap regions is not accessible in PSP model due to analytical approximations, this effect has been taken into account through global parameters attributed to parasitic capacitances. They have been used to empirically represent the degradation of the overlap gate to drain capacitance. The PSP simulation of both fresh and stressed S parameters and SSEC elements identified above are presented in Figs. 15 to 17. A good agreement is obtained between the simulation and experimental data. VI. CONCLUSION In this paper, a complete solution for RF reliability assessment has been addressed by the development of an accurate characterization setup and methodology.

Fig. 17. Measured (marks) and simulated (lines) S-parameters ( V) before (black) and after (red) RF stress. and

V

A particular attention has been paid to the study of aging induced by Hot Carriers (HC) stress under AC and RF range. After the development of a robust HC multimode model, the DC performances under those stress conditions have been analyzed and modeled. The study of RF stress under class AB condition highlights an issue on the modeling of nonconducting HC phenomenon. The degradation of RF performances has also been physically explained thanks to DC parameters i.e. , , , , . To predict the RF parameters degradation under RF stress an aging model has been implemented in PSP compact model which consider the carrier mobility, the threshold voltage, velocity saturation, the channel length modulation, the extrinsic capacitance and the drain resistance evolution. An integration of the RF behavior subjected to HC phenomenon in PSP is mandatory for a bottom-top approach. In fact, this will allow the consideration of complex circuits thanks to Design-in-Reliability simulations. REFERENCES [1] J.-T. Park, B.-J. Lee, D.-W. Kim, C.-G. Yu, and H.-K. Yu, “RF performance degradation in nMOS transistors due to hot carrier effects,” IEEE Trans. Electron Dev., vol. 47, no. 5, pp. 1068–1072, 2000. [2] C. Yu and J. S. Yuan, “MOS RF reliability subject to dynamic voltage stress-modeling and analysis,” IEEE Trans. Electron Dev., vol. 52, no. 8, pp. 1751–1758, 2005. [3] G. T. Sasse, F. G. Kuper, and J. Schmitz, “MOSFET degradation under RF stress,” IEEE Trans. Electron Dev., vol. 55, no. 11, pp. 3167–3174, 2008. [4] D. Stephens, T. Vanhoucke, and J. Donkers, “RF reliability of short channel NMOS devices,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Piscataway, NY, 2009, pp. 343–346. [5] C.-H. Liu, R.-L. Wang, Y.-K. Su, C.-H. Tu, and Y.-Z. Juang, “DC and RF degradation induced by high RF power stresses in 0.18- m nMOSFETs,” IEEE Trans. Device Mater. Reliab., vol. 10, no. 3, pp. 317–323, 2010. [6] E. Takeda, N. Suzuki, and T. Hagiwara, “Device performance degradation to hot-carrier injection at energies below the Si-SiO2 energy barrier,” in Proc. IEEE Int. Electron Dev. Meeting, 1983, vol. 29, pp. 396–399. [7] C. Guerin, V. Huard, and A. Bravaix, “General framework about defect creation at the Si/SiO2 interface,” J. Appl. Phys., vol. 105, no. 11, pp. 114 513–1 145 112, 2009.

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[8] A. Bravaix, C. Guerin, D. Goguenheim, V. Huard, D. Roy, C. Besset, S. Renard, Y. M. Randriamihaja, and E. Vincent, “Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40 nm CMOS node,” in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 55–64. [9] I. I. I. Rauch, S. E. , and G. La Rosa, “The energy-driven paradigm of NMOSFET hot-carrier effects,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 4, pp. 701–705, 2005. [10] P. M. Lee, M. M. Kuo, K. Seki, P. K. Lo, and C. Hu, “Circuit aging simulator (CAS),” in Proc. IEEE Int. Electron Devices Meeting, 1988, pp. 134–137. [11] G. T. Sasse and J. Bisschop, “The hot carrier degradation rate under AC stress,” in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 830–834. [12] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, Inc., 1999. [13] M. Koolen, J. A. M. Geelen, and M. Versleijen, “An improved de-embedding technique for on-wafer high-frequency characterization,” in Proc. IEEE Bipolar Circuits Technol. Meeting, 1991, pp. 188–191. [14] L. Negre, D. Roy, P. Scheer, D. Gloria, and G. Ghibaudo, “An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level,” in Proc. IEEE Int. Integr. Reliab. Workshop, 2011, pp. 73–76. [15] D. A. Frickey, “Conversions between S, Z, Y, H, ABCD, and T parameters which are valid for complex source and load impedances,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 2, pp. 205–211, Feb. 1994. [16] D. Lovelace, J. Costa, and N. Camilleri, “Extracting small-signal model parameters of silicon MOSFET transistors,” in Proc. IEEE MTT-S Int. Microw. Symp., 1994, pp. 865–868. [17] Y. Cheng, M. Schroter, C. Enz, M. Matloubian, and D. Pehlke, “RF modeling issues of deep-submicron MOSFETs for circuit design,” in Proc. IEEE Solid-State Integr. Circuit Technol., 1998, pp. 416–419. [18] J. C. Tinoco and J.-P. Raskin, “RF-extraction methods for MOSFET series resistances: A fair comparison,” in Proc. Int. Caribbean Conf. Devices, Circuits Syst., 2008, pp. 1–6. [19] X. Federspiel, F. Cacho, and D. Roy, “Experimental characterization of interaction between hci, off state and bti degradation modes,” in Proc. IEEE Int. Integr. Reliab. Workshop, 2011, pp. 133–136. [20] L. Negre, D. Roy, S. Boret, P. Scheer, N. Kauffmann, D. Gloria, and G. Ghibaudo, “Hot carrier impact on the small signal equivalent circuit,” in Proc. IEEE Int. Integr. Reliab. Workshop, 2010, pp. 72–75. [21] L. Negre, D. Roy, S. Boret, P. Scheer, D. Gloria, and G. Ghibaudo, “Advanced 45 nm MOSFET small-signal equivalent circuit aging under DC and RF hot carrier stress,” in Proc. IEEE Int. Reliab. Phys. Symp., 2011, pp. HV.1.1–HV.1.4. [22] V. Huard, N. Ruiz, F. Cacho, and E. Pion, “A bottom-up approach for system-on-chip reliability,” Microelectron. Reliab., vol. 51, no. 9–11, pp. 1425–1439, 2011.

Patrick Scheer was born in Grenoble, France, in 1970. He received the engineering degree in electronics from the Ecole Nationale Supérieure d’Electronique et de Radioélectricité de Grenoble, France, and the M.S. degree in optics, optoelectronics and microwaves from the Institut National Polytechnique de Grenoble, France, in 1993. He received the Ph.D. degree in optics and optoelectronics from the Ecole Nationale Supérieure de l’Aéronautique et de l’Espace, Toulouse, France, in 1998. He joined the central R&D site of STMicroelectronics, Crolles, France, in 1998 to develop high frequency models for MOS transistors in advanced CMOS and BiCMOS technologies. His interests are in the small-signal, noise and largesignal behavior of active devices, device physics, compact modeling and parameter extraction methodologies. He is currently leading a modeling group focused on analog, high frequency and high voltage devices and applications.

Laurent Negre received the engineering degree in physics with a specialization in microtechnology and microsystems from the Institut National des Sciences Appliquées de Toulouse, France, in 2008. He is currently working toward the Ph.D. degree at the Institute of Microelectronics, Electromagnetism and Photonics (IMEP-LAHC), Minatec, Grenoble. His Ph.D. work, which is devoted to the study of MOSFET RF reliability, is carried out in the reliability group of ST Microelectronics, Crolles, France.

David Roy received the B.S. and M.S. degrees in physics from the Institut National Polytechnique de Grenoble (INPG), France, in 1997 and 1998, respectively, and the Magistere of Physics Research from University Joseph Fourier de Grenoble, France, in 1998. He worked for the CEA-Grenoble on the 3D-optical micro-system in the “Laboratoire d Electronique et des Technologies de l information” (LETI) in 1999. In 1999, he joined STMicroelectronics as a Reliability Engineer, working on oxide and device reliability. Since 2007, he is in charge of the Front-end Reliability team. His current research interests include transistor reliability as well as low k interconnect reliability Florian Cacho was born in Belfort, France. He received the Ph.D. degree in material science from l’Ecole des Mines de Paris, Paris, France, in 2005. From 2005 to 2009, he was with the Technology Modeling department of STMicroelectronics, Crolles. Since 2009, he has been in charge of design for reliability activity.

Sebastien Jan received the B.S. and M.S. degrees in electronics engineering from ENSERG (INPG), Grenoble, France, in 2004. Since 2006 he has been with STMicroelectronics, Crolles, France, where he works on the development of high performance passive components in advanced bulk and SOI RF CMOS technologies. His current work deals with RF and millimeter wave characterization methods (noise and power). Samuel Boret was born in Malo-les-Bains, France, on December 23, 1972. He received the Ph.D. degree from the University of Lille, Lille, France, in 1999. In 1996, he joined the Centre Hyperfréquences et Semiconducteurs, University of Lille. As part of his graduate studies, he was involved with monolithic integrated circuits in coplanar technology for applications of reception up to 110 GHz. He is currently with Central Research and Development, RF Electrical Characterization Group, STMicroelectronics, Crolles, France. His main interests include design, characterization and modeling of RF devices in advanced silicon technologies. Daniel Gloria received the engineering degree in electronics from the Ecole Nationale Supérieure d’Electronique et de Radioélectricité, Greboble, France, in 1995, and the M.S.E.E. degree in optics, optoelectronics and microwaves design systems from the Institut National de Grenoble (INPG), France. He spent two years, from 1995 to 1997, in ALCATEL Bell Network System Labs, Charleroi, Belgium, as an RF Designer Engineer and was involved in the development of the Cablephone RF front end and its integration in HybridFiber-Coax telecommunication networks. Since 1997, he has been working for ST Microelectronics, Technology R&D Crolles, TPS Laboratory where he is in charge of HF characterization and RF passives modeling group. His interests are in optimization of active and passives devices for HF applications in BiCMOS and CMOS advanced technologies. Gérard Ghibaudo was born in France in 1954. He graduated from Grenoble Institute of Technology in 1979, where he received the Ph.D. degree in electronics in 1981 and the State Thesis degree in physics in 1984. He became Associate Researcher at CNRS in 1981 where he is now Director of Research at CNRS and Director of IMEP-LAHC Laboratory located at MINATEC-INPG center. During the academic year 1987–1988 he spent a sabbatical year at Naval Research Laboratory in Washington, DC, where he worked on the characterization of MOSFETs. His main research activities were or are in the field of electronics transport, oxidation of silicon, MOS device physics, fluctuations and low frequency noise and dielectric reliability. He has surpervised over 70 Ph.D. students in his career and has been author or co-author of over 342 articles in International Refereed Journals, 543 communications and 65 invited presentations in International Conferences and of 25 book chapters. Dr. Ghibaudo was or is involved in several European research projects (Joint coordinator of BRA-NOISE, participant to APBB, ADEQUAT 1-2-+, PROPHECY, ADAMANT, NANOCMOS, PULLNANO, FOREMOST, HONEY, MODERN, UTTERMOST, SQWIRE, etc.) or national programs (coordinator of RMNT-Ultimox, participant to RMNT-CMOS-DALI or ANR Multigate projects, etc.). Dr. G. Ghibaudo was or is a member of several technical/scientific committees of International Conferences (ESSDERC, WOLTE, ICMTS 96–2004, MIEL, ESREF, SISC1996-2000, MIGAS, ULIS, IEEE/IPFA, ICMTD, FaN 2006, ICNF 2005- ). He was co-founder of the First European Workshop on Low Temperature Electronics (WOLTE 94) and organizer of 17 Workshops/Summer School during the last 15 years. He is also member of the Editorial board of Solid State Electronics and Associate Editor of Microelectronics Reliability Journals.