SYLLABUS FOR M.TECH. (VLSI DESIGN & EMBEDDED SYSTEMS)

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The Performance of the student of M.Tech shall be graded on the basis of percentage of ... syllabus and the student will be required to attempt only 5 questions.
SYLLABUS FOR M.TECH. (VLSI DESIGN & EMBEDDED SYSTEMS) DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG.

SCHEME OF STUDIES & EXAMINATION MASTER OF TECHNOLOGY(VLSI DESIGN & EMBEDDED SYSTEMS) SEMESTER – I

EFFECTIVE FROM THE SESSION 2012-13 Course No.

Course Title

Teaching Schedule Marks L T P Session Exam. al

Total

Duration of Exam

IC Fabrication Technology

4

-

-

50

100

150

3

Digital VLSI Design

4

-

-

50

100

150

3

Hardware Description Languages MT-VLES Embedded System Design 507

4

-

-

50

100

150

3

4

-

-

50

100

150

3

MT-VLES Signal Processing 509

4

-

-

50

100

150

3

-

-

3

50

50

100

3

-

-

3

50

50

100

3

20

-

6

350

600

950

MT-VLES 501 MT-VLES 503 MT-VLES 505

MT-VLES -511 MT-VLES 513 TOTAL

Digital VLSI Design Lab Embedded System Design Lab

SCHEME OF STUDIES & EXAMINATION MASTER OF TECHNOLOGY (VLSI DESIGN & EMBEDDED SYSTEMS ) SEMESTER – 2

EFFECTIVE FROM THE SESSION 2012-13 Course No.

MT-VLES 502 MT-VLES 504 MT-VLES 506 MT-VLES 508

MT-VLES 510 MT-VLES 512 TOTAL

Course Title

Analog IC Design Embedded system DesignII Low Power VLSI Design Embedded system for Wireless & Mobile communication Elective -I Embedded system-II lab Analog IC Design Lab

Teaching Schedule Marks L T P Sessional Exam.

Total

Duration of Exam

4

-

-

50

100

150

3

4

-

-

50

100

150

3

4

-

-

50

100

150

3

4

-

-

50

100

150

3

4 -

-

3

50 50

100 50

150 100

3 3

-

-

3

50

50

100

3

20

-

6

350

600

950

SCHEME OF STUDIES & EXAMINATION MASTER OF TECHNOLOGY (VLSI DESIGN & EMBEDDED SYSTEMS) SEMESTER -3

EFFECTIVE FROM THE SESSION 2012-13 Course No.

Course Title

MT-VLES Adaptive Signal -601 Processing MT-VLES Embedded Control system -603 Elective -II MT-VLES Adaptive Signal -605 Processing Lab MT-VLES Seminar -607 MT-VLES Minor Project -609 TOTAL

Teaching Schedule Marks L T P Sessional Exam.

Total

Duration of Exam

4

-

-

50

100

150

3

4

-

-

50

100

150

3

4 -

-

3

50 50

100 50

150 100

3 3

-

-

2

50

-

50

-

4

100

9

350

12

-

100 350

700

SCHEME OF STUDIES & EXAMINATION MASTER OF TECHNOLOGY ( VLSI DESIGN & EMBEDDED SYSTEMS) SEMESTER -4

EFFECTIVE FROM THE SESSION 2012-13 Course No.

Course Title L

MT-VLES Dissertation -602 TOTAL

-

Teaching Schedule Marks T P Sessional Exam.

Total

-

24

200

400

600

-

24

200

400

600

M.D. University, Rohtak Scheme of Studies & Examinations for Master of Technology (VLSI DESIGN & EMBEDDED SYSTEMS)

The Performance of the student of M.Tech shall be graded on the basis of percentage of marks and corresponding grades as mentioned below : A) Marks 85 75 60 50 40 00

Grades A+ A B C D E

Letter Grades A+ A B C D E

Performance Excellent Very Good Good Fair Pass Repeat

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