Test-per-clock detection, localization and identification of interconnect faults Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka Silesian University of Technology, ul. Akademicka 16, Gliwice, Poland
[email protected], {tgarbolino, kgucwa, ahlawiczka} @polsl.pl
Abstract The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable.
1. Introduction In today’s deep-submicron technologies there is an increasing frequency of occurrence of faults in the interconnects between IP cores in SoC, resulting mainly from the imperfection of the fabrication process [15]. Hence, diagnosing and testing of structural defects becomes critical. Interestingly, information that is related only to the detection of a fault is sufficient merely for in-field testing, whilst if the manufacturing testing is of concern, information on the fault type is extremely essential as it makes possible to improve the technological process (eg. to eliminate frequent shortcircuits in some areas of SoC) and to introduce necessary changes of the design (eg. to reduce crosstalk between bus lines). In case of redundant structures, eg. those employing FPGA technologies, information about the fault can help to reconfigure the system. Some kinds of interconnect faults, including delay faults, may occur at higher frequencies of signal changes only. Therefore, there is a need to use self-test methods to allow atspeed testing [11]. Unfortunately, traditional interconnect testing approaches (test-per-scan schemes) are useless here [12,4,16,17]. Therefore, at-speed testing can be achieved by combining pattern generation with a response analysis in a test-per-clock scheme inside the core [13,14]. In one of the recent papers [9] Jutman has proposed a method of interconnect testing that combined short testing
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times with an easy and quick localization of static faults in the interconnects. Unfortunately, there is a flaw in this method that does not provide to identify what the fault type is. Further, it does not manage to detect difficult-to-detect strong driver shorts. Its Interleaved True/Complement Counting Sequence (IT/C) causes frequent changes of the state of the nets under test, (NUTs) thereby increasing the power consumption of the circuit under test (CUT). Instead, a short sequence reduces the probability of the stimulation of dynamic faults whilst the response verification method limits the spectrum of the applicable test sequences to interleaved sequences only.
2. Motivation The idea conceived by the authors of this paper was to create a hardware tool for response verification that would be considerably more versatile than that described in [9] at comparable implementation costs. The proposed solution employs a signature analysis technique [1] to verify the interconnects’ performance and to identify possible faults. The signature obtained after compaction of the response of the NUTs in a Multi Input Signature Register (MISR) permits first of all to check whether the NUTs are fault-free. In case of fault detection, signatures obtained separately for individual nets make possible to localise faulty nets and identify static faults (i.e. stuck-at faults or shorted nets). In [5,6] it was proven that an IET-MISR (Internal Exclusive-OR linear feedback MISR composed of T-type flip-flops) implementing primitive polynomial and built of T-type flip-flops has better detection properties than a classic IEDMISR (Internal Exclusive-OR linear feedback MISR composed of D-type flip-flops) with the same primitive polynomial in terms of mutual cancellation phenomenon, and hence we used an IET-MISR-based approach. Indeed, flexibility is one of the main advantages here: whether short detection test sequences characterized by confounding-limited resolution are of concern or long, full detection-capacity sequences ensuring the maximum resolution in the phase of fault detection are required. Some examples of the former case include the True/Complement Counting Sequence (T/C) [18] and IT/C [8,9] that can be generated by effective test generators proposed in [3] and [8,9] respectively. The classic Walking 1’s Test (W1) [4] belongs instead to the family of long sequence tests. High flexibility means shorter interconnect testing times. The testing process can be split into two phases. During the first phase, detection of faults is performed across all SoCs and hence this phase should be as short as possible. Con-
versely, the localization of faulty nets and the identification of fault types are performed on faulty circuits only. Here, high detection resolution is a must. It therefore results from the above considerations, that in order to reduce testing time it is required to use short detection sequences and long fault localization and identification sequences respectively. The organization of the remaining sections of the paper is as follows. Section 3 is devoted to the general interconnect fault detection and identification concept. Section 4 deals with the algebraic description of the operations of the MISR used in the process of localization and identification of faults. Section 5 describes a hardware implementation of the proposed solution, whilst the scenario of the whole interconnect testing process is illustrated in Section 6. The conclusions are summarized in Section 7.
3. The concept In this paper, both the detection of interconnect faults, their localization and the identification of fault types employ a MISR-based compactor of response sequences produced by the tested interconnects. As a result of MISR compaction there is produced a signature, which is compared with a reference one (golden signature). Any discrepancy indicates a presence of faults (fault) in the NUTs that are then localised and identified by a MISR converted in a Single Input Signature Register (SISR) having its serial input connected to the currently selected net. Here, the compaction of individual test response bit sequence is performed and specific signature is produced to check whether specific net is faulty or not. In addition, the signature value makes possible to identify the kind of individual faults: stuck-at-0 (sa0), stuck-at-1 (sa1), short – see Section 4. It is also possible to have the indication, what nets are shorted. In order to obtain such results, the same test sequence is applied to the interconnection network during testing of each net. Let us notice, that the fault localization and identification technique resembles that used in the seventies by Hewlett Packard for testing of digital logic packages. HP used to run a package, that periodically was producing a repeated, not necessarily the same sequence of bits at each test point. Then, a probe of signature analyzer, being a 16-bit SISR was applied at each point to produce a set of signatures and to check whether the package was faulty or not and to roughly identify possible faults. Fig. 1 provides the logic schematic diagram of the said compactor. As it can be seen, AND gates are used to convert MISR into SISR. When a0=a1=...=ai=...=an-1=1 then the circuit functions as a MISR and can be used to detect faults. If, instead, a0=a1=... aj=...=an-1=0 and ai=1 (where 0≤ i, j ≤ n-1 and i≠j), this circuit functions as a SISR to make possible fault localization and identification. Then, the i-th compactor input becomes a serial input of the SISR.
4. An algebraic analysis of a MISR This Section deals with the mathematical equations that we used in the analysis of the operations of MISR-based compactor. Special focus is given here to the concept of a normalized signature.
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interconnect test generator
a 0
a 1
T
a 2
T
T
p1
1
a n-2
...
p2
a n-1
T
T
pn-2
pn-1
Fig. 1. A linear IET-MISR compactor implementing polynomial p( x ) = ( x + 1) n +
n −1
∑ ( x + 1)
i
i =1
pi + 1
In further part of the paper, we will use the IEc-MISR symbol, where c ∈ {D, T} to indicate both IED-MISR and IET-MISR when discussing the issues that are common for these two registers. Operations of a n-bit IEc-MISR compactor during y clock cycles can be represented by the following equation, using a polynomial notation of sequences and binary vectors over the field GF (2): [u(x) + xyh(x)]/p(x) = q(x) + r(x)/p(x),
(1)
All symbols used in this Equation and in some further considerations have the following meaning: k
is the coefficient dependent on the kind of the IEc-MISR: k=0 for IED-MISR, k=1 for IET-MISR. n −1 is the equivalent polynomial ui ( x )( x + k ) i resulted from y-bit binary sequences u(x) = i =0 ui(x) applied at the input of the i-th flip-flop of IEc-MISR (i=0..n-1);
∑
deg u(x) ≤ y+n-2. n −1
h(x) =
∑ g (x + k) i
i =0
n −1
r(x) =
∑ s (x + k) i
i =0
n −1
s(x) =
∑s x i
i =0
i
i
i
is the polynomial containing gi bits of the initial state of IEc-MISR; deg h(x) ≤ n-1. is the polynomial containing si bits of the final state of the register; it constitutes the remainder of division (1); deg r(x) ≤ n-1. is the polynomial representing the final state of IEc-MISR – a signature; deg s(x) ≤ n-1.
q(x)
is the polynomial representing a sequence of bits at the output of IEc-MISR; it constitutes the quotient of (1); deg q(x) ≤ m-1.
p(x)
it is the characteristic polynomial of IEc-MISR; deg p(x) = n.
Note the operations of addition and multiplication in both the above description and in the all equations are modulo 2-based. Where the value of the sequence at the serial output of IEc-MISR represented by the quotient q(x) is not of interest,
but the only interesting part is the remainder r(x), the Equation (1) can be transformed as follows: r(x) = [u(x) + xyh(x)] mod p(x)
(3)
where ri(x) is the value of the remainder obtained in the case, where only the sequence ui(x) ≠ 0. Note, that in Equation 3, the value of the remainder ri(x) and consequently that of its signature si(x) depend on the number i of that IEc-MISR input, to which the sequence ui(x) is applied. This effect on the signature exerted by the number of the IEc-MISR input renders the identification of short nets based on incorrect signatures related to the i-th and r-th inputs extremely difficult. In addition, it is necessary to memorize the reference signature for each i-th input and the stuck-at-1 signature of the net connected to that input. The stuck-at-0 signature corresponding to any net is always 0. Hence, the amount of signatures to be memorized for an n-bit IEc-MISR is 2n+1. Consequently, a compactor composed of m independent n-bit IEc-MISRs (see Section 5) will require to memorize 2nm+1 signatures. In order to avoid the said inconvenience, let us multiply χ both sides of Equation 3 by (x+k) -i, where χ is a constant, the value of which will be established later: (x+k)χ-iui(x)(x+k)i mod p(x) = (x+k)χ-iri(x) mod p(x)
(4)
what after the reduction gives: (x+k)χui(x) mod p(x) = (x+k)χ-iri(x) mod p(x)
(5)
Let us notice that the value of the left side of the Equation 5 depends only on the value of the sequence ui(x) applied at the i-th input of the register, instead it is not affected by the number i of this input. In that case, the value of the expression: χ
si*(x) = (x+k) -iri(x) mod p(x),
(6)
will also not depend on the number i of the input and only on the value of the sequence ui(x). The polynomial si*(x) will be referred further as a normalized signature. Thereby, if for two different i-th and r-th inputs there is satisfied the relation ui(x)=ur(x), then si*(x) = sr*(x). In Equation (6), the normalized signature si*(x) is represented by the remainder ri(x). In practice, it is possible to read the value of the non-normalized signature si(x) that corresponds to that remainder. The dependence between the values of these of two polynomials is described by the following theorem. Theorem 1 In a IEc-MISR, where c ∈D, T, the remainder r(x) and the signature s(x) are interrelated as follows: r(x) = s(x+k), where k=0 for IED-MISR and k=1 for IET-MISR.
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n −1
(2)
Let us assume now, that only i-th input of IEc-MISR receives a non-zero bit sequence, whilst zeros are applied to all other inputs. Then ui(x)≠0 and uj(x)=0 for every j such that 0 ≤ j ≤ n-1 and j≠i. Assume moreover, that the IEc-MISR always starts from zero state, that is to say h(x)=0. So, Equation (3) will be as follows: ui(x)(x+k)i mod p(x) = ri(x)
Proof: Pursuant to Equation 1, s(x) =
n −1
si x i . Hence, s(x+k) = ∑ si ( x + k ) i = r(x). ∑ i =0 i =0
Based on Theorem 1, we can now transform the Equation (6) in the form: si*(x) = (x+k)χ-iri(x) mod p(x) = (x+k)χ-isi(x+k) mod p(x) (7) In order to simplify the calculation of the normalized signature, the value of the constant χ in Equation 7 should satisfy the condition χ-i ≥ 0 for every 0 ≤ i ≤ n-1 , hence χ ≥ n-1. It is best to assume, that χ=n-1, that is to say eg. for n=32 the constant χ=31. The use of normalized signatures extremely simplifies the identification of the nets affected by the same shorts. Let’s assume, that a short include nets connected to the inputs i0, i1, ..., it of IEc-MISR. In consequence, these inputs receive the same erroneous sequence ui ( x ) = ui ( x ) = ui ( x ) = ui ( x ) and in virtue of 0
1
t
2
Equations 5 and 7, the normalized signatures for these nets are identical. Another advantage of the concept of the normalized signature is that for a IEc-MISR of any length n it is sufficient to memorize the value of only n+2 of such signatures: the reference signature sGi*(x) related to each i-th input, the signature of the net stuck-at-1 and the signature of the net stuck-at 0. In case of a compactor composed of m independent n-bit IEc-MISRs, it is sufficient to memorize the value of only nm+2
