may effect double-cube divisors which are either in set D2,2,2 or in D2,2,3. Whenever such a substitution is performed the corresponding double-cube divisors ...
Testability Preserving Transformations in Multi-level Logic Synthesis Janusz Rajski and Jagadeesh Vasudevamurthy VLSl Design Laboratory Department of Electrical Engineering McGill University. 3480 University Street Montreal. Canada H3A 2A7
Abstract We present a new, highly efficient concurrent method for decomposition and factorization. The method employs objects which are either double-cube divisors or single-cube divisors having exactly t w o literals considered concurrently with their complements. We demonstrate that these objects, despite their simplicity. provide a very good framework t o reason about common algebraic divisors and the duality relations between expressions. The synthesis is based on testability preserving transformations, the synthesized multi-level network is fully tested by a complete test set derived for the original circuit.
1.
Introduction
The automatic synthesis and optimization of combinational logic can result in the saving o f design time. higher quality designs, significant improvements of the circuitry, and guaranteed functional correctness [1.2.3]. It is also important that the timing characteristics o f the circuit satisfy the performance requirements, and that the synthesis be done in an acceptable amount of CPU time. In addition t o these traditional requirements, it is also desirable that the synthesized circuits be fully testable [9.10]. The key component of logic synthesis is the factorization and decomposition of Boolean expressions [2.4] which uses algebraic and Boolean transformations. In this paper. we present a new, efficient method for multi-level logic synthesis based on algebraic transformations and De Morgan's laws. We also prove that each o f these transformations preserves testability. The method of synthesis presented in this paper uses a very efficient concurrent method of decomposition and factorization of Boolean expressions. The method is based on very This w o k w a s siipported b y strategic grant MEF0045788 froni the "Microelectronics Fund of Natural Sciences and Engineering Research Council of Ca 11 ad a"
simple objects. namely double-cube divisors and single-cube divisors with only two literals. The double-cube divisors of an expression are the cube-free, multiple-cube divisors of the expression containing exactly two cubes. We demonstrate that these objects, despite their simplicity. provide very good theoretical bases t o : a) reason about common subexpressions. b) determine dual expressions, and c) generate a rich set of good algebraic divisors. Our approach is based on a greedy algorithm which identifies and substitutes a double-cube divisor or a single-cube divisor with two literals. that jointly with its dual expression provides the greatest cost reduction in terms of the number o f literals. The concurrency of the extraction of, double-cube and single-cube divisors is a unique property of this approach which has three important implications : (1) The division by a single-cube divisor can be performed before all divisions by double-cubes are completed. This may generate multiple-cube divisors which are not cube-free, whenever such a relation gives a better reduction of literals. (2) The relation of duality between expressions can be determined and exploited efficiently. (3) Efficient extraction of common subexpressions can be done globally for the entire network. These properties of the method make it very effective. In fact, the results obtained by this method (see table 5 and 6) match the best known literal counts for most benchmark circuits. and in many cases the method generates 8001ean networks with much smaller numbers of literals [3.4.6]. The discussion of testability preservance of algebraic transformations is presented in (9,111. It is shown in 191 that, for each multi-fault in an algebraically factored circuit, with each factor having only positive references in the circuit, there is an equivalent multi-fault in the original circuit. These results imply that. when algebraic factorization is applied t o a minimized two-level circuit, all tests needed for complete multifault coverage of the synthesized circuit can be derived from the single-fault tests for the original circuit. In this work, we introduce a number o f transformations and prove that each one of them preserves testability. This means that, if the original network. two-level or multi-level, is completely tested for single stuck-at faults by a test set T.then the network obtained by any of the transformations can also be tested for single stuck-at faults by the same test T. This implies, for example. that if an input two-level representation is prime and
1990 international Test Conference CH2910-6/0000/0265$01.OO G 1990 IEEE
Paper 15.1 265
irredundant for every output. then the multi-level logic generated by the synthesis algorithm is also prime and irredundant and hence 100 % testable. In addition. a complete test set for the two-level network. also tests the generated multi-level network. We conclude this paper with results on various benchmarks circuits [4.6]. The results include literal counts. along with the CPU time required t o implement these benchmark circuits as random logic, and the number of test vectors actually needed t o test the multi-level logic. We show experimentally that in each case the complete test set for the two-level network covers 100% of single stuck-at faults in the synthesized multi-level circuit.
2.
Concurrent Decomposition Algorithm
In this section we present a new. efficient method for the decomposition and factorization of Boolean expressions. The method employs objects which are either double-cube divisors or single-cube divisors having exactly two literals considered concurrently with their complements. These objects. despite their simplicity. provide very good framework t o reason about common algebraic divisors and the duality relations between expressions. Some of the definitions (21 necessary t o understand this section are as follows:
A variable is a symbol representing a single coordinate of Boolean space. Example : x . A literal is a variable or its negation. Example : x and 5 . A cube is a set C of literals such that x E C implies 3 4 C. A cube represents the conjunction of the literals. Example : { a ,b, Z} is a cube and {a,i%}is not a cube. A sum o f products (SOP) form, also called an expression, is a set of cubes. An expression represents the disjunction of i t s cubes. An expression is nonredundant i f no cube in the expression properly contains another. A Boolean expression f is a nonredundant expression. The support of an expression, written as s u p ( f ) is the set of variables x such that either x E C for some C E f or z E C for some C E f . Informally. it is the set of variables that f is defined over. Example : sup(ab c ) = { a , b, e } . A factored form is a parenthesized algebraic expression which is suitable for multi-level logic representation. Given two Boolean expressions f and g, g is called an dgehraic divisor of f if f = gh r . where h and r are expressions and h is not null. Also sup(g) n sup(h) = 4. I f g has exactly one cube, then g is called a single-cube divisor. I f g has more than one cube. then g is called a multiple-cube divisor. For example. if f = abc abd p . g = ab is called a bd is called a multiple-cube single-cube divisor and g = bc divisor. A Boolean expression f is cube-free, i f the only cube dividing f evenly is 1. Note that a cube-free expression must have more than one cube. For example, ab c is cube-free but not a6 ac and abc.
+
+
The set of all double-cube divisors of where,
+
+
+
Double-cube divisors of a Boolean expression f are cubefree, multiple-cube divisors having exactly two cubes. For
Paper 15.1 266
f
is written as D ( f ) .
"
for i , j
"
D(f) = {did = { C % \ ( c z C j ) , c j \ ( C i " j ) H (1) = 1....n. i # j . where n is the number of cubes in f .
It is evident that the total number of double-cube divisors for a Boolean function with n cubes is O ( n 2 ) . ( c i n c 3 ) is called the base of cubes c, and cJ and the double-cube divisor definition allows double-cube divisors with an empty base. As the name indicates. double-cube divisors have exactly two cubes. A subset of double-cube divisors is represented by, Ilz,y,s.where x is the number of literals in the first cube, y is the number of literals in the second cube and s is the number of variables in the support of any double-cube divisor d. Note that max(x,y) 5 s 5 ( x + y ) . For any d E Dz,y,s.d 6 Dy,z,s and hence without loss of generality, we can assume x 5 y . For example, a double-cube divisor x y gzp E D2,3,4.
+
Let S denote the set of all single-cube divisors. A subwhere k is the set of single-cube divisors is denoted by number of literals in the single-cube divisor. For example. a single-cube divisor ab E S2.
s,.
With this notation, some useful relations between singlecube divisors, double-cube divisors and complements among theni are given below. We assume, in the discussion that follows, that double-cube divisors are extracted from functions' which are prime and irredundant with respect t o every output.
Lemma 1: Dl,1,1 and D1,2,2 are null set. Proof : Follows from the definition of double-cube divisor and the assumption that the Boolean network is prime and irredundant. Q.E.D Lemma 2: For any d E D1,1,2. 2 6 S2 Proof : For any d E D1,1,2, d has a support of 2. If the
+
+
+
support is { a ,b } . then d is either a b. or a 6. or ii b. or i% 6. By the De Morgan's law. the complement of any t i E 0 1 , 1 , 2 is a single-cube divisor having exactly two literals.
+
Q.E.D
+
+ +
+ + + +
example. i f f = ax bx c x . then the double-cube divisors of f are { U b , a c , b c } .
Example : The complement of a + 6 is ab E S2 Lemrn,a 3: For any d E D1,2,3.
6D
Proof : Since D1,2,3 has a support of 3. each variable in double-cube divisors must be different. Hence the complement of d E U1,2,3 cannot be cube-free, and therefore it cannot present in D . Q.E.D
+
Example : a + 6c E D1,2,3. Its complement is i%b i i F . Since U is a set of cube-free divisors,
D.
a6 + ?ie cannot be in
Lemma 4: For any d E D2,2,2, d is either exclusive-or or exclusive-nor expression and
d
f
E D2,2,2.
Proof : Since each cube uses t w o variables and the support of the double-cube divisor is also two. the same variables are used in both cubes. Furthermore, since the double-cube divisor is cube-free. no literal can appear in both the cubes. This implies that a variable must appear in the true forin in one cube and in the complemented form in another cube. A t w o variable function having a t w o cube. four literal algebraic representation, is either exclusive-or or exclusive-nor and hence D2,2,2 = Demr D e z n o r and Dezor n Deznor = 4. For any d E De,,,. E De,norr and for any d E De,fior. E Demr. arid since d E D2,2,2. De,,, C D2,2,2 and Deznor C u2,2,2.2 E D2,2,2. Q.E.D
a
Example : a6
a
+ ba E D2,2,2. Its complement is ab + a6
Figure 1 Existence of duality between expressions
E D2,2,2.
Proof : If duality exists, as indicated by arrows in Figure
Lemma 5: For any d E D2,2,3, a E D2,2,3
1. then f has a complement cube divisor in g. This can be verified by using Lemma 1 t o Lemma 6. For all other double-
Proof : Since each cube uses t w o variables and the support of the double-cube divisor is three. one of the three variables must be present in both cubes. Since the double-cube divisors are cube-free, the common variable must be present in true form in one cube and in the complemented form in another cube o f a double-cube divisor. By De Morgan's and
+
+
absorption laws of Boolean algebra ab 6c = ab 6E. Hence the complements of elements in D2,2,3 are also present in the same set. Q.E.D
Example : i i b + ac E D2,2,3. Its complement is a6
+ a?
E D2>2,3.
W i t h each of the cube divisors a weight is associated which indicates the number of literals that can be saved if the decomposition procedure has t o extract this cube divisor. The algorithm for decomposition is as follows : ALGORITHM 1 Decomposition and Factoring: Input : Set of Boolean equations Output : Set of Multi-level equations
Lemm.a 6 : For any d E D2,2,4,2 $ D
Proof : Similar t o Lemma 3.
cube divisors, d E D(f)-(D1,1,2,D2,2,2,D2,2,3).cannot have complement cube divisors in D ( g ) since the complement of Q.E.D such d cannot be cube-free.
Method :
Q.E.D
begin Generate double-cube divisors with weights using ( 1 )
Given t w o Boolean expressions f and g. the important task during decomposition is t o establish whether a function f has a complement cube divisor in g. Theorem I. below. establish such relations between t w o expressions.
Theorem 1: Let f and g be t w o Boolean expressions. Then if
repeat Select a double-cube divisor d that has a maximum weight. Wdmaz. Check for existence of a single-cube divisor.
If such a single-cube divisor exists call i t s and its weight Wsmm.
if Check is false then Select double-cube divisor d else Select single-cube divisor s
W = Illax(Wd,,,,.W..maz). Substitute the new expression along with its complement. Reconipute weights of affected double-cube divisors.
until ( W < 0) : end ;
then f has neither a complement double-cube divisor nor a complement single cube-divisor in g.
Notice that the process of division by a single-cube divisor
Paper 15.1 267
I
" Figure 2
N2
I
Transformation of networks
may effect double-cube divisors which are either in set D2,2,2 or in D2,2,3. Whenever such a substitution is performed the corresponding double-cube divisors preserve a copy of their original form. in addition t o the new one, t o enable the determination of the duality relation as stated in theorem 1.
3.
Testability Preserving Transformations
In this section we consider networks, two-level or multilevel, which are completely single-fault testable and demonstrate the conditions under which the synthesized circuit can be tested fully by the original test set. The various transformations done during synthesis can be classified as follows : (a) division by a single-cube divisor, (b) division by a doublecube divisor, (c) division by a double-cube divisor and i t s complement concurrently. We demonstrate that the introduced transformations performed on sum-of-product subexpressions preserve testability, which is defined as follows :
Testability preserwance : Let N1 be a network and F a transformation which transforms N1 t o a network N2. de-
A1
a -
2'
0
b
N2
Figure 3 Division by single-cube
Proof : Since K1 and K2 perform identical functions. any two corresponding nodes in ( N I - K1) and (N2 - K2) will perform the same function. This implies that a fault in ( N I - K1) can be sensitized and propagated if and only if the corresponding fault in (N2 - K2) is sensitized and propagated. Q.E.D
F
noted as N1 -+ N2. Let T be a complete test set for single stuck-at faults for N I . We say that transformation F preserves testability with respect t o a test set T . if T is a complete test set for single stuck-at faults in network N2. In the discussion that follows, we use the concept of monotonicity of logic functions which is defined as follows:
Monotonicity (51 : A logic function f is monotone increasing (decreasing) in a variable xj, if changing xi from 0 t o 1 (1 t o 0) causes all the outputs of f that change, t o increase (decrease) also from 0 t o 1 (from 1 t o 0). In order t o prove that a transformation preserves testability, we consider decomposition and factorization as a sequence of transformations, where each time a network N1 is transformed t o N2. In the transformations used in this paper it is assumed that K1 is a single-output sum-of-product subexpression. In fact only a part of the network N I . K1 is transformed t o K2. generating a new network N2. Naturally K1 and K 2 perform the same function. This is shown in Figure 2.
Lemma 7 : A complete test set T detects all single stuckat faults in N I . outside of K1. ( N I - K1). if and only if T detects all single stuck-at faults in N2. outside of K2. (N2 K2).
Paper 15.1 268
Since the testability outside the region of modification is preserved, in order t o prove the testability preservance of a transformation it is sufFicient t o demonstrate that a complete test set for K1 fully tests K2. Single cube extraction is the process of extracting cubes which are common t o two or more cubes. The common part is then created as a new intermediate node as shown in box K2 of Figure 3. Although the portion of the circuit under modification by this transformation belongs t o the AND gates following them, for clarity, it is shown in box K1 of Figure 3. The transformation performed is as follows : from the expression f = abAi abAp ... abA,. a cube, C = ab. is ... extracted and substituted t o obtain f = CA1 CA2 C A , . We show in Theorem 2 that if faults in K1 propagate to f l in NI then faults in K 2 also propagate t o f 1 in N 2 .
+
+ +
+
+ +
Theorem 2 : Single-cube extraction in a single-output sum-of-product subexpression preserves testability.
Proof : Let a i , i = 1 ,.., n, k = 0 , l denote line a' stuck-at k . It can be verified that test vectors in Table 1 are necessary and sufficient t o sensitize the faults in K1 and K2. To detect fault U;, in addition t o the sensitization requirement ab = 11. the propagation condition implies Ai = 1. As
I Am-l C C Table
1
it is a single-output subexpression. i f the fault is detected, it has t o propagate t o output f 1 . All other product lines driving the output t o which the fault propagates must carry a *O'. Notice that the condition A, = '1'is also satisfied in network N2 for any test vector that detects at, since the value of Ai cannot be modified by the fault. The condition on the output OR gate is guaranteed by the monotonicity of network N2 in a: the output is monotonically increasing in a. The fault changes the output value from '1' t o '0'. Since all other inputs t o the OR gates, through which propagation occurs, are already assigned t o *O',they cannot change. Similarly the testability preservance can be proven for other faults that are effected by the transformations :
B
SL K1
Figure 4
Division by double-cube
stuck-at faults on C in circuit Kl.has two parts : the first part obtained by assigning output gl t o '1' and output of 94 to '0' and the second part obtained by assigning output of 94 t o 'l'and output of g l t o '0'. In order t o test stuck-at faults for the inputs C in the transformed circuit K2. we can assign output of g1 t o '1'. or output of 94 t o '1.. or both. Any test set T c obtained for circuit K 1 is sufficient t o detect all stuckat faults on the inputs C. and propagate them t o output y in K2. This result in conjunction with Lemma 7 proves that double-cube extraction from a sum-of-product subexpression Q.E.D preserves testability.
Corollary 1: The transformation opposite t o the singlecube extraction, called substitution. does not preserve testability. Example : Consider a multi-output function having n outputs. with single-cube divisors M and N as follows :
T(CZ1) where T ( a b )
* T(c1)
M = iib
* T(a0) means that any test vector t E T that
detects ab in K1. also tests a0 in K2. Therefore. any test set that detects all single stuck-at faults in K1. also detects all single stuck-at faults in K2. This result. in conjunction with Lemma 7. proves that single-cube extraction from a sum-ofproduct subexpression preserves testability. Q.E.D The double-cube extraction transformation consists of extracting a double-cube from a single-output sum-of-product C ( A + B ) . and is shown in Figure subexpression. A C + C B
+
4.
Theorem 3 : Double-cube extraction in a single-output sum-of-product subexpression preserves testability. Proof : Since both K 1 and K2. in Figure 4. are fanoutfree circuits, only the faults on inputs have t o be considered. The test set T derived for circuit K 1 contains a subset of test T . which detects every stuck-at fault of the vectors TA inputs A on gate g l . Such a subset produces '1' on output g2 ( which implies '1' on 93 ) and '0 'on output 94. t o ensure '0' on 96. in order to propagate the faults on A t o output y. These conditions, and therefore the test set TA. is sufficient t o test stuck-at faults on A in the transformed circuit K2. The same argument holds for the test set Tg C T t o test stuck-at faults on the inputs B. The test Tc that detects
N = ab fl =M
f2 = N f3 = fl
+f2
Assume that M and N are used in other functions. say f 4 .. fn. so that their extraction as intermediate variables is justified. Notice that although f 1 . f 2 and f 3 can be fully tested for single stuck-at faults, some faults will not propagate t o f3. If we substitute f 1 and f2 in f 3 . f3 = iib+ab. f3 contains redundancy. The dual expression extraction in 0 1 , transforms ~ ~ a sum-of-product subexpression. f = abA aB $9. to M = ab and f = M A M B . The transformation is shown in Figure 5.
+
+
+
Theorem 4 : Dual expression extraction in D1,1,2 in a single-output sum-of-product subexpression preserves testability.
Proof : Table 2 shows the test t o detect single stuck-at faults in circuit K 1 and K2. Notice that all six vectors are required t o completely test K 1 for all single stuck-at faults. but
Paper 15.1 269
A
%
b
K2
K1
Figure 5
Division by single-cube and its complement
Table 3 a
b A a C
A a b
C
B
Table 2
K2
a C
B
I
D
Figure 7 Division by d E D2,2,3and its complement
Y
as M = ab
+ ac and f = M A + R B . The transformation is
shown in Figure
7.
KZ
Theorem 6 : Dual expression extraction in D2,2,3in a single-output sum-of-product subexpression preserves testability.
Figure 6 Division by exclusive-or and its complement only four of these vectors are sufficient t o test K2. This result in conjunction with Lemma 7 proves that dual expression extraction transformation preserves testability. Q.E.D The dual expression extraction in
D2,2,2transforms
+
+
+
a
sum-of-product subexpression. f = a6A iibA ii6B abB. as c = a6 iih and f = C A EB. The transformation is shown in Figure 6.
+
+
Theorem 5 : Dual expression extraction in 0 2 ~ in 2 a single-output sum-of-product subexpression preserves testability. Proof : It is known that all four tests are required t o test a Boolean network implementing a two input exclusiveor(exc1usive-nor) function. Hence 8 test vectors are required t o test K 1 for single stuck-at faults. From table 3 it is evident that 4 test vectors are sufficient to test the network K2. This result in conjunction with Lemma 7 proves that exclusive-or(nor) t o exclusive-nor(or) extraction transformation preserves testability. Q.E.D a
Pruuf : Table 4 shows the test t o detect single stuck-at faults in circuits K1 and K2. Notice that all nine vectors are required t o completely test K 1 for all single stuck-at faults. but only five of these vectors are sufficient t o test K2. This result in conjunction with Lemma 7 proves that dual exprespreserves testability. sion extraction transformation in D2,2,3
= iibA + acA + ii6B + aEB.
Q.E.D
The dual expression extraction in sum-of-product subexpression. f
D2,2,3transforms
Paper 15.1 270
--
I
i
J
,
I
[I
uB1 c2
K1
SUN 3/260 CPU seconds. A deterministic ATPG program, PLANET 171. was used t o generate test vectors for two-level networks and TULIP [8] was used t o analyze the fault coverage of the synthesized multi-level network. In our results, we give the number of test vectors required t o test the PLAs (reported by PLANET), the actual number of test vectors required t o test the synthesized multi-level circuit for all single stuck-at faults (reported by TULIP), and the fault coverage.
K2
PLAs are Prime and lrredundant
Figure 8 Resubstitution in Multi-output network
with rewect to every o u t w t
So far we have developed a set of results that are sufficient t o prove single-fault testability of extraction of common expression from a single-output sum-of-product subexpressions. Now, we will extend the results t o multi-output networks. 3.7
In a multi-output network, we may have a number of nodes y1, ..,yk, represented by the same expression (they have the same cover and represent the same function). Resubstitution is a transformation that replaces each copies of yl, ..,yk with a single node as in Figure 8. The conditions under which this transformation preserves testability are given in Theorem 7.
I
level
I
86
1118
2276
I level I I
fc
386 1100%
4443.6 3353
Theorem 7 : Resubstitution of common subexpressions. in a multi- output function. preserves testability if no two subexpressions control the same output. 1984
Proof : If there is any fault f that can be tested in K1. by a test t and propagated t o node y,. then the corresponding fault in K2 also propagates t o yi, in K2. as there is no modification of the network E in K2. Propagation conditions on the inputs of cone C1. in K2. is not effected by y, as there are no reconvergence from other branchs controlled by yI. This implies that a test which detects a fault in K1. on the primary output P,. also detects the corresponding fault on the Q.E.D primary output P, in K2. We demonstrated that the algebraic transformations along with De Morgan's laws presented in this paper preserve testability in the sense that if a network, two-level or multi-level. is completely tested for single stuck-at faults by a test set T then the network obtained by any of the above transformations can also be tested for single stuck-at faults by the same test T .
4.
Experimental Results
This section provides experimental results that illustrate both the effectiveness of the concurrent decomposition algorithm and the testability related properties of synthesized circuits. The concurrent decomposition algorithm described in section 2 has been implemented in a system called PENDULUM. A number of benchmarks circuits (5.61 were used t o analyze the effectiveness of the algorithms - measured by the number of literals required t o implement the synthesized circuit: and the run time efficiency of the program, given in
21.6
vg2
xorlO
I
914
I 102
I 5632 I
36
I
I
I
0.6
32
24
100%
24.6
128
53
100%
189.5
256
86
100%
6.0
154
74
100%
3245.3
3296
452
100%
9.3
320
67
100% 100%
53.0
32
8
434.7
32
9
984
I
32
I
10
100% 1100%
I
Table 5
The results in Table 5 are obtained using PLAs which are prime and irredundant for every output. These PLAs were first minimized using the single-output option of ESPRESSO 151 and then decomposed. Hence the input PLA comprised of a set of prime and irredundant single-output, two-level functions without product term sharing and hence no substitution is required. It can be seen from Table 5 that in each rase the complete test set for a two-level network covers 100% of single stuck-at faults in the synthesized multi-level circuit. This experiment not only confirms the testability preservance of the transformations discussed in section 2. but also shows the effect of the test set compression, which is due t o the
Paper 15.1 271
pla
final
CPU
init
lit
sec
lits
SOP
no of pattern two
multi
level
level
fc
5xpl
353
163
1.7
90
43
97.76%
9sym
595
263
95.5
248
137
100%
add6
2551
85
220
384
25
100%
Tables 5 and 6 also demonstrate the effect of single output minimization versus multiple-output minimization in terms of the literal count and the CPU time required for synthesis. For example, for PLAs apes1 and seq. multiple-output minimization generates the smallest circuit compared t o the one obtained through single-output minimization. Seq is twice as small, when multiple-output minimization is used. and is minimized approximately 50 times faster. In the case of PLA apes2. single-output minimization is better than multipleoutput minimization' (literal count is 422 compared t o 452). For 2 out of 20 PLAs. single-output minimized PLAs resulted in smaller literal counts, when compared t o multiple-output minimized PLAs. For 9 PLAs. multiple-output minimized PLAs resulted in smaller number of literals. The nine remaining PLAs were identical for single and multiple-output minimization. Overall. multiple-output minimized PLAs resulted in smaller literal counts in less CPU time. The tot a l numbers are : 8327 literals and 7341.86 CPU seconds for multiple-output minimized PLAs. and 10667 literals and 34851.90 CPU seconds for single-output minimized PLAs. In general, a multiple-output minimized PLAs require less product terms and results in smaller area and requires less CPU time
I
PLA - apex4
2 I
Table 6 mapping of many fault sites into one fault as the decomposition and factorization proceeds. The experimental results show that the test set for a multi-level network can be up t o 1 to 10 times smaller than the test set for the corresponding two-level network. In the case of single-output minimized PLAs. the total number of test patterns required t o test all the two-level structures is 12988. but 3430 test patterns are required t o test all the multi-level structures, which indicates an overall reduction of 1 t o 4.
I
3
1197 3363
2657 2653 I
I
I
466.6 I
I 1198
I 10 I
2438
I 1181 I3307 I 7906.3 I
Full
2427
1171 3287 19271.6
I3339
I
I
2605
4
I
446.8
1205 3364
451.9
I
Table 7 A second series of experiments, summarized in Table 6. was performed t o study the effect of multiple output minimization. which does not guarantee that the circuit is prime and irredundant for every output. Hence, unlike the previous experiment, substitution is performed on the minimized PLAs and the product terms were shared. After decomposition it can be seen that for 8 out of 20 PLAs the fault coverage is less than 100 %. Clearly testability with respect t o a given test set is not preserved. Moreover, for some circuits an experiment was performed. by an ATPG program [12]. where it was found that all the faults that are not covered by the test set were proven untestable. The Boolean overlap of terms from multiple outputs may create redundancy when each output is viewed separately.
Paper 15.1 272
1~1
I
I
.'
The literal count and the CPU time presented in Tables
5 and 6 are obtained by techniques which extracts cube divisors from the network irrespective of the number of literals in them. As a consequence, the synthesis procedure may generate expressions that have a larger number of literals in them. However, during technology mapping, these larger expressions may be further decomposed in order t o map these expressions t o a set of library primitives. A series of experiments was performed t o limit the number of literals in each of the expressions generated during the decomposition. This was performed by limiting the number o f literals. n. in the double-cube divisors. The final decomposed functions were mapped t o a particular library. The literal count in SOP form,
the number of gates and the final area along with the CPU time for one of the benchmarks. ape24.is given in Table 7. It can be seen that by limiting the number of literals in a doublecube divisor t o two (generating only expressions of the form n b ) . the final literal count in SOP form is increased by 9%. the number of gates and the final area is increased by 2% compared t o full synthesis. However there is a striking reduction of CPU time by 98%. This is mainly due t o the fact that the total number of double-cube divisors processed during the partial synthesis. is much smaller compared t o the total number of double-cube divisors that would have been processed during the full synthesis. For the same benchmark, by limiting the number of literals in double-cube divisors t o less than or equal t o 10. we can obtain the same quality of results as that of the full synthesis but in 50% less CPU time. In general for large circuits. by controlling the value of n. one may obtain the same quality of results as that of full synthesis within a reasonable amount of CPU time.
+
5.
Conclusions
We presented a new, very efficient method for the decomposition and factorization of Boolean expressions, which produces irredundant multi-level networks. The method is based on very simple objects. namely double-cube divisors and single-cube divisors with only two literals. We demonstrated that these objects, despite their simplicity. provide a very good framework t o reason about common algebraic divisors and the duality relations between expressions. Since both the time and space complexity of the operations on doublecube divisors and single-cube divisors is polynomial in the size of the two-level representation. the algorithms run much faster than those based on kernels [2]. We demonstrated. both theoretically and experimentally. that the decomposition and factorization transformations introduced in this paper preserve testability, which implies that a complete test set developed for an input network gives also complete coverage of faults in the synthesized multi-level network.
6.
[6]**Introductiont o Synthesis Benchmarks” - Second International Workshop On Logic Synthesis North Carolina. USA May 23-26,1989.
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[9]Hachtel G..Jacoby R.. Keutzer K.. Morrison C.. ” O n properties of algebraic transformations and the multifault testability of multilevel logic”, ICCAD 1989.pp. 422-425.
[lo] Devadas S..
Tony Ma H . . Newton A.R.. Sangiovanni Vincentel1i.A.. Optimal logic synthesis and testability: Two faces of the same coin”. ITC 1988. pp. 4-12. “
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testable multi-level circuits”. Fourth technical workshop in new directions for IC testing.. Oct 24-26 1989. Victoria B.C.. Canada, pp. 1-20.
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