International Journal of Computer Science and Information Security (IJCSIS),. Vol. 14, No. 7, July 2016. 214 https://sites.google.com/site/ijcsis/. ISSN 1947-5500 ...
International Journal of Computer Science and Information Security (IJCSIS), Vol. 14, No. 7, July 2016
Towards the design of Fault Tolerent Binary Comparator by Parity Preserving Reversible Logic based Multi Layer Multiplexer Biswajit Das
Shefali Mamataj
Saravanan Chandran
Murshidabad College of Engineering & Technology Berhampore, India
Murshidabad College of Engineering & Technology Berhampore, India
National Institute of Technology Durgapur, India
Abstract—Reversible circuits which are Parity-preserving are
This is the smallest amount of energy necessary for the processing of a bit. Bennett [2] showed that power dissipation may be zero in logical circuit if and only if the circuit is consisting of reversible logic gates. Although reversibility can recover loss of bit but it is unable to identify the bit error in the circuit. Reversible circuits that are fault tolerant must be able of preventing errors at outputs. Any structure consists of faulttolerant components are capable of the detection and correction of faults easily and simply. In communication field and many other applications, fault tolerance is obtained by means of parity. As a result, parity preserving reversible circuits may be the upcoming designing swing towards the growth of fault tolerant reversible systems. Most gates used in digital design are irreversible. For example the AND, OR and EXOR gates do not carry out reversible operations. Out of the commonly used gates, only the NOT gate is reversible. To design reversible circuits a set of reversible gates is required. A number of such gates have been proposed over the past decades. Among them are the controlled-not (CNOT) which was proposed by Feynman [3],Toffoli, and Fredkin [4, 5] gates. Comparison between two binary numbers has an extensive variety of application in encryption devices, microprocessors, sorting networks, communication systems etc. Therefore, binary comparator is an imperative circuitry in recent VLSI design and nanotechnology [6]. Therefore in this paper, we have presented a fault tolerant reversible binary comparator circuit which uses a lesser amount of number of gates, a lesser amount of number of garbage output, and a lesser amount of constant input and hardware complexity. Three lemmas are also presented here to prove the parity-preserving property of the proposed three fault tolerant gates to be precise FTM, FTC and FATOC in that order. This paper is organized as follows. Section II, specifies the ideas about the reversible logic, fault tolerant logic, basic definition of some fault tolerant reversible gates. Section III shows our proposed fault tolerant reversible gates and the proof of their parity preserving property. This section also shows multiplexer design using proposed fault tolerant reversible gate FTM. Section IV describes the design of proposed fault tolerant reversible binary comparator (FTCom)
nowadays getting more weight towards the progress of designing systems having fault-tolerance in the field of nanotechnology. The reversible circuit which preserves parity must have the parity preserving property means the input vector parity must be the same to the output vector parity. It contributes a expansive category of finding faults in the circuit which can be detect at the circuit outputs. Thus in a single word reversible logic circuits which preserves parity will be more beneficial towards the progress of fault free circuit realization. In this paper we have proposed three new fault tolerant reversible gates FTM, FTC and FATOC for optimizing the circuit in terms of the gate number, garbage outputs, hardware complexity and constant inputs. This work targets implementation of reversible Fault Tolerent Comparator (FTCom) by Reversible Logic-based Multi Layer Multiplexer of proposed FTM. Furthermore the design is also presented by the obtainable fault tolerant reversible gates and the proposed gates FTC & FATOC. We have also presented three lemmas to verify the fault tolerance or parity preserving property of these proposed FTM, FTC and FATOC gate respectively.
Keywords- Fault Tolerance, Parity-Preserving Reversible Gate, Reversible Logic, Comparator I.
INTRODUCTION
Reversible logic is the most admired conception regarding the energy efficiency in the area of computations. It is promising as a vital area to investigate. It can be used for wide applications in several fields, for instance low power CMOS design, quantum computing and optical information processing. An attractive point of view of the reversible logic is that to construct digital devices which can realize processing unit of computation having almost zero power dissipation. Landauer [1] showed that for the computations of irreversible circuit, for each bit an amount of energy 𝑘𝐵𝑇𝑙𝑛2 Joules is lost as a heat. The energy 𝐸 bit necessary for one bit of operation is specified by Shannon-Von Neumann-Landauer (SVNL) expression in equation (1). 𝐸bit ≥ 𝐸SVNL = 𝑘𝐵𝑇𝑙𝑛2 = 0.017 eV………………. (1) 𝑘𝐵 = Boltzmann constant 𝑇 = 300 K.
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in different ways. Section V gives the comparison results and summary of the proposed fault tolerant reversible circuits. Finally, the conclusion is given in Section VI. . II.
PRELIMINARIES
Figure2. Fredkin Gate
A. Reversible Logic A logic gate can be defined as reversible if the mapping of its input vectors to output vectors is bijective that means for each specific output is related to the specific input and also the number of inputs is the same as to the number of outputs [7]. The important cost metrics in reversible logic circuits are the gate count, constant input, garbage output, hardware complexity and quantum cost. The cost of every 2 × 2 gate is the unity and the cost of 1 × 1 gate is zero [8]. Any reversible logic can be possible to implement with primitive gates such as 2 × 2 reversible gates and 1 × 1 NOT gates. Reversible logic does not allow the fan outs and feedback paths.
Modified IG Gate (MIG): A 4*4 Modified IG gate is shown in figure 3 [12]. The input vectors are specified as A, B and C and output vectors are given as P = A, Q = A B, R = AB C and S = AB’ D.
Figure 3.Modified IG gate
B. Fault-Tolerant Logic Fault tolerant system is able to work appropriately even in the occurrence of the failure of some of its elements. Any structure consists of fault-tolerant components are capable of the detection and correction of faults easily and simply. A fault tolerant reversible gate also can be said a conservative gate [9]. The parity of input vectors and output vectors must be equal. Let us consider the input vectors be IV= I0, I1. . . I𝑛−1 and output vectors of any fault tolerant gate be OV = O0, O1. . . O𝑛−1, where
Islam Gate (IG): A 4*4 IG gate is shown in figure 4 [13]. The input vectors are specified as A, B and C and output vectors are given as P = A, Q = A B, R = ABC and S = BDB’ (AD).
Figure 4. Islam Gate
New Fault Tolerant (NFT): A 3*3 NFT gate is shown in figure 5[14]. The input vectors are specified as A, B and C and output vectors are given as P = A, Q = BC’ AC’ and R = BCC’.
(i) IV ⟨Bijective⟩ OV, (ii) I1 I2
In-1 O1 O2 On-1.
C. Fault Tolerant Reversible Logic gate Many parity preserving means fault tolerant reversible gates have been already proposed by many authors. A small number of favourable parity preserving gates are given as follows: Feynman Double Gate (F2G): A 3*3 Feynman Double Gate (F2G) is shown in figure 1 [10]. The input vectors are specified as A, B and C and output vectors are given as P = A, Q = A B, and R = AC. Quantum cost is given as equal to 2.
Figure 5. New Fault Tolerant Gate
III.
PROPOSED GATE
In this section, we have proposed three new fault tolerant reversible gates named FTM, FTC and FATOC in subsections III.A, III.B and III.C, respectively. Truth table of these gates is also presented in this section which shows their reversibility as well as their parity preserving property. Three lemmas are also presented in this section to prove the parity preserving property .Also in subsection III.D designing of fault tolerant multiplexers by FTM gate has been shown.
Figure1. Feynman Double Gate
Fredkin Gate (FRG): A 3*3 Fredkin gate (FRG) is shown in figure 2 [11]. The input vectors are specified as A, B and C and output vectors are given as P = A, Q= A’B AC and R = A’C AB. Quantum cost is equal to 5.
A. Proposed fault tolerant reversible FTM gate In this subsection, a new 3*3 fault tolerant reversible gate namely FTM gate is proposed. The proposed gate and its truth table is given away in Fig. 6 and Table 1.respectively.It can be
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revealed from the truth table that the input pattern related to a particular output pattern can be uniquely determined and find out the input-output bit parity.
notified from the truth table that the input bit pattern related to a specific output bit pattern can be possible to determine uniquely and find out the input-output bit parity.
.Figure 6. FTM Gate
Figure 7. FTC Gate
Therefore it can be said that the proposed FTM gate is a reversible gate. TABLE I.
Therefore it can be said that the proposed FTC gate is a reversible gate.
TRUTH TABLE FOR FTM GATE
TABLE II.
TRUTH TABLE FOR FTC GATE
Inputs A
Inputs B
P
Outputs Q
C
R
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
P 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Outputs Q R 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1
S 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0
Lemma 1: Proposed FTM Gate is a Fault Tolerant Gate Lemma 2: Proposed FTC Gate is a Fault Tolerant Gate Proof: The input vectors and output vectors of FTM gate are Iv = {A, B, C} and Ov = {B, (B’ABC), (B’CAB)} respectively. From Section II.B, we can know that input parity and output parity will be same in fault tolerant or parity preserving gate. Therefore, the input parity of FTM gate is = ABC
Proof: The input vectors and output vectors of FTC gate be Iv = {A, B, C, D} and Ov = {A’, (AB’C), (A’BC), (ACD)’} respectively. From Section II.B, we can be familiar with that input parity and output parity must have to be same in fault tolerant or parity preserving gate. Thus, the input parity of FTC gate is = ABCD
Output parity of FTM gate is = B (B’ABC) (B’CAB) = B(1C) B’A (B’CAB) = BC’ B’(A C AB = B(C’ A) B’ (AC) = B (C A)’ B’ (AC) = (BAC) =ABC Thus, output parity is equal to input parity. As FTM gate preserves the parity values of input and output, FTM gate is a fault tolerant reversible gate.
Output parity of FTC gate is = A’(AB’C) (A’BC) (ACD)’ = (CC) (A’B’) A’B ACD1 = (A’1)B’ A’B (ACD) = AB’ A’B ACD = (A A) AB’ A’BCD = AB’ A’BCD =ABCD
B. Proposed fault tolerant reversible FTC gate C. Proposed fault tolerant reversible FATOC gate In this subsection, a new 4*4 fault tolerant reversible gate namely FTC gate is proposed. The proposed gate and its truth table are shown in Fig. 7 and Table II .respectively. It can be
In this subsection, a new 4*4 fault tolerant reversible gate namely FATOC gate is proposed. The proposed gate and its truth table are shown in Fig. 8 and Table III respectively. It
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required and garbage is two but for the 4:1 multiplexer designing three FTM gates are required and garbage is five.
can be said from the truth table that the input pattern related to a particular output pattern can be uniquely determined and can find out the input-output bit parity.
Figure 9. FTM Gate as 2:1 MUX Figure 8. FATOC Gate
Therefore it can be said that the proposed FATOC gate is a reversible gate. TABLE III.
TRUTH TABLE FOR FATOC GATE
Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
P 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Outputs Q R 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1
S 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1
Figure 10. FTM Gate as 4:1 MUX
IV.
PROPOSED DESIGN FOR FTCOM
This section describes the design of proposed fault tolerant reversible binary comparator (FTCom) in different ways. The subsection IV.A describes realization of FTCom by the proposed multiplexer and the subsection IV.B describes realization of FTCom by the existing fault tolerant gates and proposed gates in several ways. The binary comparator compares two binary numbers (A, B) and determines the result among X (A=B) and Y (AB). The truth table of 1-bit comparator is shown in Table IV.
Lemma 3: Proposed FATOC Gate is a Fault Tolerant Gate. Proof: The input vectors and output vectors of FATOC gate be Iv = {A, B, C, D} and Ov = {A, (AB’C), (A’BC), (ACD)} respectively. From Section II.B, we can know that input parity and output parity have to be same in fault tolerant or parity preserving gate. Accordingly, the input parity of FATOC gate is = ABC D
TABLE IV.
TRUTH TABLE FOR 1 BIT COMPARATOR
Inputs A 0 0 1 1
Output parity of FATOC gate is = A(AB’C) (A’BC) (ACD) = (CC) (AB’) A’B ACD = (AA)B’ A’B CD = B’ A’B CD =ABC D
B 0 1 0 1
X(A=B) 1 0 0 1
Outputs Y(AB). 0 0 1 0
A. Proposed 1 bit FTCom based on fault tolerant reversible multilayer multiplexer of FTM gate The proposed FTM gate can be used to implement a 1-bit comparator as a multiplexer. It is well known that X (A=B) = (AB)’, Y (AB) = AB’.
D. Proposed fault tolerant reversible FTM gate as Multiplexer In this subsection fault tolerant multiplexer has been designed by the proposed fault tolerant reversible FTM gate.The designs of 2:1 multiplexer & 4:1 multiplexer are shown in figure 9 and figure 10 respectively. From figure we can see for the realization of 2:1 multiplexer only one FTM gate is
1) Proposed FTCom based on fault tolerant reversible multilayer 2:1multiplexer of FTM gate To realize 1 bit FTCom by 2:1 fault tolerant multiplexer of FTM gate, three FTM gates and one F2G gate are required
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shown in figure 11 which takes two 1-bit binary numbers as input A and B, and four constant inputs. The circuit produces four garbage outputs and three most wanted outputs that are (A=B) (AB).
In this way we can construct 2 bit binary comparator by 8:1 multiplexer and 16:1 multiplexer.Moreover comparator for N bit operation can be implemented by (22N:1) multiplexer and (22N-1:1 ) multiplexer.
B. Proposed 1bit FTCom based on fault tolerant reversible logic gate The 1 bit comparator can also be realized by using fault tolerant reversible gates. This subsection describes several ways of 1 bit FTCom realization. 1) Proposed FTCom based on fault tolerant reversible FRGgate To realize 1 bit FTCom by existing fault tolerant Fredkin gate, two FRG gates and two F2G gates are required shown in figure 13 which takes two 1-bit binary numbers as input A and B, and four constant inputs. The circuit produces four garbage outputs and three required outputs that are (A=B) (AB).
Figure 11.Realization of FTCOM by 2:1 MUXof FTM gate
2) Proposed FTCom based on fault tolerant reversible multilayer 4:1multiplexer of FTM gate To realize 1 bit FTCom by 4:1 fault tolerant multiplexer of FTM gate, nine FTM gates are required shown in figure 12 which takes two 1-bit binary numbers as input A and B, and twelve constant inputs. The circuit produces eleven garbage outputs and three needed outputs that are (A=B) (AB).
Figure13. Realization of FTCom by FRG gate
2) Proposed FTCom based on fault tolerant reversible MIG gate To realize 1 bit FTCom by existing fault tolerant Modified Islam gate, two MIG gates and one F2G gates are required shown in figure 14 which takes two 1-bit binary numbers as input A and B, and six constant inputs. The circuit produces six garbage outputs and three wanted outputs that are (A=B) (AB).
Figure14. Realization of FTCom by MIG Gate Figure12. Realization of FTCom by 4:1 MUXof FTM gate
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3) Proposed FTCom based on fault tolerant reversible IGgate
6) Proposed FTCom based on proposed fault tolerant reversible FTC gate
To realize 1 bit FTCom by existing fault tolerant Islam gate, one IG gate and one F2G gate are required shown in figure 15 which takes two 1-bit binary numbers as input A and B, and two constant inputs. The circuit produces two garbage outputs and three required outputs that are (A=B) (AB).
To realize 1 bit FTCom by proposed fault tolerant FTC gate, one FTC gate is needed shown in figure 18 which takes two 1bit binary numbers as input A and B, and one constant input. The circuit produces one garbage outputs and three wanted outputs that are (A=B) (AB).
Figure15. Realization of FTCom by IG gate
Figure18. Realization of FTCom by FTC gate
4) Proposed FTCom based on fault tolerant reversible NFTgate To realize 1 bit FTCom by existing fault tolerant New Fault Tolerant gate, two NFT gates and two F2G gates are required shown in figure 16 which takes two 1-bit binary numbers as input A and B, and four constant inputs. The circuit produces five garbage outputs and three wanted outputs that are (A=B) (AB).
C. Proposed 2bit FTCom based on proposed fault tolerant reversible logic gate The 1-bit comparator compares two 2-bit of two binary numbers (A=A1A0, B=B1B0) and determines the result among X (A=B) and Y (AB). The truth table of 2-bit comparator is shown in Table V. TABLE V.
TRUTH TABLE FOR 2 BIT COMPARATOR
Inputs A(A1A0) 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11
Figure16. Proposed FTCom based on fault tolerant reversible NFT Gate
5) Proposed FTCom based on proposed fault tolerant reversible FATOC gate To realize 1 bit FTCom by proposed fault tolerant FATOC gate, one FATOC gate and one F2G gate are required shown in figure 17 which takes two 1-bit binary numbers as input A and B, and one constant input. The circuit produces one garbage output and three required desired outputs that are (A=B) (AB).
B(B1B0) 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
X(A=B) 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
Outputs Y(AB). 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
To realize 2 bit FTCom by proposed fault tolerant gate, four FTC gate, one FTM and one F2G gate are required shown in figure 19 which takes two 2-bit binary numbers as input A=A1A0 and B=B1B0 and six constant inputs. The circuit produces ten garbage outputs and three wanted outputs that are (A=B) (AB). Figure17. Realization of FTCom by FATOC gate
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TABLE VII. COMPARISON OF 1 BIT FTCOM BY FAULT TOLERANT REVERSIBLE GATE Sl no
proposed1-bit FTCom (using FRG gate) proposed 1-bit FTCom(using MIG gate) proposed 1-bit FTCom (using NFT gate) proposed 1-bit FTCom (using IG gate) Proposed 1-bit FTCom (using proposed FATOC gate) Proposed 1-bit FTCom (using proposed FTC gate) Existing 1-bit FTCom (using AG gate) [15]
Furthermore N-bit FTCom can also be possible to design by these proposed fault tolerant gates. COMPARISON RESULTS
In this section comparison results are shown. Table VI shows that we can construct any bit of fault tolerant comparator (FTCom) by the fault tolerant multiplexer which is based on the proposed fault tolerant reversible FTM gate. The required multiplexer, number of gates, garbage output and hardware complexity is given to design 1bit, 2 bit and N bit FTCom. Also Table VII shows the comparison among the various proposed 1-bit FTCom and the existing 1-bit FTCom.
TABLE VIII.
Sl no 1bit F T C o m 2bit F T C o m Nbit F T C o m
COMPARISON OF FTCOM BY MULTIPLEXER OF FTM GATE
Required Multiplexer 2:1 Multiplexer
Gate Count
Garbage
4
4
4:1 Multiplexer
9
11
9(2 α+4ß+δ)
8:1 Multiplexer
23
28
21(2 α+4ß+ δ)+4 α
16:1 Multiplexer
45
53
53(2 α+4ß+δ)
3(22N+2N2)+1
3(22N-1) (2 α+4ß+ δ)+N2α
3(22N+2N3)+2
{3(22N-1)+N-1)}(2 α+4ß+δ)
22N-1:1 Multiplexer 22N:1 Multiplexer
3(22N1)+N 3(22N1)+N-1
Existing 2-bit FTCom [15] Proposed 2-bit FTCom (using proposed Fault tolerant gate)
Hardware Complexity 3(2
Garb age
Hardware Complexity
4
4
4
8α+8ß+2δ
3
6
6
8α+4ß+2δ
4
4
5
8α+6ß+2δ
2
2
2
6α+3ß+δ
2
1
1
6α+2ß+2δ
1
1
1
4α+2ß+3δ
1
3
2
7α+4ß+4δ
COMPARISON OF 2 BIT FTCOM BY FAULT TOLERANT REVERSIBLE GATE
Sl No TABLE VI.
consta nt input
In this paper various designing of 1 bit FTCom are represented by the existing fault tolerant reversible gates FRG, MIG, NFT, IG and also by our proposed fault tolerant reversible gates FTC, FATOC and FTM. In terms of Gate count, constant input, garbage output and hardware complexity all these designs are given in Table VII. Furthermore it can be seen that our proposed 1 bit FTCom using proposed fault tolerant gate FTC and FATOC are most efficient with other designs with respect to gate count, constant input, garbage output and hardware complexity. Also a comparison of 2-bit FTCom is shown in Table VIII. It can be seen that our proposed 2-bit FTCom is more efficient with respect to the existing one.
Figure19. Realization of 2-bit FTCom by FTC & FTM gate
V.
Gate Cou nt
α+4ß+δ)+2 α
Gate Count
Const ant Input
Garb age
Hardware Complexity
6
11
10
20α+14ß+7δ
6
6
10
22α+16ß+14δ
A chart is given below to describe the required number of gates, constant input, garbage output for 1 bit FTCom by FRG, MIG, NFT, IG, FTC and FATOC gates.
6 5 4 3 2 1 0
220
Gate Count Constant Input Garbage
FRG
NFT
MIG
IG
FATOC
FTC
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VI.
[6]
CONCLUSION
This works represents towards the design of Fault Tolerent Binary Comparator by Parity Preserving Reversible Logic based Multi Layer Multiplexer. The design is very useful for the future computation in the field of very low power application zone such as digital circuits along with quantum computers. It is shown that the proposed circuit is highly optimized with respect to number of reversible logic gates, constant input, number of garbage and hardware complexity. The design methods are definitely useful for the construction of future computer and other computational structures in nanometric fashion. Synthesis of these designs and QCA implementation of these designs may be the future scope of work.
[7]
[8]
[9]
[10]
[11] [12]
ACKNOWLEDGMENT The authors wish to thank the CSE and ECE Department of Murshidabad College of Engineering and Technology, Berhampore, for supporting this work
[13]
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