VLSI Design and Implementation of Efficient Software Defined ... - Core

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ScienceDirect Procedia Computer Science 58 (2015) 414 – 421

Second International Symposium on Computer Vision and the Internet (VisionNet’15)

VLSI Design and Implementation of Efficient Software Defined Radio using Optimized Quadrature Direct Digital Frequency Synthesizer on FPGA Vishnu Ga, Karthik Pb , Fathima Jabeenc * 0F

a P.G. Student, Department of Electronics and Communications Engineering, KSSEM, Bangalore b Associate Professor, Department of Electronics and Communications Engineering, KSSEM, Bangalore c Professor & HOD, Department of Electronics and Communications Engineering, KSSEM, Bangalore

Abstract This paper presents an framework for efficient design and implementation of software defined radio (SDR) on FPGA platform using optimized Quadrature Direct Digital Frequency Synthesizer (QDDFS). An basic SDR System consists of RF Antennas, Analog to Digital converter (ADC), Digital to Analog converter (DAC), Filters and processing units. Reconfigurability and optimization can be achieved in the processing unit to a maximum extent. Processing unit of the SDR System is designed and implemented completely in this paper. The important parts of the SDR system designed are 16-Quadrature Amplitude Modulation (16-QAM), Orthogonal Frequency Division Multiplexing (OFDM) (16 point Fast Fourier Transforms (FFT), Inverse Fast Fourier Transform (IFFT) and Cyclic Prefix) and QDDFS. QDDFS generates the sine and cosine values in digital domain and it is optimized in terms of the device utilization with efficient performance and the functionality of rapidly hopping between the different frequencies, faster response time are also achieved. Both in transmitter and receiver, the same QDDFS architecture is used. The Input to the SDR system designed is Text Data which is fed and retrieved in the ASCII Format. © byby Elsevier B.V.B.V. This is an open access article under the CC BY-NC-ND license © 2015 2015The TheAuthors. Authors.Published Published Elsevier (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of organizing committee of the Second International Symposium on Computer Vision and the Peer-review under responsibility of organizing committee of the Second International Symposium on Computer Vision and the Internet Internet(VisionNet’15). (VisionNet’15) Keywords: SDR; QDDFS; 16-QAM; FFT; FPGA;

* Vishnu G. E-mail address:[email protected]

1877-0509 © 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of organizing committee of the Second International Symposium on Computer Vision and the Internet (VisionNet’15) doi:10.1016/j.procs.2015.08.051

G. Vishnu et al. / Procedia Computer Science 58 (2015) 414 – 421

1. Introduction Reconfigurabilty is one of the important parameter in the radio communication systems, one of the methods to achieve it is through Software Defined Radio (SDR) technology. In SDR technology, during runtime hardware is made reconfigurable by adjusting the system parameters by using software. SDR is a transceiver system in which Quadrature Direct Digital Frequency Synthesizer (QDDFS) is an important block which generates the sine and cosine signals in digital format which are essential for Digital Up Converters (DUC) & Digital Down Converters (DDC). DDC and DUC are used in Software Defined Radios (SDRs). Frequency Control Word (FCW) is used to control the QDDFS to synthesize the signals at the required frequency. QDDFS is used because it offers several advantages like very fine tuning resolution and fast switching speed. To optimize the SDR in terms of area and time, many methods like genetic algorithms, genetic programming 19, 20, 21, 22. Some of the techniques to design the DDFS are Coordinate Rotation Digital Computer (CORDIC) Technique, Lookup Table Technique. While 2, 3, 4 have used Lookup Table based approaches, CORDIC based approaches have been used in 5, 6, 7 for the generation of Sine and Cosine. Both LUT and CORDIC technique can be used to design the DDFS 8. Lookup Table based designs require large memory and CORDIC based techniques are time inefficient as it is a iterative algorithm. Using Trigonometric identities as references, sine and cosine values can be computed 9 in which the architecture requires 4 Multiplier and 2 Adders. An simplified architecture has been proposed in 25, which uses only 2 Adders and 2 multipliers to generate the sine and cosine values. QDDFS Architecture proposed in 25 is the most time and area efficient architecture compared to the existing architecture, hence it is used in designing the proposed SDR system. The rest of the paper is organized as follows; Section 2 briefly describes the overall framework and the functionality of each block of the framework proposed, Section 3 deals with detailed discussion of the implementation of the blocks and the QDDFS and Section 4 discusses about the simulation and hardware synthesis results and finally Section 5 concludes the paper. 2. Methodology Software Defined Radio (SDR) architecture is designed using the Verilog HDL and implemented on Field Programmable Gate Array (FPGA) using Xilinx and ModelSim Software Tools. SDR is a Transceiver Architecture which consists of both transmitter and receiver. The Input to the transmitter is a digital data i.e. the ASCII value of the Text and at the receiver part, the digital data is retrieved back. In transmitter, the text is encoded using the16QAM modulator which is followed by 8-point IFFT which converts the digital data into time domain. Same DDFS architecture is used both transmitter and receiver. The receiver basically performs the inverse of the transmitter. The FFT converts the digital data into frequency domain data. Demodulation converts the information back to the baseband data. The overall block diagram of the system has been shown in Fig. 1.

Fig. 1 Block Diagram of Software Defined Radio

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3. Block Description and Implementation 3.1. Modulator and Demodulator The input to the proposed SDR system is text which is given to the system in form of ASCII values i.e. 8 bits for each letter. In a single instance, only 4 bit data can be given to the system and at the receiver side same 4 bit data is retrieved back. In this work, 16-QAM (Quadrature Amplitude Modulation) used. It converts or encodes or modulates the 4 bit input into 16 bit output. 16-QAM is used in this work because of its low bit-error rate and the design of the 16-QAM is done based on the Table 1 shown below. Table 1 is obtained using the standard gray code and k-map for encoding the data.

16-QAM Input (Symbol)

Table 1. 16-QAM Mapping Sequence 16-QAM Input (Binary Representation) Modulation Angles

16-QAM Output (Mapped Sequence)

0

0000

225°

10 + 10j

1

0001

202.5°

20 + 10j

2

0010

135°

40 + 10j

3

0011

157.5°

30 + 10j

4

0100

247.5°

10 + 20j

5

0101

225°

20 + 20j

6

0110

112.5°

40 + 20j

7

0111

135°

30 + 20j

8

1000

315°

10 + 40j

9

1001

337.5°

20 + 40j

10

1010

45°

40 + 40j

11

1011

22.5°

30 + 40j

12

1100

292.5°

10 + 30j

13

1101

315°

20 + 30j

14

1110

67.5°

40 + 30j

15

1111

45°

30 + 30j

3.2. Zero Padding & Symbol Generator In this block, the modulator output which is of 16 bit is converted to 128 bit in order to increase the range of the Fast Fourier transform. i.e. each point in 8-Point FFT and IFFT will be of 16 bits. so the range of each point becomes from 0 to 216 (65536). Symbol Generator converts the 16 bit QAM output to 64 bit data using shift and OR operation. The 16 bit data is shifted to left by 16 bits and OR operation is done to it with the original 16 bit data. This operation is repeated for 3 times in order to get the 64 bit data. Zero Padding converts the 64 bit data from symbol generator to 128 bit data using concatenation process. In this block 32 bit Zero's are concatenated on both sides of the 64 bit data. so the input to the IFFT is a 128 bit data. 3.3. Fast Fourier Transform and Inverse Fast Fourier Transform IFFT and FFT is required to design OFDM, therefore in transmitter, an Fixed 8-point Inverse Fast Fourier Transform (IFFT) is used to convert the 128 bit data to time domain. It is designed based Cooley-Tukey Algorithm. The block diagram of the IFFT is as shown in Fig. 2.


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Fig. 2 Block Diagram of the 8-point IFFT Inverse Fast Fourier Transformation is performed using two IFFT modules. The input to the modules is from the zero padding 128 bit real and imaginary output. Each module gives both real and imaginary outputs. The final IFFT outputs are obtained by subtracting the real part of one module with the imaginary part of the other module. In Receiver, Fast Fourier Transform (FFT) is used to convert the time domain data back to frequency domain. This transformation is done using two FFT modules and two adders are used to obtain the frequency domain data as shown in the Fig. 3.

Fig. 3 Block Diagram of the 8-point FFT FFT & IFFT Module is designed based on the Cooley Tukey Algorithm 24. Twiddle factor used in the 8-point IFFT is WN n = e(-j2πn/N)

(1)

The Butterfly diagram of the designed IFFT is as shown in Fig. 4,

Fig. 4 8-point Radix-2 Butterfly Diagram

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3.4. Cyclic Prefix and Inverse Cyclic Prefix To prevent the data loss in channel, cyclic prefix is used at transmitter section. both the real and imaginary data from the IFFT is combined and lower order 48 bits of imaginary data from IFFT is combined with it. The output of the cyclic prefix is 304 bits data which are given to QDDFS as 16 bit input at a time using shifting operation. The 16 bit data given to the QDDFS are MSB bits. At the receiver, inverse cyclic prefix is used to perform the inverse operation of that in transmitter i.e. 16 bit data is converted back to 128 bit imaginary and real data. 3.5. Quadrature Direct Digital Frequency Synthesizer Architecture The Architecture Quadrature Direct Digital Frequency Synthesizer (QDDFS) is as shown in Fig. 5.

Fig. 5 Architecture for QDDFS The architecture used in this paper utilizes two adders, two multiplexers, two multipliers and two registers 25. When Sel is high, the Yi and Xi are fed to the register. initially the sel is made high and on the next positive edge of clk, the Yi and Xi values are used to compute the values of Sine and Cosine. After the first clock cycle, sel is made 0 and the multiplexers acts as a wire till end. The previous value of Cosine is multiplied by Δθ and added with the previous value of Sine to generate the current value of Sine, Yc. Similarly, the previous value of Sine, Yp is multiplied by Δθ and subtracted from the previous value of Cosine, Xp to generate the current value of Cosine, Xc. (2) (3) The above equations represents the DDFS and the frequency control word Δθ is given by equation below, (4) where, fclk is system clock frequency and f is the desired frequency and Yi and Xi are made 0 and 1.


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4. Results And Discussion In this section, the simulation result of SDR system and hardware synthesis result of DDFS is discussed in this section.

Fig. 6 Transmitter Simulation Result for Text Input 'S' (01010011) Fig. 6 represents the simulation result of SDR transmitter for input (0101), the 16-bit modulation output obtained are Real (r_out): 0000000000001010 and Imaginary (i_out): 0000000000011110, the 304 bit DUC output (ofdm_out) obtained is (1, 0, -8, 5, -7, 0, 5, 0, -3, 0, 1, 15, -10, 0, 3, 0, 1, 0, -8).

Fig. 7 Receiver Simulation Result for Text Input 'S' (01010011)

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Fig. 7 represents the simulation result of SDR Receiver. 304 bit DDC output is given as input to the receiver (1, 0, 8, 5, -7, 0, 5, 0, -3, 0, 1, 15, -10, 0, 3, 0, 1, 0, -8). 4-bit Receiver Output (ofdm_op) obtained is (0101) which is the given input to the transmitter. For the Text input 'S', Sin is given as (0101) & (0011), the 16-bit modulation output obtained are Real (r_out): 0000000000001010 & 0000000000011110 and Imaginary (i_out): 0000000000011110 & 0000000000101000, the 304 bit DUC output (ofdm_out) obtained is (1, 0, -8, 5, -7, 0, 5, 0, -3, 0, 1, 15, -10, 0, 3, 0, 1, 0, -8) & (-2, 0, -8, 15, 14, 0, 7, 0, -3, 0, -4, 20, -16, 0, 6, 0, -2, 0, -8) respectively. The 304 bit DUC/DDC output is given as input to the receiver (1, 0, -8, 5, -7, 0, 5, 0, -3, 0, 1, 15, -10, 0, 3, 0, 1, 0, -8) & (-2, 0, -8, 15, -14, 0, 7, 0, -3, 0, -4, 20, -16, 0, 6, 0, -2, 0, -8). 4-bit Receiver Output (ofdm_op) obtained is (0101) & (0011) respectively which represents the Text 'S' which is obtained back from the Receiver. Hardware Analysis and Synthesis Result of the DDFS is as shown below. The target device is chosen as Xilinx Spartan 3E XC3S50 (-5TQ144) family and the device utilization is compared with the design shown in 5 where the time and area efficient collapsed modified CORDIC based DDFS is used.

Logic Utilization

Table 2. Device Utilization of DDFS DDFS Designed DDFS used in [5]

Slices

280

570

Slice Flip-Flops

32

221

4-Input LUTS

537

1061

From the Table 2 it is evident that the trigonometric identity based DDFS is optimized than the Modified CORDIC based DDFS Architectures 5.

Logic Utilization

Maximum Delay

Table 3. Delay Analysis of the SDR CORTEX A9 Xilinx Spartan III XC3S50 (-5TQ144) Xenomai O.S

Linux O.S

0.895 ms

7.545 ms

8.008 ns

From the Table 3, it is evident that the maximum delay time required for obtaining the output is very less in the SDR designed in this project on FPGA Platform compared to the SDR designed in ARM CORTEX-A9 Platform on different operating systems like Xenomai and Linux operating systems 12. Xilinx Spartan III XC3S50 (-5TQ144) is FPGA Platform considered for timing Analysis. The Minimum Time period taken for the arrival of input before clock is 7.784 ns and the maximum time taken to obtain the output after the clock is 8.008 ns. The maximum operating frequency of the designed SDR system in the mentioned target device is 16.105 MHz i.e. the minimum time period of the SDR System is 62.092 ns. 5. Conclusion In this paper, an simplified QDDFS Architecture is presented which provides optimization in terms of complexity, time and space. It requires extremely less memory i.e. only two 32 registers. Fine phase and frequency resolution is also maintained with reducing the device utilization as the architecture utilizes only two adders, two multiplexers, two multipliers and two registers. This paper also presents an efficient SDR using the Optimized QDDFS which can rapidly hop between the frequencies. The proposed framework consumes lesser silicon area and faster responsive and is realizable on FPGA as the memory required is less and the architecture of QDDFS is simple. The future scope


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of the work is design the SDR to support wider frequency range, complex modulation techniques and to work at higher clock rate. 6. References [1] [2] [3] [4] [5] [6] [7]

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