Impact of VLSI Design Techniques on Implementation

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Impact of VLSI Design Techniques on Implementation of Parallel Prefix Adders Kunjan D. Shinde(&), K. Amit Kumar(&), and C. N. Shilpa Department of Electronics and Communication Engineering, PESITM, Shivamogga, India [email protected], [email protected], [email protected]

Abstract. Adder in general is a digital block used to perform addition operation of given data and generates the results as sum and carry_out. This block is used in various platform for addition/subtraction/multiplication applications. There are several approaches to design and verify the functionality of the adder, based on which they may be classified on type of data it uses for addition, precession of the adder, algorithm used to implementation the adder structure. In this paper we are concentrating on the algorithm/method used to implement an adder structure while keeping the precision constant and considering the binary data for verification of the design. Use of conventional adders like ripple carry adder, carry save adder and carry look ahead adder are not used/implemented for industry and research applications, on the other hand the parallel prefix adders became popular with their fast carry generation network. The presented work gives a detailed analysis on the impact of various VLSI Design techniques like CMOS, GDI, PTL, and modified GDI techniques to implement the parallel prefix adders like Kogge Stone Adder (KSA), Brent Kung Adder (BKA) and Lander Fischer Adder with precession of 4bits, 8bits and 16bits. To measure the performance (in terms of Number of Transistors required, Power Consumed, and Speed) and verify the functionality of these adders we have used Cadence Design Suite 6.1.6 tool with GPDK 180 nm MOS technology, from the results and comparative analysis we can observe that the CMOS technique consumes less power and more transistors to implement a logic, whereas the GDI technique consumes slightly more power than CMOS and implements the logic with less number of transistors. In this paper we also present a simple approach to get the best of both techniques by new technique as modified GDI technique, using this we have optimized the design both in terms of power and transistors used. Keywords: VLSI design techniques  Parallel prefix adders Kogge Stone Adder  Brent Kung Adder  Ladner Fischer Adder CMOS design  GDI design  Modified-GDI design  CADENCE 180 nm technology  Area  Power  Delay

1 Introduction Addition is the most common arithmetic operation used in various digital blocks and binary adders are widely used to perform operations like addition/Subtraction/ Multiplication and in ALU (Arithmetic and Logical Unit). As the adder is most © Springer Nature Singapore Pte Ltd. 2018 I. Zelinka et al. (Eds.): ICSCS 2018, CCIS 837, pp. 473–482, 2018. https://doi.org/10.1007/978-981-13-1936-5_50

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fundamental block in digital system the performance adder block plays a vital role in the design of other digital systems and hence the performance of the adders has to be improved. In VLSI system, the requirements of adder should be fast in performing the operation, low power consumption, and less area. The performance in digital system also depends on the algorithm/architecture used to implement adder. The major issue in the binary addition is propagation delay in carry generation stage, as the number of input stages increases the propagation delay also increases with reduction in the speed of operation. To overcome this problem, Parallel Prefix Adders (PPAs) are used and as they are effective, reliable and fast, hence they are better suited in the modern digital systems. In this paper we have consider the three parallel prefix adder, which are Kogge Stone Adder, Brent Kung Adder and Lander Fischer Adder. The design and implementation of parallel prefix adders are performed using VLSI Techniques like CMOS design, GDI design and Modified-GDI design. Digital circuit design is an important phase, as most of the processing in todays chip are digital and the circuit that performs this operations should consume low power, occupy less area and compute in small delay. These are the main performance parameters and issues in the VLSI design and implementation. Several VLSI design techniques are proposed to implement digital circuits, among those the popular and most often used is CMOS technique, when compared with GDI design style, the GDI technique consumes less number of transistors for designing the digital circuits and consume more power when compared to CMOS technique. Some issues with GDI design style may be driving multiple load and it suffer from the swing degradation at the output signals, limitations of this design techniques are overcome by introducing the new design technique called as modified GDI technique. The modified GDI technique for a given digital circuit can be performed by drawing the given circuit in the form of layers i.e. vertical and horizontal layers, without altering the functionality of the circuit the each odd layer is designed using CMOS technique and the remaining even layers are designed using GDI technique, and at the last stage the design is made using CMOS technique in order to retain the full swing output. With such a combination of both the techniques used as an intermediate and optimal solution for digital circuit which provides good results in terms of accuracy in output, speed in computation and low power consumption [5, 7–9].

2 Literature Survey The following are some papers that we have referred to design and implementation of parallel prefix adders using different design techniques. In [1], the authors have designed and compared various 8-bit different adders using Verilog HDL coding for conventional adder and parallel prefix adder. From [2], the basic design of parallel prefix adders like Kogge Stone Adder and Brent Kung Adder have been explained using different design techniques. In [3], a brief introduction about carry tree structure and working principle of KSA, BKA and LFA adders have been explained, a comparative analysis is coated based on area, delay and power consumption. In [4] the

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authors have focused on the design of high speed carry select adder (CSL) for replacing ripple carry adders (RCA) structure in conventional design of Ladner-Fischer Parallel Prefix Adders (LFA), with this replacement the authors have reduced the delay in generating the result. In [5], the GDI technique is applied for digital circuits and its performance is measured. In [6], the authors have implemented various parallel prefix adders and created a comparative analysis. In [7, 9] the authors have verified the functionality of the parallel prefix adders on various platforms like FPGA. and In [8], a modified GDI logic is used to design the system and verified its behaviors.

3 Design of Parallel Prefix Adder The Parallel Prefix Adder has advanced architecture over the Carry Look ahead Adder (CLA) which is due to the Carry Network of the adder. In VLSI implementations, parallel-prefix adders are known to have the best performance, and widely used in industry for high performance Arithmetic Logic Units digital circuit operation. Compared to the other conventional adders the PPA performs high speed addition operation achieved with the help of its advanced carry generation network, reduce the delay and power consumption. In Parallel Prefix Adder, the execution of partial and final result is performed in parallel and the current stage outcome of the execution is dependent upon the initial input bits at that stage [3]. The following is the general structure of Parallel Prefix adder which involves three steps in process to generate the final results; the steps are explained with reference to Kogge Stone Adder architecture for better understanding (Fig. 1).

Fig. 1. Architecture of parallel prefix adder

A. Pre-Processing Block: The initial stage of the Parallel Prefix Adder is Pre-Processing, two signals are produced in this stage which are termed as generate signal (Gi) and the propagate

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signal (Pi). The generated and propagate signal are computed for every ith stage of the input signal and its operation is represented using following equations. Pi = Ai XOR Bi

ð1Þ

Gi = Ai AND Bi

ð2Þ

B. Carry Generation Block: Carry generation stage is a most important block in Parallel Prefix Adder, as the carries are computed before the final result is available using a carry graph. Each adder has different carry graph and based on this the carries are computed. The carry graph consists of two components known as Black Cell and Gray Cell. Black Cell is used to produce the Generated signal and Propagated signal, needed to the calculation of the next stage. Gray Cell is used to produce only Generated signal and these signals are produced based on the earlier inputs received [1]. i. Black Cell: The black cell operator receives two set of generate and propagate signals (Gi, Pi) and (Gj, Pj) compute one set of generate and propagate signals (G, P). G = Gi OR ðPi AND PjÞ

ð3Þ

P = Pi AND Pj

ð4Þ

ii. Gray Cell: The Gray operator receives two set of generate and propagate signals (Gi, Pi) and (Gj, Pj) compute one set of generate signals (G). G = Gi OR ðPi AND PjÞ

ð5Þ

C. Post Processing Block: This is the final stage of the adder; Sum and Carry are the final outcome of the adder. Si = Pi XOR Ci  1

ð6Þ

4 Various Parallel Prefix Adder Architectures The general structure of the parallel prefix adder is understood from the Sect. 3, these Parallel prefix adders differ from each other is by the method of generating carry from the carry generation stage of the adders, The following are the adders we have considered for analysis.

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A. Kogge Stone Adders: The Kogge Stone Adder is one of the most important Parallel Prefix Adders. It generates the carry signal in O (Log2 N) time. This adder is widely used in the industry and considered as the fastest adder design. Carries are generated fast by computing them in parallel, speed of operation is very high due to the low depth of node and operation done in parallel and main important factor is the outcome of the adder is depend upon the initial inputs. Figure 2 gives the schematic of KSA [1].

Fig. 2. Carry generation network of KSA

B. Brent Kung Adder: Figure 3 shows the schematic of BKA. It is one of `the Parallel prefix adder’s forms of the carry look ached adder. BKA prefix adder prefix tree is a bit complex to build the design because it has the most logic levels and it have a gate level depth of O(log2n). Construction of design consumed less number of transistor count and it takes less area and speed of operation compare to other prefix adders. BKA structure reduced the delay without compromising the power performance of adder [6].

Fig. 3. Carry generation network of BKA

C. Ladner Fischer Adder: This prefix tree structure shown in Fig. 4. The structure has the minimum logic dept and the number of logic level of (log2n) is always the minimum in this scheme for an n-bit adder. Limits performance of the structure because of complex area by increasing the delay and consumed more power due to large drive cells [2–4].

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Fig. 4. Carry generation network of LFA

5 Results and Discussion The implementation and functional verification of all the parallel prefix is performed on the Cadence Design Suite 6.1.6 version for design and simulation using Analog Design Environment (ADE), GPDK 180 nm technology is used for designing digital blocks using n-MOS and p-MOS transistor. D. Simulation Results The following are the simulation results of the Parallel Prefix adder used in this paper. The simulation results with schematic are shown only for adders designed using 16bit precession, the schematic and simulation of 4bit and 8bit precession is not show in this paper (Figs. 5, 6, 7, 8, 9, 10, 11, 12 and 13).

Fig. 5. Schematic and simulation of 16bit KSA using CMOS design.

Fig. 6. Schematic and simulation of 16bit KSA using GDI design.

Impact of VLSI Design Techniques

Fig. 7. Schematic and simulation of 16bit KSA using m-GDI design.

Fig. 8. Schematic and simulation of 16bit BKA using CMOS design.

Fig. 9. Schematic and simulation of 16bit BKA using GDI design.

Fig. 10. Schematic and simulation of 16bit BKA using m-GDI design.

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Fig. 11. Schematic and simulation of 16bit LFA using CMOS design.

Fig. 12. Schematic and simulation of 16bit LFA using GDI design.

Fig. 13. Schematic and simulation of 16bit LFA using m-GDI design.

E. Comparative Analysis The comparative analysis of various adders with 4bit, 8bit and 16 bit precession are shown and the results obtained are tabulated for comparison in Table 1. The comparative analysis in Table 1 gives the performance analysis of parallel prefix adder like KSA, BKA and LFA adder with precision of 4bit, 8bit, and 16bit. The performance metric consist of delay, Power and number of transistor used to design the adder. For better analysis and visual representation, a bar graph is plotted for transistor used and delay of various adders. From the comparative analysis it is clear that, the number of transistor required to design a parallel prefix adder using GDI design style is about 30% of transistors required to design the same adder using CMOS design style and 60% of transistor are required for GDI design style when compared to modified GDI design style. Power consumed by modified GDI design is higher than the GDI and CMOS design style, if the power is major issue and prime focus on selecting adder for application then CMOS design is the best choice. When compared with delay associated with different design

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Table 1. Comparative analysis of parallel prefix adder

CMOS Design Style GDI Design Style M-GDI Design Style CMOS Design Style GDI Design Style M-GDI Design Style CMOS Design Style GDI Design Style M-GDI Design Style

Kogge Stone Adder

Brunt Kung Adder

Lander Fisher Adder

4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit 4bit 8bit 16bit

Delay in s 41.43E-9 71.66E-9 161.1E-9 90.95E-9 83.82E-9 181.0E-9 92.05E-9 83.82E-9 192.3E-9 41.67E-9 81.43E-9 161.4E-9 42.67E-9 82.59E-9 162.8E-9 52.73E-9 93.33E-9 173.4E-9 41.32E-9 81.43E-9 161.4E-9 42.15E-9 82.58E-9 162.4E-9 53.75E-9 89.49E-9 172.7E-9

Power in W 1.35E-5 2.7E-7 8.95E-9 3.36E-7 3.99E-7 8.95E-9 0.0010520 0.0010870 0.0001083 3.5E-7 4.746e-7 5.71E-7 1.05E-7 1.30e-7 1.54E-7 0.0010870 0.0004173 0.0010856 4.66E-9 3.675e-7 5.54E-7 1.97E-9 1.274e-7 1.23E-7 7.47E-9 0.000568 0.0011088

Transistors 240 570 1362 68 190 454 74 248 772 192 414 804 64 122 268 82 212 388 174 414 756 100 122 252 62 246 410

styles, CMOS design style produces fast results (less delay in generating result) while consume more number of transistors. Note: In results and comparative analysis, we have performed simulation for different types of adder like Kogge Stone Adder, Brunt Kung Adder and Lander Fisher Adder. We are not comparing the performance of the various adder architecture, but we are

1500

KSA CMOS KSA GDI KSA m-GDI

1000

BKA CMOS BKA GDI BKA m-GDI

500

LFA CMOS LFA GDI

0

LFA m-GDI

4bit

8bit

16bit

Fig. 14. Transistor count in VLSI technology for various parallel prefix adders

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200 100 0 4bit

8bit

16bit

KSA CMOS KSA GDI KSA m-GDI BKA CMOS BKA GDI BKA m-GDI LFA CMOS LFA GDI LFA m-GDI

Fig. 15. Delay in ns versus VLSI technology for various parallel prefix adders

trying to measure the impact of designing the adder using different design style on various adders with existing architectures (Figs. 14 and 15).

6 Conclusion With the presented work in this paper, the CMOS design style uses more number of transistor while generating faster results and consuming less power, GDI design style uses about 30% of transistors compared to CMOS style and does not provides a full swing output, using the modified GDI logic the adders consume moderate number of transistors with full swing output and generates results with an increased delay.

References 1. Shinde, K.D., Jayashree, C.N.: Modeling, design and performance analysis of various 8- bit adders for embedded approach. In: Second International Conference on ELSEVIRE, ERCIC 2014 (2014). ISBN 9789351072621 2. Brent, R.P., Kung, H.T.: A regular layout for parallel adders. IEEE Trans. C-31(3), 260–264 (1982) 3. Naganathan, V.: A comparative analysis of parallel prefix adders in 32 nm and 45 nm static CMOS technology. The University of Texas at Austin (2015) 4. Chakali, P., Patnala, M.K.: Design of high speed ladner-fischer based carry select adders. Int. J. Soft Comput. Eng. (IJSCE) 3(1), 173–176 (2013). ISSN 2231-2307 5. Verma, P., Manchanda, R.: Review of various GDI technique for low power digital circuits. Int. J. Emerg. Technol. Adv. Eng. 4(2) (2014) 6. Talsania, M., John, E.: A comparative analysis of parallel prefix adders. Department of Electrical and Computer Engineering, University of Taxas at San Antonio, Tx (2013) 7. Yezerla, S.K., Naik, B.R.: Design and estimation of delay, power and area of parallel prefix adders. In: Proceeding of 2014 RAECS UIET Punjab University, Chandigarh, March 2014 8. Verma, P., Singh, R., Mishra, Y.K.: Modified GD technique - a power efficient method for digital circuit design. IJATES. 10(10) (2013) 9. Hoe, D.H.K., Matinez, C., Vandavalli, S.J.: Design and characterization of parallel prefix adders using FPGA. In: 2011 IEEE Hard South System on System Theory (SSST) (2011)