What's new in LabVIEW RT & FPGA

What’s new in LabVIEW RT & FPGA

Howard

SW + HW

What’s new in LabVIEW 2010!

Improved Performance

Optimizing the LabVIEW Compiler Dataflow Intermediate Representation (DFIR) – High-level representation – Preserves dataflow, parallelism, and execution semantics

Low-Level Virtual Machine (LLVM) – Low-level representation – Sequential – Knowledge of target machine characteristics, instruction sets, alignment, etc.

Block Diagram DFIR

Transforms LabVIEW Intermediate Language LLVM

Transforms Target Machine Code

DFIR Optimizations

Common Subexpression Elimination

Unreachable Code Elimination

LabVIEW Compiler Optimizes Your Code

LabVIEW Compiler Optimizes Your Code

1

Only this portion of the code will execute Because the input is constant, the compiler can determine which code will execute, and remove the unnecessary code

LabVIEW Compiler Optimizes Your Code

2

Sequence Structure is now unnecessary

The Match Pattern primitive will not change from iteration to iteration

LabVIEW Compiler Optimizes Your Code 3

• Decompositions Used • • • •

SubVI Inlining Unreachable Code Elimination Dead Code Elimination Loop Invariant Code Motion

What’s new in LabVIEW 2010!

Environment Enhancements

LabVIEW Idea Exchange

LabVIEW 2010 Idea Exchange Feature Name

LabVIEW 2009

LabVIEW 2010

User PJM_LabVIEW

Default Number of Undo Steps

Altenbach

Local Variable Redesign

Altenbach

String Radix

Falkpl

Wire Labels Growable Merge Error Node

Dany.

Move Switch Items in the connector pane

tst 8 Mouse Clicks

2 Mouse Clicks

What’s new in Real-Time 2010!

System Configuration Tools

NI Network Browser • Stand-alone application that allows configuration of remote systems without MAX • Included with System Configuration 1.1 distribution and other drivers

Module # of #: Series name

NI Network Browser • Component needed to use Network Browser – LabVIEW RT 10.0 – NI Web-Based Configuration and Monitoring • Can be chosen when installing RT 10.0

Module # of #: Series name

NI Network Browser • Most MAX functions can be done here

Module # of #: Series name

What’s new in Real-Time 2010!

Real-Time Hypervisor 2.0

Hypervisor Introduction Host OS

LabVIEW Real-Time

NI Real-Time Hypervisor

I/O

RAM

CPUs

• Combine RT processing and a GUI on one controller

• Very few support issues to date (RAM limitation fixed)

Linux Now Supported as a Host OS Host OS

LabVIEW Real-Time

or

NI Real-Time Hypervisor

I/O

RAM

CPUs

• Red Hat Enterprise Linux • NI will evaluate other distributions on request

Flexible CPU Core Allocation

Host OS

LabVIEW Real-Time

or

• Assign CPUs to OSs based on detailed cache information

NI Real-Time Hypervisor • Easier installation (no more Standard Mode) I/O

RAM

CPUs

Communicate Between OSs Faster with HighThroughput Shared Memory Host OS

LabVIEW Real-Time

or

NI Real-Time Hypervisor

I/O

RAM

CPUs

LabVIEW FPGA 2010 Feature Overview

IP Integration Node - Directly import Xilinx .xco files or your own VHDL easily

LabVIEW FPGA 2010 Feature Overview

IP Integration Node - Directly import Xilinx .xco files or your own VHDL easily New Compilation Flow - Earlier compilation estimates and build specifications

LabVIEW FPGA 2010 Feature Overview

IP Integration Node - Directly import Xilinx .xco files or your own VHDL easily New Compilation Flow - Earlier compilation estimates and build specifications Cycle-Accurate Simulation - Use ModelSim for cycle-accurate simulation

LabVIEW FPGA 2010 Feature Overview

IP Integration Node - Directly import Xilinx .xco files or your own VHDL easily New Compilation Flow - Earlier compilation estimates and build specifications Cycle-Accurate Simulation - Use ModelSim for cycle-accurate simulation More IP Blocks - New IP for statistics, complex multiplication, and more

LabVIEW FPGA 2010 Feature Overview

IP Integration Node - Directly import Xilinx .xco files or your own VHDL easily New Compilation Flow - Earlier compilation estimates and build specifications Cycle-Accurate Simulation - Use ModelSim for cycle-accurate simulation More IP Blocks - New IP for statistics, complex multiplication, and more Host Improvements – New dynamic reference for host VI reuse

What’s new in FPGA 2010!

IP Integration Node

IP Integration Node Use Core Generator or Custom VHDL

IP Integration Node Use Core Generator or Custom VHDL

Configure IP Integration Node and Generate Simulation Model

IP Integration Node Use Core Generator or Custom VHDL

Configure IP Integration Node and Generate Simulation Model

Use the IP Block Using Standard LabVIEW I/O Interfaces

What’s new in FPGA 2010!

New Compilation Flow

Options for Compiling New High-Performance Cloud (Beta) New Compile Server and Workers

Development PC

Single CPU Compile

On-Site Compile Farm

Cloud Compilation

LabVIEW 2010 Feature

New Compilation Flow - Earlier compilation estimates and build specifications •LabVIEW FPGA Compile Farm Toolkit •LabVIEW FPGA Compile Cloud Service(beta) •Pre-Synthesis Compilation Estimates •Build Specification for FPGA

Compilation Features LabVIEW FPGA Compile Farm Toolkit

Compilation “Smart” Server

LabVIEW FPGA Development Machines

Compilation Workers

New Compilation Server Infrastructure • Compile Farm Installation

• Targeting the Farm in LabVIEW Tools » FPGA Module Options…

Compilation Features LabVIEW FPGA Compile Cloud Service (Beta)

LabVIEW FPGA Development Machines

High-RAM Dedicated Workhorse Computers in the Cloud

Cloud Beta Information

High-RAM Dedicated Workhorse Computers in the Cloud

• Sign up at ni.com/beta • Free during the beta period • There will be a beta community group for support and direct interaction with R&D.

Compilation Features Pre-Synthesis Compilation Estimates

• Course-grain but early • Within one minute of compilation starting • Estimates Slices (LUTs and Registers)

Compilation Features Build Specifications for FPGA

• 每個FPGA VI能夠擁有專 屬的設定檔 • 能夠產生模擬軟體所需 的設定檔案

Compilation Demonstration • Build Specs • Compile Farm • Pre-Synthesis Estimates

What’s new in FPGA 2010!

Cycle Accurate Simulation

Cycle-Accurate Simulation with ModelSim LabVIEW

VHDL

Platform LabVIEW FPGA

Xilinx IP

HDL IP

Simulation Export ModelSim

VHDL

VHDL Generated

Test Bench I/O Nodes Controls/Indicators DMA FIFOs CLIP I/O

VHDL

Build Specification: Simulation Export

What’s new in FPGA 2010!

More IP Blocks

New Native IP Blocks • • • • • • •

Statistics Express VI – Mean, Variance, STD High-Throughput Complex Multiply Basic Elements – Accumulator, Delay, DSP48E Matrix Vector Multiply Dual-Port Memory Read External DRAM Memory I/O CLIP Improvements – Import Wizard

What’s new in FPGA 2010!

Most Improvements

Dynamic Host Reference Reusable Host SubVI

LabVIEW FPGA 2010 Feature Overview

IP Integration Node - Directly import Xilinx .xco files or your own VHDL easily New Compilation Flow - Earlier compilation estimates and build specifications Cycle-Accurate Simulation - Use ModelSim for cycle-accurate simulation More IP Blocks - New IP for statistics, complex multiplication, and more Host Improvements – New dynamic reference for host VI reuse