WHEN TO SWITCH WHICH SWITCH IN A FIVE LEVEL SINGLE PHASE CASCADED INVERTER Martina Calais , Vassilios G. Agelidis , and Michael S. Dymond Australian Cooperative Research Centre for Renewable Energy (ACRE) Centre for Renewable Energy and Sustainable Technologies Australia (CRESTA) School of Electrical and Computer Engineering Curtin University of Technology email:
[email protected]
PowerSearch Ltd
Abstract A five level single phase cascaded inverter consists of two full bridges connected in series on the AC side. Each bridge can create three different voltage levels at its AC output allowing for an overall five level AC output voltage. Due to switch combination redundancies, there are certain degrees of freedom of how to generate the five level AC output voltage. This paper presents and discusses several different cyclic switching methods which minimise the switching frequency, equalise stress on the devices and minimise the ripple on the DC filter capacitors.
I. INTRODUCTION Multilevel inverters synthesize the AC voltage from several different levels of DC voltages. Each additional DC voltage level adds a step to the AC voltage waveform. By switching the DC voltages to the AC output a staircase waveform can be produced which approaches the sinusoidal waveform with minimum harmonic distortion. Compared to a full bridge inverter which can generate two or three level voltage waveforms at its AC output, a multilevel inverter has the following advantages:
If the number of DC bus voltage levels is high, a near-sinusoidal staircase voltage can be generated with only fundamental frequency switching. Fundamental frequency switching minimises switching losses and is particularly suitable for high power high voltage applications such as large induction motor drives or static VAr compensators, where GTOs with limited switching frequencies are applied [1][2][3]. When the number of levels is sufficiently high, harmonic content will be low enough to avoid the need for filters [1]. High voltages on the DC side do not have to be blocked by one switching device only, but a number of switching devices in series (the number of switching devices depends on the chosen multilevel converter topology and the number of levels). Due to the division of the DC bus in several levels of voltages, switching devices in a multilevel inverter can be rated at lower voltages compared to switching devices applied in a full bridge inverter [1][4].
Some multilevel converter topologies such as the flying capacitor multilevel converter and the cascaded multilevel converter provide switch combination redundancies. These redundancies are advantageous in several ways: For example, they can be used for balancing the different voltage levels, for minimising the switching frequency, and for employing each switching device equally, hence avoiding asymmetrical wear and asymmetrical temperature distribution within the converter [5][1]. Fast dynamic response of a multilevel inverter can be achieved by switching “larger” voltage steps to the output. Due to the flexibility arising from the accessibility of different DC potentials, control schemes can be tailored depending on the application of the inverter [5].
Various multilevel topologies, such as the diode clamped, flying capacitor, magnetic coupled or cascaded converters, are known from the technical literature [6][7][1]. In [8] several multilevel topologies have been compared for the implementation in a specific application: A transformerless, single phase, grid connected photovoltaic (PV) system. A five level cascaded inverter has been identified as a suitable solution and as part of a joint research project between the Centre for Renewable Energy and Sustainable Technologies Australia (CRESTA) and PowerSearch Ltd a prototype system is now under development. In this paper two characteristics of the five level cascaded inverter are investigated: Its switch combination redundancies and the accessibility of different DC voltage levels. Due to this flexibility, the operation of the inverter in the grid connected photovoltaic application
v
can be optimised. The paper is organised as follows: First the five level cascaded inverter and its switch combinations are described in section II. Then three different ways of when to switch which switch in the inverter (three different switching sequences) are discussed. First a solution suggested for a high power application presented in [5] will be analysed in section III. Based on this concept, switching sequences for a cascaded inverter implemented in a transformerless, single phase PV system have been developed and are described in section IV. Results of simulations performed using the simulation package PSCAD/EMTDC (Version 2.00) [9][10][11] are included. Section V and VI summarise and conclude the analysis and list the advantages of each of the switching sequences.
E
Fullbridge 1
Da1 Sb1
Db1
E1 Sa2
Da2 Sb2
Db2
Dc1
Sd1
Dd1
Dc2
Sd2
Dd2
E2 Sc2
Fullbridge 2
Fig. 1 Cascaded Five Level Inverter.
IV
VI V
-E
20
10 time (ms)
Fig. 2 Example of the cascaded inverter output voltage. The intervals I - VI indicate the different modes the inverter operates in.
State 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Full bridge 1
E1 E1
012 011 E1 E1 E1 012 011 E1 012 012 011 011 E1 E1
Full bridge 2
022 021 E2 E2 E2 022 021 E2 E2 E2 022 021 022 021 E2 E2
vinv E1 E1 E2 E2 E 1 + E2 E1 E1 E2 E2 E1 E2
0 0 0 0 0 0
Table 1 Inverter states of cascaded five level inverter.
level voltage can look like is shown in Fig. 2. for a control signal frequency of 2 kHz. One period (20 ms for a 50 Hz signal) can be divided into 6 intervals, each representing a different operational mode of the inverter. Although e.g. mode I and mode III are identical with respect to output voltage levels, the mode information is important for the generation of the switching signals and in particular for generating an optimised switching sequence as will be described in section IV. The cascaded inverter as shown in Fig. 1 has 16 inverter states which allow bi-directional current flow and a fixed inverter output voltage. They are listed in Table 1. For E1 = E2 = E the following is valid:
v inv Sc1
II
-2E
The five level cascaded inverter as shown in Fig. 1 consists of two single phase full bridges with 4 switching devices each. Each individual full bridge has 16 possible inverter states. Of these 16 inverter states only 4 inverter states allow bi-directional current flow and a fixed inverter output voltage. Combining two full bridges with their AC side connected in series results in the addition of the individual full bridge output voltages. Since each bridge can create three different voltage levels at its AC output this allows for an overall five level AC output voltage of the cascaded inverter. An example of how this five
III
I
0
II. A FIVE LEVEL SINGLE PHASE CASCADED INVERTER
Sa1
inv
2E
vinv = E , four possible states vinv = 2 E , one possible state vinv = E , four possible states vinv = 2 E , one possible state vinv = 0, six possible states
However, two of the inverter states (states 15 and 16, see Table 1) creating a voltage vinv = 0 across the load, switch a positive voltage from one bridge and a negative voltage from the other bridge resulting in a cancellation of the voltages only if they are identical.
decrease ON
As shown above except for generating the voltages 2E and +2E there are degrees of freedom as how to generate 0, E or E at the inverter output. E or E , each can be generated in four ways, 0 can be generated in 6 ways. Utilising only 5 of the inverter states to generate the five level voltage waveform at the output would not be convenient out of the following reasons [5]:
The semiconductor switching devices would be used in an asymmetrical way, with the result that their thermal problems and wear would be asymmetrical, too. The minimum dead times of the semiconductor switching devices limit the switching frequency of the inverter. However, with the cascaded inverter the degrees of freedom given with the many inverter states can be used to extend the “on times” of the semiconductor devices to as long as possible, thus reducing the problems arising from minimum dead times. This is an advantage especially for high power application where GTO devices with low switching frequency capability are used.
III. A CYCLIC SWITCHING SEQUENCE FOR A HIGH POWER APPLICATION The five level cascaded inverter and its control scheme described in [5] has been implemented in a non conventional high power application: a converter for plasma stabilisation with a peak power of 3.6 MVA. A cyclic switching sequence with the following characteristics is proposed:
a1
b2
a1
b2
c1
d2
c1
d2
OFF
increase
increase
a1
b2
c1
d2
v
= 0 E inv 12 2 (State 3)
v
= -E E inv 1 2 (State 15)
(State 11) v = 0 0 inv 12 22 decrease
a1
b2
c1
d2
=E 0 inv 1 22 (State 1)
How the above objectives are realised is shown in Fig. 3 as an example for the modes I and III. In these modes the inverter voltage when it needs to be increased takes the level E and when it needs to be decreased takes the level 0. The cyclic switching sequence in modes I and III cycles through the states in the following way: 11-3-15-4-14-2-16-1-11-.. (and so forth). Indicated through shaded areas in Fig. 3 are the on-states of the switches a1, b2, c1, and d2, which
c1
d2
inv
=0
11
E 2
decrease
increase
a1
b2
c1
d2
a1
b2
c1
d2
a1
b2
c1
d2
v
=0 0 inv 11 21 (State 14)
decrease v
= E -E inv 1 2 (State 16)
v
=E 0 inv 1 21 (State 2)
Fig. 3 Cyclic switching sequence as described in [5]. Operation in modes I and III.
when switched on contribute to an increase in inverter output voltage. The on-states for the switches a2, b1, c2 and d1 are complementary to the on-states of a1, b2, c1, and d2. IV. CYCLIC SWITCHING SEQUENCES FOR LOW POWER PHOTOVOLTAIC APPLICATIONS Fig. 4 shows the application of the five level single Cascaded Inverter
I1
a1 C 1
1
L inv V inv
I2 C
2
V L
i inv
E1 b2
The turn-on time and turn-off time of each switching device are spaced out as much as possible. As a result the frequency of the voltage pulses at the inverter output is four times higher than the switching frequency of each switch. The states 15 and 16 are used to generate a zero voltage at the inverter output by switching the two DC bus voltages to cancel each other out. The two DC sources are discharged intermittently by changing from one source to the other after every fourth switching instant.
b2
(State 4) v
increase v
a1
Vgrid
c1 2
E2 d2
E 1 I1 I2 E 2
Switching Signals Current Controller
MPPT E 1ref
E 2ref
DC Voltage Controller
^i
ref
i
i inv
ref
Current Reference Value Generation
Vgrid
System Control
Fig. 4 A cascaded inverter for a transformerless single phase low power grid connected photovoltaic system. In the given application the inverter switches are MOSFETs with body diodes which are capable of conducting the full rated current of the MOSFET.
phase cascaded inverter in a transformerless gridconnected PV system. One characteristic of this system which will be discussed in more detail in this section is the necessity for sufficiently high DC bus voltages. Due to the step down nature of the topology and since the system avoids the transformer the sum of the DC
Control signal
a)
The realisation of the above objectives results in a switching sequence as shown in Fig. 5 (again as an
1.5
p.u.
1 0.5 0 -0.5 Gate signal a1 1.5
b)
1 0.5 0 -0.5 Gate signal b2
c)
1.5 1 0.5 0 -0.5 Gate signal c1
d)
1.5 1
p.u.
1. The switching frequency of each switch is minimal. To achieve this, one objective when choosing the switching sequence is to keep switches on as long as possible. 2. Each switch should be stressed in the same way in order to achieve equal losses in each switch and with that an equal temperature distribution. 3. Over one period the amount of power extracted from both arrays should be the same. Both sources should be loaded symmetrically in the case of a PV system. The switching pattern has to take this into account. It is e.g. not possible to only discharge source E1 to generate a voltage level of vinv = E and vinv = E at the output. 4. The ripple in the DC bus capacitors should be minimal since this causes losses and increases cost.
With this optimised switching sequence regarding DC bus voltage ripple (intermittent source discharge) and equalising the loading of each switch (equalising thermal stress over all switches) can be achieved. Simulation results for one positive half cycle show
p.u.
When considering the cascaded inverter for this particular application the above described switching sequence can be further improved. The objective is to find a switching sequence with the following characteristics:
Besides optimising the switching sequence within the modes (I-VI), the switching transitions when changing from one mode to the other can be optimised. The aim is here to avoid high frequency switching, but to leave switches on as long as possible. 6 cases, that is every changeover from one mode to the next, and all possible inverter states have to be considered.
p.u.
bus voltages has to be higher than the grid voltage at all times. Only then power can be transferred from the PV sub-arrays to the grid.
0.5 0 -0.5 Gate signal d2
e)
1.5
p.u.
1
decrease
a1
ON
b2
a1
0.5 0
b2
-0.5
OFF
b2
c1
d2
c1 v
d2
c1
= 0 E inv 12 2 (State 3)
v
f)
d2
=0 0 inv 12 21 (State 12)
6 4.6
a1
b2
c1
d2
A
a1
i inv
increase
increase
3.2 1.8 0.4 -1
v
g)
= 0
0
inv decrease
12 22
a1
b2
(State 11)
v
(State 2)
=E inv 1
0
21
V
v
decrease
a1
600 450 300 150 0 -150 -300
b2
E 266
h)
inv
E 2
1
c1
d2 increase
v
inv
increase
c1
d2
V
264 262 260 258
=E 0 1 22 (State 1)
a1
c1
b2
a1
d2
c1
b2
v
=0
0
inv 11 21 (State 14)
d2
decrease v
=0 0 inv 11 22 (State 13)
v
=0 E inv 11 2 (State 4)
Fig. 5 Optimised cyclic switching sequence for a PV system. Operation in modes I and III.
example for modes I and III). When comparing Figs. 3 and 5 it can be seen that in Fig. 5 the states 15 and 16 are avoided and states 12 and 13 are used instead. Also the two sources are discharged intermittently. The energy is transferred to the AC side by alternating from source E1 to source E2 every second switching instant.
256
time (ms)
10
Fig. 6 Simulation results: Polarised Ramptime ZACE current control method and cyclic switching sequence, Linv =4 mH, C1 C2 600F, iinv =5 A, (a) control signal (fcontrolsignal 10 kHz), (b)-(e) gate signals for switches a1, b2, c1, d2 (see Fig. 4)(fs 2.5 kHz), (f) unfiltered inverter output current iinv , (g) inverter output voltage vinv , (h) DC bus voltages E1 and E2 .
^
=
=
the cyclic switching sequence in conjunction with the Polarised Ramptime Zero Average Current Error (Polarised Ramptime ZACE) control method [12] in Fig. 6. However, as can be seen in Fig. 6, during the mode changes the di/dt may become very small. Due to different temperatures but also due to shading effects
Due to the problem outlined above it is suggested to operate the inverter during the transitions from mode I to mode II, mode II to III, mode IV to V, and mode V to VI as a normal full bridge in a “bipolar” way, switching between zero states and 2E in the positive half wave (as shown in Fig. 8g) or between zero states and 2E for the negative half wave respectively. In the following the transition periods where bipolar operation is necessary will be referred to as “intermediate modes”. Fig. 7 indicates these intermediate modes for 400
E max
I
II
III
voltage (Emin =196 V) are indicated as well as a grid voltage with an amplitude of 340 V. It is unlikely that the voltage difference between the two PV sub-arrays will be that high in practice, a voltage difference of up to 20 V is more realistic. Control signal
a)
1.5
p.u.
1 0.5 0 -0.5 sa1s 1.5
b)
p.u.
1 0.5 0 -0.5 sb2s
c)
1.5
p.u.
1 0.5 0 -0.5 sc1s
d)
1.5
p.u.
1 0.5 0 -0.5 sd2s
e)
1.5
p.u.
1 0.5 0 -0.5
i f)
inv
6
A
4.6 3.2 1.8 0.4 -1
v
V
g)
inv
600 450 300 150 0 -150 -300
E h)
V
it cannot be guaranteed that the two PV sub-array operate at the same DC voltages. In fact it is desirable to operate them individually and to adjust each DC voltage so that each PV sub-array operates in its Maximum Power Point (MPP) in order to minimise mismatch losses. However, operating the two PV sub-arrays at different voltage levels complicates the control. Previously it was discussed that the inverter operates in 6 different modes (see Fig. 2). However, now when considering different PV sub-array operating voltages, at the mode changes between mode I and II, I and III, IV and V, and V and VI control can be lost if one of the PV sub-array voltages is used to determine the mode change. For example, in the case that the PV sub-array with the lower operating voltage is used to determine the mode change from mode I to mode II (instant where E1 = vgrid or E2 = vgrid ), then at the beginning of mode II vgrid = Emin . In order to be able to increase the current through the inductor Linv (see Fig. 4) the voltage across the inductor has to be positive, which is ensured: vL = vinv vgrid = Emin + Emax Emin = Emax . However, to be able to decrease the current the voltage across the inductor has to be negative. Since the PV sub-arrays are discharged intermittently two cases can occur: vL = vinv vgrid = Emin Emin = 0 or vL = vinv vgrid = Emax Emin > 0. The last case is critical and may lead to loss of control. Under the same conditions the mode change from mode IV to V is critical. Similarly, if Emax is used for determining the mode changes, at the mode changes from mode II to III and V to VI control can be lost.
E
1
2
265 260 255 250 245 240 235
time (ms)
10
Fig. 8 Simulation results: Polarised Ramptime ZACE current control method and cyclic switching sequence considering intermediate modes, Linv =4 mH, C1 C2 600F, iinv =5 A, (a) control signal (fcontrolsignal 10 kHz), (b)-(e) gate signals for switches a1, b2, c1, d2 (see Fig. 4)(fs 2.5 kHz), (f) unfiltered inverter output current iinv , (g) inverter output voltage vinv , (h) DC bus voltages E1 and E2 .
=
=
^
200
Grid Voltage (V)
E
->
min
Intermediate Modes
->
