A 7-dB 43-GHz CMOS Distributed Amplifier on High ... - IEEE Xplore

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 3, MARCH 2008

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A 7-dB 43-GHz CMOS Distributed Amplifier on High-Resistivity SOI Substrates Christophe Pavageau, Mehdi Si Moussa, Member, IEEE, Jean-Pierre Raskin, Senior Member, IEEE, Danielle Vanhoenaker-Janvier, Senior Member, IEEE, Nicolas Fel, Jean Russat, Laurence Picheta, and François Danneville, Member, IEEE

Abstract—This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity cm) or high-resistivity 1k cm) substrates, and with (10 either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the impact of active device performance and transmission line losses on circuit design by means of simulations, analytical calculations, and comparisons of the small-signal equivalent-circuit parameters. On standard-resistivity substrates, DAs with FB devices and lossy microstrip lines on thin film exhibit a measured gain of 7.1 dB and a unity-gain bandwidth (UGB) of 27 GHz for a dc power consumption of 57 mW. With the introduction of high-resistivity substrates, other DAs, with the same architecture and using lower loss coplanar waveguide lines, show a UGB of 51 GHz with FB devices and 47 GHz with BC devices. To the authors’ knowledge, the designs presented in this paper achieve the best tradeoffs in terms of gain, bandwidth, and power consumption for CMOS-based circuits with comparable architecture.



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Index Terms—CMOS, coplanar waveguides (CPWs), distributed amplifier (DA), microstrip (MS), monolithic microwave integrated circuit (MMIC), silicon-on-insulator (SOI).

I. INTRODUCTION HE distributed amplifier (DA) architecture has been widely used with III–V monolithic microwave integrated circuit (MMIC) technologies to achieve multidecade flat gain for applications in instrumentation, electronic warfare, and broadband optical communication systems. The past years

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Manuscript received March 20, 2007; revised October 8, 2007. This work was performed under the frame of MEDEA T206 and A107 (4G-Radio), both European Economic Community (EEC) projects, and was supported by the French Ministry of Economy, Finance and Industry, by The Walloon Region (Belgium114751), by the Institut d’Electronique et de Microélectronique et de Nanotechnologie, and by the Commissariat à 1’Énergie Atomique. C. Pavageau was with the Institut d’Electronique et de Microélectronique et de Nanotechnologie (IEMN), Unité Mixte de Recherche (UMR), Centre National de la Recherche Scientifique (CNRS) 8520, 59652 Villeneuve d’Ascq, France. He is now with the Interuniversity Microelectronics Centre, 3001 Leuven, Belgium (e-mail: [email protected]). M. Si Moussa, J.-P. Raskin, and D. Vanhoenacker-Janvier are with the Microwave Laboratory, Université catholique de Louvain, 1348 Louvain-la-Neuve, Belgium (e-mail: [email protected]; [email protected]; [email protected]). N. Fel and J. Russat are with the Commissariat à 1’Énergie Atomique, 91680 Bruyères-Le-Châtel, France. L. Picheta and F. Danneville are with the Institut d’Electronique et de Microélectronique et de Nanotechnologie (IEMN), Unité Mixte de Recherche (UMR), Centre National de la Recherche Scientifique (CNRS) 8520, 59652 Villeneuve d’Ascq, France (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2008.916930

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have witnessed the fast increase of silicon technology performance at high frequencies, along with gate-length reduction. At nanometer-scale silicon-on-insulator (SOI)-CMOS transistors and cutoff frequencies higher than 150 GHz exhibit [1], [2], enabling the design of millimeter-wave integrated circuits and especially DAs. Although active device performance rises fast, transmission line losses remain a limiting factor for MMICs in silicon-based technologies. In this paper, designs and measurements of DAs on 130-nm partially depleted (PD) SOI-CMOS technology are presented. This technology offers either conventional floating-body (FB) devices or specific body-contacted (BC) devices, which are free from FB effects such as the kink, and therefore, are suitable for operation in harsh environments [3]. The drawback of BC devices is higher parasitic components, reducing their high-frequency performance compared to FB devices. The first objective was, therefore, to investigate and compare DA performance using both FB and BC devices. Two DAs have been initially manufactured on standard-resistivity substrates (10 cm) with FB and BC devices, and lossy microstrip (MS) lines. They show the same power gain of 6.5 dB at 5 GHz and unity gain cutoff frequencies of 27 and 23 GHz, respectively. Thanks to the introduction of high-resistivity substrates 1 k cm and the use of coplanar waveguide (CPW) lines, DAs with lower losses, and therefore, higher cutoff frequencies, were characterized. They exhibit a measured power gain of 7 dB and unity gain cutoff frequencies of 51 and 47 GHz for FB and BC devices, respectively. II. DEVICE TECHNOLOGY The DA chips were manufactured using a standard 130-nm PD SOI-CMOS process featuring polysilicon resistors, metal–insulator–metal (MIM) capacitors, six copper layers, and an additional top metal layer made of 0.88- m-thick Alucap. cm) or high Unibond substrates with standard resistivity (10 1k cm were available. Detailed information resistivity concerning the technology can be found in [1]. III. ACTIVE DEVICE PERFORMANCE AND MODELING The PD SOI-CMOS technology offers both BC and conventional FB transistors to the designers. FB transistors are high-speed devices but suffer from inherent parasitic phenomena, such as kink and parasitic bipolar effects [3]. On the contrary, the body contact eliminates FB effects by forcing the body potential to the potential of the transistor’s source terminal through a direct contact. In principle, both FB and BC devices have the same intrinsic high-frequency performance

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TABLE I MEASURED EQUIVALENT-CIRCUIT ELEMENTS OF 130-nm SOI FB AND BC DEVICES WITH GATE TOPOLOGY OF 30 FINGERS OF 2 m EACH (V = 1:2 V, I = 176 mA/mm)

and the kink is indeed mainly a low-frequency phenomenon that disappears above 10 MHz [4]. Unfortunately, the body contact of BC devices requires a specific layout, which introduces extra parasitic capacitances and resistances, degrading high-frequency characteristics. For both BC and FB devices, we used a multifingered configuration with 30 gate fingers of 2 m, corresponding to a total gatewidth (W) of 60 m. An Agilent 8510 XF vectorial network analyzer was used for device characterization up to 110 GHz. With a drain–source V and a gate–source voltage V, voltage which correspond to a drain current of 16 mA, FB devices and maximum demonstrate measured peak cutoff frequency oscillation frequency of 89 and 125 GHz, respectively. Under the same dc-bias conditions, BC devices exhibit lower and of 63 and frequency performance with measured 76 GHz. is as follows [5]: A usual expression of (1)

where and are the gate and source resistances , the , the transconductance, nonquasi-static channel resistance and are, respectively, and , the output conductance. the total gate-to-source capacitance and the total gate-to-drain capacitance, both including intrinsic, overlap, and fringing capacitances. Table I summarizes the measured values of the equivalent-circuit elements. A close examination of Table I together with (1) explains the lower frequency performance of BC devices. These of 7.2 , which is devices show an extrinsic gate resistance significantly higher than the 3.2- value extracted for FB devices. They also have a huge increase of the total gate-to-source , which is 79.5 and 48.9 fF for BC and FB decapacitance and vices, respectively. These two major differences on are due to a specific layout of BC compared to FB devices, as illustrated in Figs. 1 and 2. The body contact requires an exten. Moreover, the sion of the polysilicon gate, thus increasing gate–oxide area on top of the active area is also extended, as shown in Fig. 2(a), thus leading to a huge increase of the lateral overlap component of the gate-to-source capacitance. This component is bias-dependent and was estimated between 1 and 2 fF per finger on 250-nm SOI technology [6]. Fig. 3 represents the gate-to-source capacitance extracted from -parameter measurements for both FB and BC devices in 130-nm SOI technology. From these data, we estimated the lateral overlap capacitance value between 0.4–1.15 fF per finger from weak to strong inversion.

Fig. 1. 3-D schematic of FB transistor without any contact to the body (left) and body-contact transistor with an external contact (right).

Fig. 2. BC devices. (a) Cross section. (b) Top view.

Fig. 3. Total gate-to-source capacitance C as a function of drain current density of BC and FB devices (W = 30 2 m, V = 1:2 V).

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For both FB and BC devices, in-house small- and large-signal models were used [4]. Fig. 4 features the equivalent circuit of the small-signal model, whose values were extracted from -parameter measurements [7]. As shown in Fig. 5, model parameters are consistent with measurements for frequencies varying from 0.5 to 50 GHz. The accuracy was estimated using the error equation from [8] as follows:

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Fig. 6. Geometry of CPW (left) and MS (right) transmission lines on SOI substrate.

Fig. 4. Small-signal equivalent circuit of MOSFET.

TABLE II MS LINE CHARACTERISTICS

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Fig. 5. S -parameters of an FB device (W = 30 2 m) for frequencies from 500 MHz to 50 GHz and drain–source current between 100–450 mA/mm (V = 1:2 V). Symbols are used for measurements and solid lines for simulations (error

Fig. 11. Schematic of a four-stage cascode DA.

TABLE V EFFECTIVE PERMITTIVITY AND CORRESPONDING THICKNESS FOR THE SIMPLIFIED CPW LINE STRUCTURE IN HFSS

Correctness of line description in HFSS was ascertained by comparison with measured and modeled -parameters of MS and CPW lines, showing good agreement (Figs. 7 and 9). The transmission line model was implemented in Agilent’s Advanced Design System (ADS) circuit simulation software by extracting -, -, -, and -parameters from the simulated and complex characteristic complex propagation constant [17]. impedance V. DA DESIGN mulation for the effective permittivity tures [16] as follows:

of two-phase mix(3)

and are the complex permittivities of the host and where inclusion phases, and is the volume fraction of the space occupied by the inclusion phase. Fig. 10 gives an example of the simplified structure, and Table V displays the effective permittivity calculations and corresponding thicknesses of the dielectric layers.

A. Architecture DAs can be described as a set of artificial input and output transmission lines coupled through the transconductance of gain stages connected in parallel, as shown in Fig. 11. These artificial lines are constructed with a series of high-impedance transmission lines ( and ), which absorb the input and output capacitances of the different stages to achieve system impedance matching, which is usually 50 . As they are connected to the gate and drain of the transistors, they are referred to as the gate and drain lines. These artificial lines have a very high LC cutoff

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frequency, explaining the inherently wideband characteristics of DAs. The DAs presented in Section VI were designed with the architecture featured in Fig. 11 with either FB or BC devices. They were entirely simulated in Agilent Technologies’ ADS software environment with models described in Sections III and IV. Cascode pairs were used to circumvent the Miller effect of MOSFET transistors [18]. This provides higher power gain, wider bandwidth, improved reverse isolation, and lower gain ripple [19]. Common-source and common-gate transistors of the cascode pair are composed of 30-gate fingers with a width of 2 m each. We determined the optimal number of stages according to the analytical formulation in [20], taking into account the contribution of transmission lines and transistors to the losses of artificial transmission lines. Adding more stages than the required optimal number does not improve the gain, but increases the attenuation. With the MS lines used on this study, the optimal number of stages is four. Instead of integrating biasing networks, we took advantage of the on-wafer measurement setup (cf. Section VI) to apply supply voltages for transistors since these circuits are prototypes intended for technology investigations. Hence, the chip benefits from the broadband decoupling of external bias-tees of the vectorial network analyzer. As a consequence of this, the gate of the common-source transistors and the drain of the common-gate transistors are supplied through the input and output microwave pads, respectively (Fig. 11). A third microwave pad is added laterally for biasing the gate of the common-gate transistors. In addition to the cascode pair, a loss-compensation technique, widely used in III–V technology, was applied to the drain artificial transmission line. This technique lies on the properties of the common-gate transistor of the cascode pair. The real part of its output impedance includes a term that behaves as a broadband and frequency-dependent negative resistance [19]–[21], decreasing the real part of the cascode output impedance that causes losses on the drain artificial line. The compensation is and controlled with two additional transmission lines (Fig. 11). increases the negative part, improving thereby gain at high frequencies, but potentially causing instability if changes the too high values are used. On the other hand, frequency dependence of the negative resistance term and reand values stores circuit stability. A proper selection of enables to obtain a flat frequency response without experiencing stability problems. B. Device Impact on the Cutoff Frequency of the Input Transmission Line The DA’s bandwidth is mainly limited by the cutoff frequency of the artificial gate line, given by [20] (4)

where and are the inductance and capacitance per secis the cascode tion of the physical transmission line, and can be expressed in terms of the pair input capacitance.

Fig. 12. Simulated attenuation per section of gate line and input capacitance of cascode stage loaded by the output line with FB and BC devices and with MS lines. W = 30 2 m and V = 1:4 V.

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small-signal equivalent-circuit elements of the common-source transistors [18] as follows: (5) where is the small-signal voltage gain. As explained in Section III, BC devices have a much higher value than FB devices (Table I) due to a specific layout leading to higher overlap and fringing parasitic capacitances. Therefore, the cutoff frequency of the gate line with BC devices is lower than that with FB devices. capacitance values between However, the difference of BC and FB devices has a reduced impact on the gate line cutoff frequency. It is mainly minored by the Miller effect when calwith (5). In addition, is combined with into culating the physical transmission line to construct the artificial gate line, as shown in (4). This decreases even more the impact of higher values, but it is a second-order contribution on the gate line cutoff frequency compared to the Miller effect. In order to illustrate the consequences on DA design, Fig. 12 represents the simulated values of the attenuation per section and the input capacitance of a casof the gate line code cell (with either FB or BC devices having a total width of 30 2 m). For this simulation, MS line sections of 480- m length and 2- m width were considered with a strip on the Metal-6 layer (cf. Section IV-A). The resulting inductance and capacitance values per section of MS line are 187 pH and 53 fF, respectively. Under these conditions, the simulated 3-dB cutoff frequency of the gate line is 23.5 GHz with BC devices and 26.5 GHz with FB devices, which can also be found analytically by using (4) and (5). In conclusion, whereas BC devices have higher parasitic conand sensibly lower cutoff frequencies tribution on compared to FB devices, this has a minor impact on the cutoff frequency of the artificial gate line. C. Line Losses Influence on GBW Product As mentioned already in Section IV, one of the main challenges in silicon technology is related to transmission line performance. In order to investigate the impact on DA design, we performed simulation as a function of transmission line losses

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Fig. 15. Chip micrograph of the four-stage DA with MS. Circuit area for both DAs is 0.5 1.5 mm .

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Fig. 13. MS line losses using a simplified analytical formula (lines with symbols) and an HFSS simulation (dashed line).

Fig. 16. Measured gain S and isolation S (top), input return loss S and output return loss S (bottom) of DA with MS lines implemented on Metal-6 layer. V = 1:4 V.

Fig. 14. Simulated power gain S (top) and GBW product (bottom) as a function of line losses at 20 GHz for a four-stage cascode DA.

of the four-stage DA with FB devices. We used the MOSFET model presented in Section III and also a simplified transmission line losses model described by the following expression: (6) is the attenuation constant where is the frequency and at a reference frequency . In order to be consistent with the was set at 20 GHz. This model data given in Section IV-C, is accurate enough for our study, as shown in Fig. 13, which compares these calculated line losses with a HFSS simulation. and gainFig. 14 represents the simulated DA’s power gain

bandwidth (GBW) product as a function of line losses. It should be noticed that the DA was optimized according to a criterion of a maximum gain ripple of 0.4 dB in the bandwidth. In addition, the parasitics of the probe pads were not taken into account. As expected, we can observe an increase of the GBW product while line losses decrease. The maximum GBW achievable with the previous described architecture and SOI MOSFET devices is 130 GHz. VI. MEASURED AND SIMULATED RESULTS A. FB Versus BC Devices Based on the architecture previously described, two DAs have been initially manufactured and measured with standard-resiscm) and either FB or BC devices [22]. tivity substrates (10 When designed, high-resistivity substrates, as well as the addition of the Alucap layer on top of the Metal-6 layer, were

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Fig. 17. Chip micrographs of the four-stage DAs on high-resistivity substrates ( 1 k 1 cm) with CPW lines and BC devices (top) and FB devices (bottom). Circuit areas are 0.68 2 2.2 mm and 0.78 2 2.2 mm , respectively.

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Fig. 19. Measured and simulated gain S and isolation S (top), input return loss S and output return loss S (bottom) of DA with FB devices and CPW lines on high-resistivity substrates (>1 k 1 cm), V = 1:8 V.

Fig. 18. Measured gain S and isolation S (top), input return loss S and output return loss S (bottom) of DA with CPW lines on high-resistivity substrates (>1 k 1 cm), V = 1:8 V.

not available, leading us to implement MS lines on the Metal-6 layer. The chip micrograph is shown in Fig. 15. On-wafer measurements were performed using an Anritsu 37369A vectorial network analyzer operating up to 40 GHz. The input and output pads were not calibrated out so that measured results include additional parasitic effects due to RF pads. V with a Fig. 16 shows measured -parameters at bias current of 41 mA. The DA with BC devices exhibits an average gain of 5.4 1.4 dB from 1 to 20 GHz with a unity-gain

bandwidth (UGB) of 23 GHz, whereas the second DA with FB devices shows an average gain of 7.1 1.1 dB from 1 to 25 GHz with a UGB of 27 GHz. Input and output return losses are better than 8 dB up to 20 GHz. The measured noise figure is 6.5–7.5 dB over 6–20 GHz for both DAs. The large deviation with respect to the average gain, is due to the tuning of the loss-compensation circuit. Inaccurate transmission line models, when both DAs were designed, led to an overcompensation for the DA with FB and an under-compensation for the DA with BC devices. It should also be noticed that both amplifiers exhibit the same gain for frequencies under 5 GHz, which is 6.5 dB. This can be easily explained as both devices have approximately the same transconductance value (Table I), leading to the same low-frequency gain for both DAs. An analytical expression of this gain can be found in [20]. Indeed, the only noticeable difference between both DAs concerns the bandwidth, which is explained in Section V-B. Simulations of these DAs are available in [22], showing excellent agreement with measurements. These simulation were performed using corrected models corresponding to actual layouts. B. Gain-Bandwidth Enhancement With CPW Line on High-Resistivity Substrates Based on the good convergence observed between simulations and measurements, two DAs with the previous architecture were designed using CPW lines on high-resistivity substrates 1 k cm , as described in Section IV. Chip micrographs are shown in Fig. 17.

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TABLE VI STATE-OF-THE-ART OF CASCODE DAs

On-wafer measurements were performed using an Agilent 8510 XF vectorial network analyzer operating up to 110 GHz for the DA with FB devices. The particular pad configuration of the second DA with BC devices (Fig. 17) required the use of another measurement setup with dual probes and an Agilent 8510C vectorial network analyzer operating up to 50 GHz. V with a Fig. 18 shows measured -parameters at bias current of 42 mA. The DA with BC devices has an average gain of 7 0.5 dB from 1 to 43 GHz. The magnitude of the input and output reflection coefficients is better than 8 and 6 dB up to 40 GHz. The DA with FB devices has an average gain of 7 1.6 dB from 1 to 40 GHz. Input and output reflection coefficients are better than 9 and 6 dB up to 40 GHz, respectively. The highest gain ripple of the DA with FB devices is due to an under-compensation of the output line losses. It should be noticed that the DA with FB devices has a higher UGB than the DA with BC devices, with values of 51 and 47 GHz, respectively,

while both exhibit the same low-frequency gain. The small difference of UGB with respect to the large difference of devices cutoff frequencies is explained in Section V-B. The use of CPW lines on high-resistivity substrates, with lower loss compared to MS lines, leads to an enlarged DA operational bandwidth with a twofold increase. Fig. 19 shows the simulated -parameters of the DA with FB devices and CPW lines. An excellent agreement with measurements is achieved. VII. STATE-OF-THE-ART OF CMOS DAs Table VI summarizes the performance achieved in this study and eases the comparison with other state-of-the-art cascode DAs fabricated with both bulk or SOI CMOS technologies and III–V technologies. Particular attention is paid to the gain and bandwidth performance with respect to the dc power consumption, active devices performance, and passives technology. It should be mentioned that most of the published data in III–V

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technologies concern commercial products, contrary to CMOS results, which concern mainly prototype circuits for technology benchmarking. A first factor-of-merit (FOM) is the GBW product taking into account the gain and the 3-dB cutoff frequency. Most of the published results in Table VI do not provide the 3-dB cutoff frequency, but the UGB instead. Therefore, a slightly modify definition of the GBW was considered, replacing the 3-dB cutoff frequency by the UGB. The 120-nm SOI-CMOS DAs from [32], [33] achieve the best performance with this criterion for a CMOS chip, but it should be mentioned that these designs use aggressive gate-length shrinkage, with 60-nm gate-length cutoff frequencies and devices, leading to higher wider operating bandwidth. With respect to the technology performance, our designs with CPW lines and BC transistors achieve fairly good performance compared to other designs in more advanced SOI technology and better performance compared to designs in 180-nm bulk CMOS technology. To go further in comparison, another FOM was defined based on the previous one. In this FOM, we normalize the power gain and the UGB to the cutoff freto the power consumption quency of the active device. This factor enables to have an insight of the DA performance related to the technology. Its main advantages are to compare linked parameters and to be independent of architectural choices such as the number of stages, which increase the gain, but also the power dissipation. According to this criterion, our design with CPW lines and BC devices achieves better tradeoffs than other designs in CMOS, and comparable tradeoffs with the circuit in InP HBT technology [26]. For a long time, III–V technologies have been achieving very high gain and high-frequency performance, together with very high power consumption and high-voltage operation [23]. This last feature is more difficult to achieve for CMOS chips due to the low breakdown voltage of MOSFET devices. VIII. CONCLUSION Designs and measurements of DAs in a 130-nm SOI-CMOS cm) process have been presented on standard-resistivity (10 and high-resistivity 1 k cm substrates using either FB or BC devices. Initially, two DAs have been manufactured on standard-resistivity substrates with both FB and BC devices and lossy MS lines (1 dB/mm at 20 GHz). They show an average gain of 7.1 and 5.4 dB, respectively, and UGB of 27 and 23 GHz, respectively. DAs with either FB or BC devices exhibit nearly the same bandwidth, despite significant differences between devices in and cutoff frequencies. We have analytically shown that capacitance of BC dethe higher parasitic contribution on vices indeed has a minor impact on the bandwidth, compared to the Miller effect, which affects both devices and has a paramount impact. It has also been shown, both experimentally and analytically, that transmission line losses on silicon are the main limiting factor for gain and bandwidth performance. Careful design engineering of transmission lines enables significant performance improvement and the possibility to reach the maximum GBW product for 130-nm SOI transistors. We took advantage of the availability of high-resistivity substrates 1 k cm to realize

other DAs with low-loss CPW lines and FB and BC devices. Measurements exhibit an average gain of 7 dB for both circuits, and a twofold increase of the bandwidth with a UGB of 51 and 47 GHz with FB and BC, respectively. To the best of the authors’ knowledge, the designs presented in this paper achieve the best tradeoffs for a CMOS technology in terms of gain, bandwidth, and power consumption with respect to the used technology performance. Furthermore, it demonstrates the suitability of the 130-nm SOI-CMOS process for microwave and millimeter-wave operation. ACKNOWLEDGMENT The authors thank P. Simon, Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, and S. Lepillet, Institut d’Electronique et de Microélectronique et de Nanotechnologie (IEMN), Villeneuve d’Ascq, France, for measurements setup. The chips were manufactured by ST-Microelectronics, Crolles, France. REFERENCES [1] C. Raynaud et al., “Is CMOS a promising technology for SOCs in high frequency range?,” in 12th Int. SOI Symp. of 207th Electrochem. Soc. Meeting, Quebec City, QC, Canada, May 15–20, 2005, pp. 331–344. [2] L. Sungjae, L. Wagner, B. Jagannathan, S. Csutak, J. Pekarik, N. Zamdmer, M. Breitwisch, R. Ramachandran, and G. Freeman, “Record NFETs in microprocessor SOI RF performance of sub-46 nm L CMOS technologies,” in IEEE Int. Electron Devices Meeting, Dec. 2005, pp. 241–244. [3] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 2nd ed. Norwell, MA: Kluwer, 1997. [4] F. Danneville, G. Pailloncy, A. Siligaris, D. Gloria, and G. Dambrine, “Linear, noise and nonlinear HF models for advanced CMOS technology,” in 1st Eur. Microw. Integrated Circuits Conf., Sep. 10–13, 2006, pp. 209–212. [5] G. Dambrine, C. Raynaud, D. Lederer, M. Dehan, O. Rozeaux, M. Vanmackelberg, F. Danneville, S. Lepillet, and J.-P. Raskin, “What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?,” IEEE Electron Devices Lett., vol. 24, no. 3, pp. 189–191, Mar. 2003. [6] A. Bracale, “Caractérisation et modélisation des transistors MOS sur substrat SOI pour des applications micro-ondes,” Ph.D. dissertation, Dept. RF Modeling and Design, Univ. Pierre et Marie Curie Paris VI, Paris, France, 2001. [7] G. Dambrine, J.-P. Raskin, F. Danneville, D. Vanhoenacker-Janvier, J.-P. Colinge, and A. y. Capp, “High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits,” IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1733–1741, Aug. 1999. [8] D. Lovelace, J. Costa, and N. Camilleri, “Extracting small-signal model parameters of silicon MOSFET transistors,” Microw. RF, pp. 865–868, 1994. [9] C. P. Wen, “Coplanar waveguide: A surface strip transmission line suitable for nonreciprocal gyromagnetic device applications,” IEEE Trans. Microw. Theory Tech., vol. MTT-17, no. 12, pp. 1087–1090, Dec. 1969. [10] G. Six, M. Vanmackelberg, H. Happy, G. Dambrine, S. Boret, and D. Gloria, “Transmission lines on low resistivity silicon substrates for MMIC’s applications,” in Proc. 31th Eur. Microw. Conf., 2001, vol. 2, pp. 193–196. [11] W. Durr, U. Erben, A. Schuppen, H. Dietrich, and H. Schumacher, “Investigation of microstrip and coplanar transmission lines on lossy silicon substrates without backside metallization,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 712–715, May 1998. [12] W. Heinrich, J. Gerdes, F. J. Schmuckle, C. Rheinfelder, and K. Strohm, “Coplanar passive elements on Si substrate for frequencies up to 110 GHz,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 709–712, May 1998. [13] G. E. Ponchak, “RF transmission lines on silicon substrates,” in Proc. 29th Eur. Microw. Conf., 1999, pp. 158–161.

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[14] S. Montusclat, F. Gianesello, D. Gloria, and S. Tedjini, “Silicon integrated antenna developments up to 80 GHz for millimeter wave wireless links,” in Proc. 35th Eur. Microw. Conf., 2005, vol. 3, pp. 4–7. [15] C. Warns, W. Menzel, and H. Schumacher, “Transmission lines and passive elements for multilayer coplanar circuits on silicon,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 612–622, May 1998. [16] A. Kraszewski, “Prediction of the dielectric properties of two phases mixtures,” J. Microw. Power, vol. 12, no. 3, pp. 215–215, 1977. [17] G. Gonzales, Microwave Transistor Amplifiers, 1st ed. Englewood Cliffs, NJ: Prentice-Hall, 1984, pp. 5–5. [18] L. D. Jackel, R. G. Swartz, R. E. Howard, P.-K. Ko, and P. Grabbe, “CASFET: A MOSFET-JFET cascode device with ultralow gate capacitance,” IEEE Trans. Electron Devices, vol. 31, no. 12, pp. 1752–1758, Dec. 1984. [19] S. Deibele and J. B. Beyer, “Attenuation compensation in distributed amplifier design,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 9, pp. 1425–1433, Sep. 1989. [20] J. B. Beyer, S. N. Prasad, R. C. Becker, J. E. Nordman, and G. K. Hohenwarter, “MESFET distributed amplifier design guidelines,” IEEE Trans. Microw. Theory Tech., vol. MTT-32, no. 3, pp. 268–275, Mar. 1984. [21] S. Kimura, Y. Imai, Y. Umeda, and T. Enoki, “Loss-compensated distributed baseband amplifier IC’s for optical transmission systems,” IEEE Trans. Microw. Theory Tech., vol. 44, no. 10, pp. 1688–1693, Oct. 1996. [22] C. Pavageau, M. S. Moussa, A. Siligaris, L. Picheta, F. Danneville, J. P. Raskin, D. Vanhoenaker-Janvier, J. Russat, and N. Fel, “Low power 23-GHz and 27-GHz distributed cascode amplifiers in a standard 130 nm SOI CMOS process,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 11–17, 2005, 4 pp. [23] J. M. Carroll, A. Coutant, M. S. Heins, C. F. Campbell, and E. Reese, “0.25 m pHEMT 40 Gb/s E/O modulator drivers,” in IEEE MTT-S Int. Microw. Symp. Dig., 2002, pp. 489–492. [24] C. Meliani, G. Post, J. Decobert, W. Mouzannar, G. Rondeau, E. Dutisseuil, and R. Lefevre, “92 GHz cut-off frequency InP double channel HEMT based coplanar distributed amplifier for 40 Gbit/s applications and beyond,” in Proc. 28th Eur. Solid-State Circuits Conf., 2002, pp. 615–617. [25] R. E. Leoni, III, S. J. Lichwala, J. G. Hunt, C. S. Whelan, P. F. Marsh, W. E. Hoke, and T. E. Kazior, “A DC–45 GHz metamorphic HEMT traveling wave amplifier,” in Gallium Arsenide Integrated Circuit (GaAs IC) Symp. Dig., 2001, pp. 133–136. [26] Y. Baeyens, R. Pullela, J. P. Mattia, H.-S. Tsai, and Y.-K. Chen, “A 74-GHz bandwidth InAlAs/InGaAs–InP HBT distributed amplifier with 13-dB gain,” IEEE Microw. Guided Wave Lett., vol. 9, pp. 461–463, Nov. 1999. [27] R.-C. Liu, K.-L. Deng, and H. Wang, “A 0.6–22-GHz broadband CMOS distributed amplifiers,” in IEEE Radio Freq. Integrated Symp. Dig., 2003, pp. 103–106. [28] R. E. Amaya, N. G. Tarr, and C. Plett, “A 27 GHz fully integrated CMOS distributed amplifier using coplanar waveguides,” in IEEE Radio Freq. Integrated Symp. Dig., 2004, pp. 193–196. [29] R. E. Amaya, J. Aguirre, and C. Plett, “Gain bandwidth considerations in fully integrated distributed amplifiers implemented in silicon,” in IEEE Int. Circuits Syst. Symp. Dig., 2004, pp. IV-273–IV-276. [30] H. Shigematsu, M. Sato, I. Hirose, F. Brewer, and M. Rodwell, “40 Gb/s CMOS distributed amplifier for fiber-optic communication systems,” in IEEE Int. Solid-Circuits Conf. Dig., 2004, vol. 1, pp. 476–540. [31] L.-H. Lu, T.-Y. Chen, and Y.-J. Lin, “A 32-GHz non-uniform distributed amplifier in 0.18-mm CMOS,” Microw. Wireless Compon. Lett., vol. 15, no. 11, pp. 754–747, Nov. 2005. [32] J. Kim, J.-O. Plouchart, N. Zamdmer, R. Trzcinski, R. Groves, M. Sherony, Y. Tan, M. Talbi, J. Safran, and L. Wagner, “A 12 dBm 320 GHz GBW distributed amplifier in a 0.12 m SOI CMOS,” in IEEE Int. Solid-Circuits Conf. Dig., 2004, vol. 1, pp. 478–540. [33] J.-O. Plouchard, J. Kim, N. Zamdmer, L. Liang-Hung, M. Sherony, Y. Tan, R. Groves, R. Trzcinski, M. Talbi, A. Ray, and L. Wagner, “A 4–91-GHz traveling-wave amplifier in standard 0.12-m SOI CMOS microprocessor technology,” IEEE J. Solid-States Circuit, vol. 39, no. 9, pp. 1455–1461, Sep. 2004. [34] F. Ellinger, “60-GHz SOI CMOS travelling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 553–558, Feb. 2005.

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Christophe Pavageau was born in Angers, France, in 1979. He received the Engineers degree in electrical engineering from the Ecole Supérieure d’Electronique de 1’Ouest, Angers, France, in 2002, the M.S. degree in microelectronics and microtechnologies from Rennes I University, Rennes, France, in 2002, and the Ph.D. degree (with Honors) from Lille-I University, Lille, France, in 2005. From 2002 to 2005, he was with the Institut d’Electronique et de Microélectronique et de Nanotechnologie (IEMN), Villeneuve d’Ascq, France, and the Commisariat à 1’Energie Atomique, Bruyères-le-Châtel, France, as a doctoral student involved with the modeling of SOI MOSFETs and transmission lines and with the design of SOI CMOS microwave integrated circuits. In November 2005, he joined the Microsystems Components and Packaging Group, Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium, where he is involved with the design of CMOS 45-nm circuits with above-IC technology for 60-GHz applications.

Mehdi Si Moussa (S’03–A’06–M’08) was born in Skikda, Algeria, in 1977. He received the State Engineering degree in electronics and Magister degree in microwave and communication from the Ecole Nationale Polytechnique (ENP), Algiers, Algeria, in 1999 and 2001, respectively, and the Ph.D. degree in applied sciences from the Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 2006. His doctoral research concerned the design of microwave DAs and oscillators on SOI CMOS technology. Since 2002, he has been a Research Assistant with the Microwave Laboratory (EMIC), UCL. His research interests include simulation, design, and modeling of RF and microwave circuits in SOI CMOS technology for wideband and hightemperature applications. He is currently involved in the design of microwave low-noise amplifiers (LNAs) in SOI CMOS technology for low-power hightemperature applications.

Jean-Pierre Raskin (M’97–SM’06) was born in Aye, Belgium, in 1971. He received the Industrial Engineer degree from the Institut Supérieur Industriel d’Arlon, Arlon, Belgium, in 1993, and the M.S. and Ph.D. degrees in applied sciences from the Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively. From 1994 to 1997, he was a Research Engineer with the Microwave Laboratory, UCL, where he was involved with the modeling, characterization, and realization of MMICs in SOI technology for low-power low-voltage applications. In 1998, he joined the Electrical Engineering and Computer Science Department, The University of Michigan at Ann Arbor, where he was involved in the development and characterization of micromachining fabrication techniques for microwave and millimeter-wave circuits and microelectromechanical transducers/amplifiers working in hard environments. In 2000, he joined the Microwave Laboratory, UCL, as an Associate Professor. Since 2007, he has been Professor and Head of the Microwave Laboratory, UCL. He is a member of the Research Center in Micro and Nanoscopic Materials and Electronic Devices, UCL. He has authored or coauthored over 350 scientific papers. His research interests are the modeling, wideband characterization, and fabrication of advanced SOI MOSFETs, as well as microfabrication and nanofabrication of microelectromechanical systems (MEMS)/nanoelectromechanical systems (NEMS) sensors and actuators. Dr. Raskin is an European Microwave Association (EuMA) associate member.

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Danielle Vanhoenacker-Janvier (M’88–SM’90) received the Electrical Engineer degree and Ph.D. degree in applied sciences from the Université Catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1978 and 1987, respectively. She is currently with the UCL, where she was an Assistant (1979–1987), Senior Scientist (1987–1994), Associate Professor (1994–2000), Professor (2000–2007), and Full Professor (2007) with the Microwave Laboratory. From 2001 to 2007, she was Head of the Microwave Laboratory. She has been involved in the study of atmospheric effects on propagation above 10 GHz for over 30 years and she is also interested in the analysis and modeling of the mobile propagation channel and the evaluation of its impact on communication systems. In 1989, she extended her research activity to microwave circuits. She is involved in the analysis, design, and measurement of microwave planar passive and active circuits with a special interest, since 1994, in microwave integrated circuits on SOI. She has authored over 140 technical papers and coauthored a book. She is a reviewer for various international conferences and journals. Dr. Vanhoenacker-Janvier is a member of evaluation committees for grants and projects at Innovatie door Wetenschap en Technologie (IWT) since 1997, and at Fonds door Wetenschappelijk Onderzoek (FWO) and Fonds pour la formation à la Recherche dans l’Industrie et l’Agriculture (FRIA) since 2001. She is member of the evaluation committee of various laboratories and research centers (IRCTR, TUDelft, NL, ECIME–ENSEA, SMARAD, TKK). She is also a reviewer for various IEEE journals.

Nicolas Fel was born in Tours, France, on March 2, 1966. He received the Doctorate degree in physics from the Institut d’Électronique Fondamentale (IEF), University of Paris XI, Orsay, France, in 1993. His doctoral research concerned GaAs high-speed and high-resolution DACs. Since 1993, he has been a Research Engineer with the Commissariat à 1’Énergie Atomique (CEA), Bruyères-Le-Châtel, France, where he is involved in the design of mixed-mode or RF integrated circuits using either silicon or III–V advanced technologies.

Jean Russat was born in Arcachon, France, on January 3, 1959. He received the Doctorate degree in microelectronics and microcomputing from the Laboratory of Solid State Physics, Ecole Normale Supérieure, University of Paris VII, Paris, France, in 1987. His doctoral research concerned the formation of polyamic acid and polyimide/metal interfaces. Since 1989, he has been with the Commissariat à 1’Énergie Atomique (CEA), Bruyères-Le-Châtel, France, where he has been involved in research projects dedicated to various physics areas such as solid-state physics, antennas, and high-frequency electronics. He currently heads a laboratory involved with the design of integrated circuits.

Laurence Picheta was born in Lens, France, 1966. She received the Ph.D. Degrees in electrical engineering from University of Lille, Lille, France, in 1994. Since 1995, she has been an Associate Professor with the University of Lille. Her research is carried out at the Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN), Villeneuve d’Ascq, France. Her research was first related to devices and circuits in III–V technology [frequency converters using cold field-effect transistors (FETs)], and more recently, devices and circuits using advanced silicon technology (SOI).

François Danneville (M’98) was born in Ham, France, in 1964. In 1991, he became an Associate Professor with the University of Lille, Lille, France. Until 2001, his research has been carried out at the Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN), Villeneuve d’Ascq, France, where he studied the noise properties of III–V devices operating in linear and nonlinear regimes for application in centrimetric and millimetric wave range. In 1998, he was a Visitor (noise expertise) with the EEsof Division, Hewlett-Packard Company (now Agilent Technologies) Santa Rosa, CA. Since 2001, he has been a Full Professor with the University of Lille. His research at the IEMN is oriented toward advanced silicon devices and circuits, which includes the dynamic, noise, and linearity properties of MOSFET-based devices (including alternative architectures), SiGe HBTs and circuit design in millimetric wave range using SOI technology, and SiGe BiCMOS technology.